1 /* 2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time 3 * chips. 4 * 5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>. 6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>. 7 * 8 * References: 9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. 10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. 11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. 12 * Application Note 90, Using the Multiplex Bus RTC Extended Features. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/bcd.h> 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/rtc.h> 27 #include <linux/workqueue.h> 28 29 #include <linux/rtc/ds1685.h> 30 31 #ifdef CONFIG_PROC_FS 32 #include <linux/proc_fs.h> 33 #endif 34 35 36 /* ----------------------------------------------------------------------- */ 37 /* Standard read/write functions if platform does not provide overrides */ 38 39 /** 40 * ds1685_read - read a value from an rtc register. 41 * @rtc: pointer to the ds1685 rtc structure. 42 * @reg: the register address to read. 43 */ 44 static u8 45 ds1685_read(struct ds1685_priv *rtc, int reg) 46 { 47 return readb((u8 __iomem *)rtc->regs + 48 (reg * rtc->regstep)); 49 } 50 51 /** 52 * ds1685_write - write a value to an rtc register. 53 * @rtc: pointer to the ds1685 rtc structure. 54 * @reg: the register address to write. 55 * @value: value to write to the register. 56 */ 57 static void 58 ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) 59 { 60 writeb(value, ((u8 __iomem *)rtc->regs + 61 (reg * rtc->regstep))); 62 } 63 /* ----------------------------------------------------------------------- */ 64 65 66 /* ----------------------------------------------------------------------- */ 67 /* Inlined functions */ 68 69 /** 70 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD. 71 * @rtc: pointer to the ds1685 rtc structure. 72 * @val: u8 time value to consider converting. 73 * @bcd_mask: u8 mask value if BCD mode is used. 74 * @bin_mask: u8 mask value if BIN mode is used. 75 * 76 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE. 77 */ 78 static inline u8 79 ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask) 80 { 81 if (rtc->bcd_mode) 82 return (bcd2bin(val) & bcd_mask); 83 84 return (val & bin_mask); 85 } 86 87 /** 88 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD. 89 * @rtc: pointer to the ds1685 rtc structure. 90 * @val: u8 time value to consider converting. 91 * @bin_mask: u8 mask value if BIN mode is used. 92 * @bcd_mask: u8 mask value if BCD mode is used. 93 * 94 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE. 95 */ 96 static inline u8 97 ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask) 98 { 99 if (rtc->bcd_mode) 100 return (bin2bcd(val) & bcd_mask); 101 102 return (val & bin_mask); 103 } 104 105 /** 106 * s1685_rtc_check_mday - check validity of the day of month. 107 * @rtc: pointer to the ds1685 rtc structure. 108 * @mday: day of month. 109 * 110 * Returns -EDOM if the day of month is not within 1..31 range. 111 */ 112 static inline int 113 ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday) 114 { 115 if (rtc->bcd_mode) { 116 if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09) 117 return -EDOM; 118 } else { 119 if (mday < 1 || mday > 31) 120 return -EDOM; 121 } 122 return 0; 123 } 124 125 /** 126 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. 127 * @rtc: pointer to the ds1685 rtc structure. 128 */ 129 static inline void 130 ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) 131 { 132 rtc->write(rtc, RTC_CTRL_A, 133 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); 134 } 135 136 /** 137 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. 138 * @rtc: pointer to the ds1685 rtc structure. 139 */ 140 static inline void 141 ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) 142 { 143 rtc->write(rtc, RTC_CTRL_A, 144 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); 145 } 146 147 /** 148 * ds1685_rtc_begin_data_access - prepare the rtc for data access. 149 * @rtc: pointer to the ds1685 rtc structure. 150 * 151 * This takes several steps to prepare the rtc for access to get/set time 152 * and alarm values from the rtc registers: 153 * - Sets the SET bit in Control Register B. 154 * - Reads Ext Control Register 4A and checks the INCR bit. 155 * - If INCR is active, a short delay is added before Ext Control Register 4A 156 * is read again in a loop until INCR is inactive. 157 * - Switches the rtc to bank 1. This allows access to all relevant 158 * data for normal rtc operation, as bank 0 contains only the nvram. 159 */ 160 static inline void 161 ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) 162 { 163 /* Set the SET bit in Ctrl B */ 164 rtc->write(rtc, RTC_CTRL_B, 165 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); 166 167 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ 168 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) 169 cpu_relax(); 170 171 /* Switch to Bank 1 */ 172 ds1685_rtc_switch_to_bank1(rtc); 173 } 174 175 /** 176 * ds1685_rtc_end_data_access - end data access on the rtc. 177 * @rtc: pointer to the ds1685 rtc structure. 178 * 179 * This ends what was started by ds1685_rtc_begin_data_access: 180 * - Switches the rtc back to bank 0. 181 * - Clears the SET bit in Control Register B. 182 */ 183 static inline void 184 ds1685_rtc_end_data_access(struct ds1685_priv *rtc) 185 { 186 /* Switch back to Bank 0 */ 187 ds1685_rtc_switch_to_bank1(rtc); 188 189 /* Clear the SET bit in Ctrl B */ 190 rtc->write(rtc, RTC_CTRL_B, 191 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); 192 } 193 194 /** 195 * ds1685_rtc_get_ssn - retrieve the silicon serial number. 196 * @rtc: pointer to the ds1685 rtc structure. 197 * @ssn: u8 array to hold the bits of the silicon serial number. 198 * 199 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The 200 * first byte is the model number, the next six bytes are the serial number 201 * digits, and the final byte is a CRC check byte. Together, they form the 202 * silicon serial number. 203 * 204 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be 205 * called first before calling this function, else data will be read out of 206 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done. 207 */ 208 static inline void 209 ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) 210 { 211 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL); 212 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1); 213 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2); 214 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3); 215 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4); 216 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5); 217 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6); 218 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC); 219 } 220 /* ----------------------------------------------------------------------- */ 221 222 223 /* ----------------------------------------------------------------------- */ 224 /* Read/Set Time & Alarm functions */ 225 226 /** 227 * ds1685_rtc_read_time - reads the time registers. 228 * @dev: pointer to device structure. 229 * @tm: pointer to rtc_time structure. 230 */ 231 static int 232 ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) 233 { 234 struct ds1685_priv *rtc = dev_get_drvdata(dev); 235 u8 ctrlb, century; 236 u8 seconds, minutes, hours, wday, mday, month, years; 237 238 /* Fetch the time info from the RTC registers. */ 239 ds1685_rtc_begin_data_access(rtc); 240 seconds = rtc->read(rtc, RTC_SECS); 241 minutes = rtc->read(rtc, RTC_MINS); 242 hours = rtc->read(rtc, RTC_HRS); 243 wday = rtc->read(rtc, RTC_WDAY); 244 mday = rtc->read(rtc, RTC_MDAY); 245 month = rtc->read(rtc, RTC_MONTH); 246 years = rtc->read(rtc, RTC_YEAR); 247 century = rtc->read(rtc, RTC_CENTURY); 248 ctrlb = rtc->read(rtc, RTC_CTRL_B); 249 ds1685_rtc_end_data_access(rtc); 250 251 /* bcd2bin if needed, perform fixups, and store to rtc_time. */ 252 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK, 253 RTC_YEAR_BIN_MASK); 254 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK, 255 RTC_CENTURY_MASK); 256 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK, 257 RTC_SECS_BIN_MASK); 258 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK, 259 RTC_MINS_BIN_MASK); 260 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK, 261 RTC_HRS_24_BIN_MASK); 262 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK, 263 RTC_WDAY_MASK) - 1); 264 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, 265 RTC_MDAY_BIN_MASK); 266 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK, 267 RTC_MONTH_BIN_MASK) - 1); 268 tm->tm_year = ((years + (century * 100)) - 1900); 269 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); 270 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ 271 272 return 0; 273 } 274 275 /** 276 * ds1685_rtc_set_time - sets the time registers. 277 * @dev: pointer to device structure. 278 * @tm: pointer to rtc_time structure. 279 */ 280 static int 281 ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) 282 { 283 struct ds1685_priv *rtc = dev_get_drvdata(dev); 284 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century; 285 286 /* Fetch the time info from rtc_time. */ 287 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK, 288 RTC_SECS_BCD_MASK); 289 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK, 290 RTC_MINS_BCD_MASK); 291 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK, 292 RTC_HRS_24_BCD_MASK); 293 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK, 294 RTC_WDAY_MASK); 295 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK, 296 RTC_MDAY_BCD_MASK); 297 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK, 298 RTC_MONTH_BCD_MASK); 299 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100), 300 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK); 301 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100), 302 RTC_CENTURY_MASK, RTC_CENTURY_MASK); 303 304 /* 305 * Perform Sanity Checks: 306 * - Months: !> 12, Month Day != 0. 307 * - Month Day !> Max days in current month. 308 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. 309 */ 310 if ((tm->tm_mon > 11) || (mday == 0)) 311 return -EDOM; 312 313 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) 314 return -EDOM; 315 316 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || 317 (tm->tm_sec >= 60) || (wday > 7)) 318 return -EDOM; 319 320 /* 321 * Set the data mode to use and store the time values in the 322 * RTC registers. 323 */ 324 ds1685_rtc_begin_data_access(rtc); 325 ctrlb = rtc->read(rtc, RTC_CTRL_B); 326 if (rtc->bcd_mode) 327 ctrlb &= ~(RTC_CTRL_B_DM); 328 else 329 ctrlb |= RTC_CTRL_B_DM; 330 rtc->write(rtc, RTC_CTRL_B, ctrlb); 331 rtc->write(rtc, RTC_SECS, seconds); 332 rtc->write(rtc, RTC_MINS, minutes); 333 rtc->write(rtc, RTC_HRS, hours); 334 rtc->write(rtc, RTC_WDAY, wday); 335 rtc->write(rtc, RTC_MDAY, mday); 336 rtc->write(rtc, RTC_MONTH, month); 337 rtc->write(rtc, RTC_YEAR, years); 338 rtc->write(rtc, RTC_CENTURY, century); 339 ds1685_rtc_end_data_access(rtc); 340 341 return 0; 342 } 343 344 /** 345 * ds1685_rtc_read_alarm - reads the alarm registers. 346 * @dev: pointer to device structure. 347 * @alrm: pointer to rtc_wkalrm structure. 348 * 349 * There are three primary alarm registers: seconds, minutes, and hours. 350 * A fourth alarm register for the month date is also available in bank1 for 351 * kickstart/wakeup features. The DS1685/DS1687 manual states that a 352 * "don't care" value ranging from 0xc0 to 0xff may be written into one or 353 * more of the three alarm bytes to act as a wildcard value. The fourth 354 * byte doesn't support a "don't care" value. 355 */ 356 static int 357 ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 358 { 359 struct ds1685_priv *rtc = dev_get_drvdata(dev); 360 u8 seconds, minutes, hours, mday, ctrlb, ctrlc; 361 int ret; 362 363 /* Fetch the alarm info from the RTC alarm registers. */ 364 ds1685_rtc_begin_data_access(rtc); 365 seconds = rtc->read(rtc, RTC_SECS_ALARM); 366 minutes = rtc->read(rtc, RTC_MINS_ALARM); 367 hours = rtc->read(rtc, RTC_HRS_ALARM); 368 mday = rtc->read(rtc, RTC_MDAY_ALARM); 369 ctrlb = rtc->read(rtc, RTC_CTRL_B); 370 ctrlc = rtc->read(rtc, RTC_CTRL_C); 371 ds1685_rtc_end_data_access(rtc); 372 373 /* Check the month date for validity. */ 374 ret = ds1685_rtc_check_mday(rtc, mday); 375 if (ret) 376 return ret; 377 378 /* 379 * Check the three alarm bytes. 380 * 381 * The Linux RTC system doesn't support the "don't care" capability 382 * of this RTC chip. We check for it anyways in case support is 383 * added in the future and only assign when we care. 384 */ 385 if (likely(seconds < 0xc0)) 386 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, 387 RTC_SECS_BCD_MASK, 388 RTC_SECS_BIN_MASK); 389 390 if (likely(minutes < 0xc0)) 391 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes, 392 RTC_MINS_BCD_MASK, 393 RTC_MINS_BIN_MASK); 394 395 if (likely(hours < 0xc0)) 396 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours, 397 RTC_HRS_24_BCD_MASK, 398 RTC_HRS_24_BIN_MASK); 399 400 /* Write the data to rtc_wkalrm. */ 401 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, 402 RTC_MDAY_BIN_MASK); 403 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); 404 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); 405 406 return 0; 407 } 408 409 /** 410 * ds1685_rtc_set_alarm - sets the alarm in registers. 411 * @dev: pointer to device structure. 412 * @alrm: pointer to rtc_wkalrm structure. 413 */ 414 static int 415 ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 416 { 417 struct ds1685_priv *rtc = dev_get_drvdata(dev); 418 u8 ctrlb, seconds, minutes, hours, mday; 419 int ret; 420 421 /* Fetch the alarm info and convert to BCD. */ 422 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec, 423 RTC_SECS_BIN_MASK, 424 RTC_SECS_BCD_MASK); 425 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min, 426 RTC_MINS_BIN_MASK, 427 RTC_MINS_BCD_MASK); 428 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour, 429 RTC_HRS_24_BIN_MASK, 430 RTC_HRS_24_BCD_MASK); 431 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday, 432 RTC_MDAY_BIN_MASK, 433 RTC_MDAY_BCD_MASK); 434 435 /* Check the month date for validity. */ 436 ret = ds1685_rtc_check_mday(rtc, mday); 437 if (ret) 438 return ret; 439 440 /* 441 * Check the three alarm bytes. 442 * 443 * The Linux RTC system doesn't support the "don't care" capability 444 * of this RTC chip because rtc_valid_tm tries to validate every 445 * field, and we only support four fields. We put the support 446 * here anyways for the future. 447 */ 448 if (unlikely(seconds >= 0xc0)) 449 seconds = 0xff; 450 451 if (unlikely(minutes >= 0xc0)) 452 minutes = 0xff; 453 454 if (unlikely(hours >= 0xc0)) 455 hours = 0xff; 456 457 alrm->time.tm_mon = -1; 458 alrm->time.tm_year = -1; 459 alrm->time.tm_wday = -1; 460 alrm->time.tm_yday = -1; 461 alrm->time.tm_isdst = -1; 462 463 /* Disable the alarm interrupt first. */ 464 ds1685_rtc_begin_data_access(rtc); 465 ctrlb = rtc->read(rtc, RTC_CTRL_B); 466 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); 467 468 /* Read ctrlc to clear RTC_CTRL_C_AF. */ 469 rtc->read(rtc, RTC_CTRL_C); 470 471 /* 472 * Set the data mode to use and store the time values in the 473 * RTC registers. 474 */ 475 ctrlb = rtc->read(rtc, RTC_CTRL_B); 476 if (rtc->bcd_mode) 477 ctrlb &= ~(RTC_CTRL_B_DM); 478 else 479 ctrlb |= RTC_CTRL_B_DM; 480 rtc->write(rtc, RTC_CTRL_B, ctrlb); 481 rtc->write(rtc, RTC_SECS_ALARM, seconds); 482 rtc->write(rtc, RTC_MINS_ALARM, minutes); 483 rtc->write(rtc, RTC_HRS_ALARM, hours); 484 rtc->write(rtc, RTC_MDAY_ALARM, mday); 485 486 /* Re-enable the alarm if needed. */ 487 if (alrm->enabled) { 488 ctrlb = rtc->read(rtc, RTC_CTRL_B); 489 ctrlb |= RTC_CTRL_B_AIE; 490 rtc->write(rtc, RTC_CTRL_B, ctrlb); 491 } 492 493 /* Done! */ 494 ds1685_rtc_end_data_access(rtc); 495 496 return 0; 497 } 498 /* ----------------------------------------------------------------------- */ 499 500 501 /* ----------------------------------------------------------------------- */ 502 /* /dev/rtcX Interface functions */ 503 504 /** 505 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. 506 * @dev: pointer to device structure. 507 * @enabled: flag indicating whether to enable or disable. 508 */ 509 static int 510 ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 511 { 512 struct ds1685_priv *rtc = dev_get_drvdata(dev); 513 514 /* Flip the requisite interrupt-enable bit. */ 515 if (enabled) 516 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) | 517 RTC_CTRL_B_AIE)); 518 else 519 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) & 520 ~(RTC_CTRL_B_AIE))); 521 522 /* Read Control C to clear all the flag bits. */ 523 rtc->read(rtc, RTC_CTRL_C); 524 525 return 0; 526 } 527 /* ----------------------------------------------------------------------- */ 528 529 530 /* ----------------------------------------------------------------------- */ 531 /* IRQ handler */ 532 533 /** 534 * ds1685_rtc_extended_irq - take care of extended interrupts 535 * @rtc: pointer to the ds1685 rtc structure. 536 * @pdev: platform device pointer. 537 */ 538 static void 539 ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev) 540 { 541 u8 ctrl4a, ctrl4b; 542 543 ds1685_rtc_switch_to_bank1(rtc); 544 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 545 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 546 547 /* 548 * Check for a kickstart interrupt. With Vcc applied, this 549 * typically means that the power button was pressed, so we 550 * begin the shutdown sequence. 551 */ 552 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) { 553 /* Briefly disable kickstarts to debounce button presses. */ 554 rtc->write(rtc, RTC_EXT_CTRL_4B, 555 (rtc->read(rtc, RTC_EXT_CTRL_4B) & 556 ~(RTC_CTRL_4B_KSE))); 557 558 /* Clear the kickstart flag. */ 559 rtc->write(rtc, RTC_EXT_CTRL_4A, 560 (ctrl4a & ~(RTC_CTRL_4A_KF))); 561 562 563 /* 564 * Sleep 500ms before re-enabling kickstarts. This allows 565 * adequate time to avoid reading signal jitter as additional 566 * button presses. 567 */ 568 msleep(500); 569 rtc->write(rtc, RTC_EXT_CTRL_4B, 570 (rtc->read(rtc, RTC_EXT_CTRL_4B) | 571 RTC_CTRL_4B_KSE)); 572 573 /* Call the platform pre-poweroff function. Else, shutdown. */ 574 if (rtc->prepare_poweroff != NULL) 575 rtc->prepare_poweroff(); 576 else 577 ds1685_rtc_poweroff(pdev); 578 } 579 580 /* 581 * Check for a wake-up interrupt. With Vcc applied, this is 582 * essentially a second alarm interrupt, except it takes into 583 * account the 'date' register in bank1 in addition to the 584 * standard three alarm registers. 585 */ 586 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) { 587 rtc->write(rtc, RTC_EXT_CTRL_4A, 588 (ctrl4a & ~(RTC_CTRL_4A_WF))); 589 590 /* Call the platform wake_alarm function if defined. */ 591 if (rtc->wake_alarm != NULL) 592 rtc->wake_alarm(); 593 else 594 dev_warn(&pdev->dev, 595 "Wake Alarm IRQ just occurred!\n"); 596 } 597 598 /* 599 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 600 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting 601 * each byte to a logic 1. This has no effect on any extended 602 * NV-SRAM that might be present, nor on the time/calendar/alarm 603 * registers. After a ram-clear is completed, there is a minimum 604 * recovery time of ~150ms in which all reads/writes are locked out. 605 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot 606 * catch this scenario. 607 */ 608 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) { 609 rtc->write(rtc, RTC_EXT_CTRL_4A, 610 (ctrl4a & ~(RTC_CTRL_4A_RF))); 611 msleep(150); 612 613 /* Call the platform post_ram_clear function if defined. */ 614 if (rtc->post_ram_clear != NULL) 615 rtc->post_ram_clear(); 616 else 617 dev_warn(&pdev->dev, 618 "RAM-Clear IRQ just occurred!\n"); 619 } 620 ds1685_rtc_switch_to_bank0(rtc); 621 } 622 623 /** 624 * ds1685_rtc_irq_handler - IRQ handler. 625 * @irq: IRQ number. 626 * @dev_id: platform device pointer. 627 */ 628 static irqreturn_t 629 ds1685_rtc_irq_handler(int irq, void *dev_id) 630 { 631 struct platform_device *pdev = dev_id; 632 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 633 struct mutex *rtc_mutex; 634 u8 ctrlb, ctrlc; 635 unsigned long events = 0; 636 u8 num_irqs = 0; 637 638 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ 639 if (unlikely(!rtc)) 640 return IRQ_HANDLED; 641 642 rtc_mutex = &rtc->dev->ops_lock; 643 mutex_lock(rtc_mutex); 644 645 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ 646 ctrlb = rtc->read(rtc, RTC_CTRL_B); 647 ctrlc = rtc->read(rtc, RTC_CTRL_C); 648 649 /* Is the IRQF bit set? */ 650 if (likely(ctrlc & RTC_CTRL_C_IRQF)) { 651 /* 652 * We need to determine if it was one of the standard 653 * events: PF, AF, or UF. If so, we handle them and 654 * update the RTC core. 655 */ 656 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { 657 events = RTC_IRQF; 658 659 /* Check for a periodic interrupt. */ 660 if ((ctrlb & RTC_CTRL_B_PIE) && 661 (ctrlc & RTC_CTRL_C_PF)) { 662 events |= RTC_PF; 663 num_irqs++; 664 } 665 666 /* Check for an alarm interrupt. */ 667 if ((ctrlb & RTC_CTRL_B_AIE) && 668 (ctrlc & RTC_CTRL_C_AF)) { 669 events |= RTC_AF; 670 num_irqs++; 671 } 672 673 /* Check for an update interrupt. */ 674 if ((ctrlb & RTC_CTRL_B_UIE) && 675 (ctrlc & RTC_CTRL_C_UF)) { 676 events |= RTC_UF; 677 num_irqs++; 678 } 679 } else { 680 /* 681 * One of the "extended" interrupts was received that 682 * is not recognized by the RTC core. 683 */ 684 ds1685_rtc_extended_irq(rtc, pdev); 685 } 686 } 687 rtc_update_irq(rtc->dev, num_irqs, events); 688 mutex_unlock(rtc_mutex); 689 690 return events ? IRQ_HANDLED : IRQ_NONE; 691 } 692 /* ----------------------------------------------------------------------- */ 693 694 695 /* ----------------------------------------------------------------------- */ 696 /* ProcFS interface */ 697 698 #ifdef CONFIG_PROC_FS 699 #define NUM_REGS 6 /* Num of control registers. */ 700 #define NUM_BITS 8 /* Num bits per register. */ 701 #define NUM_SPACES 4 /* Num spaces between each bit. */ 702 703 /* 704 * Periodic Interrupt Rates. 705 */ 706 static const char *ds1685_rtc_pirq_rate[16] = { 707 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", 708 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", 709 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" 710 }; 711 712 /* 713 * Square-Wave Output Frequencies. 714 */ 715 static const char *ds1685_rtc_sqw_freq[16] = { 716 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz", 717 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz" 718 }; 719 720 /** 721 * ds1685_rtc_proc - procfs access function. 722 * @dev: pointer to device structure. 723 * @seq: pointer to seq_file structure. 724 */ 725 static int 726 ds1685_rtc_proc(struct device *dev, struct seq_file *seq) 727 { 728 struct ds1685_priv *rtc = dev_get_drvdata(dev); 729 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8]; 730 char *model; 731 732 /* Read all the relevant data from the control registers. */ 733 ds1685_rtc_switch_to_bank1(rtc); 734 ds1685_rtc_get_ssn(rtc, ssn); 735 ctrla = rtc->read(rtc, RTC_CTRL_A); 736 ctrlb = rtc->read(rtc, RTC_CTRL_B); 737 ctrlc = rtc->read(rtc, RTC_CTRL_C); 738 ctrld = rtc->read(rtc, RTC_CTRL_D); 739 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 740 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 741 ds1685_rtc_switch_to_bank0(rtc); 742 743 /* Determine the RTC model. */ 744 switch (ssn[0]) { 745 case RTC_MODEL_DS1685: 746 model = "DS1685/DS1687\0"; 747 break; 748 case RTC_MODEL_DS1689: 749 model = "DS1689/DS1693\0"; 750 break; 751 case RTC_MODEL_DS17285: 752 model = "DS17285/DS17287\0"; 753 break; 754 case RTC_MODEL_DS17485: 755 model = "DS17485/DS17487\0"; 756 break; 757 case RTC_MODEL_DS17885: 758 model = "DS17885/DS17887\0"; 759 break; 760 default: 761 model = "Unknown\0"; 762 break; 763 } 764 765 /* Print out the information. */ 766 seq_printf(seq, 767 "Model\t\t: %s\n" 768 "Oscillator\t: %s\n" 769 "12/24hr\t\t: %s\n" 770 "DST\t\t: %s\n" 771 "Data mode\t: %s\n" 772 "Battery\t\t: %s\n" 773 "Aux batt\t: %s\n" 774 "Update IRQ\t: %s\n" 775 "Periodic IRQ\t: %s\n" 776 "Periodic Rate\t: %s\n" 777 "SQW Freq\t: %s\n" 778 "Serial #\t: %8phC\n", 779 model, 780 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), 781 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), 782 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), 783 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), 784 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), 785 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), 786 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), 787 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), 788 (!(ctrl4b & RTC_CTRL_4B_E32K) ? 789 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), 790 (!((ctrl4b & RTC_CTRL_4B_E32K)) ? 791 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), 792 ssn); 793 return 0; 794 } 795 #else 796 #define ds1685_rtc_proc NULL 797 #endif /* CONFIG_PROC_FS */ 798 /* ----------------------------------------------------------------------- */ 799 800 801 /* ----------------------------------------------------------------------- */ 802 /* RTC Class operations */ 803 804 static const struct rtc_class_ops 805 ds1685_rtc_ops = { 806 .proc = ds1685_rtc_proc, 807 .read_time = ds1685_rtc_read_time, 808 .set_time = ds1685_rtc_set_time, 809 .read_alarm = ds1685_rtc_read_alarm, 810 .set_alarm = ds1685_rtc_set_alarm, 811 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, 812 }; 813 /* ----------------------------------------------------------------------- */ 814 815 static int ds1685_nvram_read(void *priv, unsigned int pos, void *val, 816 size_t size) 817 { 818 struct ds1685_priv *rtc = priv; 819 struct mutex *rtc_mutex = &rtc->dev->ops_lock; 820 ssize_t count; 821 u8 *buf = val; 822 int err; 823 824 err = mutex_lock_interruptible(rtc_mutex); 825 if (err) 826 return err; 827 828 ds1685_rtc_switch_to_bank0(rtc); 829 830 /* Read NVRAM in time and bank0 registers. */ 831 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; 832 count++, size--) { 833 if (count < NVRAM_SZ_TIME) 834 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++)); 835 else 836 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++)); 837 } 838 839 #ifndef CONFIG_RTC_DRV_DS1689 840 if (size > 0) { 841 ds1685_rtc_switch_to_bank1(rtc); 842 843 #ifndef CONFIG_RTC_DRV_DS1685 844 /* Enable burst-mode on DS17x85/DS17x87 */ 845 rtc->write(rtc, RTC_EXT_CTRL_4A, 846 (rtc->read(rtc, RTC_EXT_CTRL_4A) | 847 RTC_CTRL_4A_BME)); 848 849 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start 850 * reading with burst-mode */ 851 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, 852 (pos - NVRAM_TOTAL_SZ_BANK0)); 853 #endif 854 855 /* Read NVRAM in bank1 registers. */ 856 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; 857 count++, size--) { 858 #ifdef CONFIG_RTC_DRV_DS1685 859 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR 860 * before each read. */ 861 rtc->write(rtc, RTC_BANK1_RAM_ADDR, 862 (pos - NVRAM_TOTAL_SZ_BANK0)); 863 #endif 864 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT); 865 pos++; 866 } 867 868 #ifndef CONFIG_RTC_DRV_DS1685 869 /* Disable burst-mode on DS17x85/DS17x87 */ 870 rtc->write(rtc, RTC_EXT_CTRL_4A, 871 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 872 ~(RTC_CTRL_4A_BME))); 873 #endif 874 ds1685_rtc_switch_to_bank0(rtc); 875 } 876 #endif /* !CONFIG_RTC_DRV_DS1689 */ 877 mutex_unlock(rtc_mutex); 878 879 return 0; 880 } 881 882 static int ds1685_nvram_write(void *priv, unsigned int pos, void *val, 883 size_t size) 884 { 885 struct ds1685_priv *rtc = priv; 886 struct mutex *rtc_mutex = &rtc->dev->ops_lock; 887 ssize_t count; 888 u8 *buf = val; 889 int err; 890 891 err = mutex_lock_interruptible(rtc_mutex); 892 if (err) 893 return err; 894 895 ds1685_rtc_switch_to_bank0(rtc); 896 897 /* Write NVRAM in time and bank0 registers. */ 898 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; 899 count++, size--) 900 if (count < NVRAM_SZ_TIME) 901 rtc->write(rtc, (NVRAM_TIME_BASE + pos++), 902 *buf++); 903 else 904 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++); 905 906 #ifndef CONFIG_RTC_DRV_DS1689 907 if (size > 0) { 908 ds1685_rtc_switch_to_bank1(rtc); 909 910 #ifndef CONFIG_RTC_DRV_DS1685 911 /* Enable burst-mode on DS17x85/DS17x87 */ 912 rtc->write(rtc, RTC_EXT_CTRL_4A, 913 (rtc->read(rtc, RTC_EXT_CTRL_4A) | 914 RTC_CTRL_4A_BME)); 915 916 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start 917 * writing with burst-mode */ 918 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, 919 (pos - NVRAM_TOTAL_SZ_BANK0)); 920 #endif 921 922 /* Write NVRAM in bank1 registers. */ 923 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; 924 count++, size--) { 925 #ifdef CONFIG_RTC_DRV_DS1685 926 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR 927 * before each read. */ 928 rtc->write(rtc, RTC_BANK1_RAM_ADDR, 929 (pos - NVRAM_TOTAL_SZ_BANK0)); 930 #endif 931 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); 932 pos++; 933 } 934 935 #ifndef CONFIG_RTC_DRV_DS1685 936 /* Disable burst-mode on DS17x85/DS17x87 */ 937 rtc->write(rtc, RTC_EXT_CTRL_4A, 938 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 939 ~(RTC_CTRL_4A_BME))); 940 #endif 941 ds1685_rtc_switch_to_bank0(rtc); 942 } 943 #endif /* !CONFIG_RTC_DRV_DS1689 */ 944 mutex_unlock(rtc_mutex); 945 946 return 0; 947 } 948 949 /* ----------------------------------------------------------------------- */ 950 /* SysFS interface */ 951 952 /** 953 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. 954 * @dev: pointer to device structure. 955 * @attr: pointer to device_attribute structure. 956 * @buf: pointer to char array to hold the output. 957 */ 958 static ssize_t 959 ds1685_rtc_sysfs_battery_show(struct device *dev, 960 struct device_attribute *attr, char *buf) 961 { 962 struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); 963 u8 ctrld; 964 965 ctrld = rtc->read(rtc, RTC_CTRL_D); 966 967 return sprintf(buf, "%s\n", 968 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); 969 } 970 static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); 971 972 /** 973 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. 974 * @dev: pointer to device structure. 975 * @attr: pointer to device_attribute structure. 976 * @buf: pointer to char array to hold the output. 977 */ 978 static ssize_t 979 ds1685_rtc_sysfs_auxbatt_show(struct device *dev, 980 struct device_attribute *attr, char *buf) 981 { 982 struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); 983 u8 ctrl4a; 984 985 ds1685_rtc_switch_to_bank1(rtc); 986 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 987 ds1685_rtc_switch_to_bank0(rtc); 988 989 return sprintf(buf, "%s\n", 990 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); 991 } 992 static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); 993 994 /** 995 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. 996 * @dev: pointer to device structure. 997 * @attr: pointer to device_attribute structure. 998 * @buf: pointer to char array to hold the output. 999 */ 1000 static ssize_t 1001 ds1685_rtc_sysfs_serial_show(struct device *dev, 1002 struct device_attribute *attr, char *buf) 1003 { 1004 struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); 1005 u8 ssn[8]; 1006 1007 ds1685_rtc_switch_to_bank1(rtc); 1008 ds1685_rtc_get_ssn(rtc, ssn); 1009 ds1685_rtc_switch_to_bank0(rtc); 1010 1011 return sprintf(buf, "%8phC\n", ssn); 1012 } 1013 static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); 1014 1015 /** 1016 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. 1017 */ 1018 static struct attribute* 1019 ds1685_rtc_sysfs_misc_attrs[] = { 1020 &dev_attr_battery.attr, 1021 &dev_attr_auxbatt.attr, 1022 &dev_attr_serial.attr, 1023 NULL, 1024 }; 1025 1026 /** 1027 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. 1028 */ 1029 static const struct attribute_group 1030 ds1685_rtc_sysfs_misc_grp = { 1031 .name = "misc", 1032 .attrs = ds1685_rtc_sysfs_misc_attrs, 1033 }; 1034 1035 /* ----------------------------------------------------------------------- */ 1036 /* Driver Probe/Removal */ 1037 1038 /** 1039 * ds1685_rtc_probe - initializes rtc driver. 1040 * @pdev: pointer to platform_device structure. 1041 */ 1042 static int 1043 ds1685_rtc_probe(struct platform_device *pdev) 1044 { 1045 struct rtc_device *rtc_dev; 1046 struct resource *res; 1047 struct ds1685_priv *rtc; 1048 struct ds1685_rtc_platform_data *pdata; 1049 u8 ctrla, ctrlb, hours; 1050 unsigned char am_pm; 1051 int ret = 0; 1052 struct nvmem_config nvmem_cfg = { 1053 .name = "ds1685_nvram", 1054 .size = NVRAM_TOTAL_SZ, 1055 .reg_read = ds1685_nvram_read, 1056 .reg_write = ds1685_nvram_write, 1057 }; 1058 1059 /* Get the platform data. */ 1060 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; 1061 if (!pdata) 1062 return -ENODEV; 1063 1064 /* Allocate memory for the rtc device. */ 1065 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 1066 if (!rtc) 1067 return -ENOMEM; 1068 1069 /* 1070 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all 1071 * platforms put the RTC in an easy-access place. Like the SGI Octane, 1072 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip 1073 * that sits behind the IOC3 PCI metadevice. 1074 */ 1075 if (pdata->alloc_io_resources) { 1076 /* Get the platform resources. */ 1077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1078 if (!res) 1079 return -ENXIO; 1080 rtc->size = resource_size(res); 1081 1082 /* Request a memory region. */ 1083 /* XXX: mmio-only for now. */ 1084 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size, 1085 pdev->name)) 1086 return -EBUSY; 1087 1088 /* 1089 * Set the base address for the rtc, and ioremap its 1090 * registers. 1091 */ 1092 rtc->baseaddr = res->start; 1093 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size); 1094 if (!rtc->regs) 1095 return -ENOMEM; 1096 } 1097 rtc->alloc_io_resources = pdata->alloc_io_resources; 1098 1099 /* Get the register step size. */ 1100 if (pdata->regstep > 0) 1101 rtc->regstep = pdata->regstep; 1102 else 1103 rtc->regstep = 1; 1104 1105 /* Platform read function, else default if mmio setup */ 1106 if (pdata->plat_read) 1107 rtc->read = pdata->plat_read; 1108 else 1109 if (pdata->alloc_io_resources) 1110 rtc->read = ds1685_read; 1111 else 1112 return -ENXIO; 1113 1114 /* Platform write function, else default if mmio setup */ 1115 if (pdata->plat_write) 1116 rtc->write = pdata->plat_write; 1117 else 1118 if (pdata->alloc_io_resources) 1119 rtc->write = ds1685_write; 1120 else 1121 return -ENXIO; 1122 1123 /* Platform pre-shutdown function, if defined. */ 1124 if (pdata->plat_prepare_poweroff) 1125 rtc->prepare_poweroff = pdata->plat_prepare_poweroff; 1126 1127 /* Platform wake_alarm function, if defined. */ 1128 if (pdata->plat_wake_alarm) 1129 rtc->wake_alarm = pdata->plat_wake_alarm; 1130 1131 /* Platform post_ram_clear function, if defined. */ 1132 if (pdata->plat_post_ram_clear) 1133 rtc->post_ram_clear = pdata->plat_post_ram_clear; 1134 1135 /* set the driver data. */ 1136 platform_set_drvdata(pdev, rtc); 1137 1138 /* Turn the oscillator on if is not already on (DV1 = 1). */ 1139 ctrla = rtc->read(rtc, RTC_CTRL_A); 1140 if (!(ctrla & RTC_CTRL_A_DV1)) 1141 ctrla |= RTC_CTRL_A_DV1; 1142 1143 /* Enable the countdown chain (DV2 = 0) */ 1144 ctrla &= ~(RTC_CTRL_A_DV2); 1145 1146 /* Clear RS3-RS0 in Control A. */ 1147 ctrla &= ~(RTC_CTRL_A_RS_MASK); 1148 1149 /* 1150 * All done with Control A. Switch to Bank 1 for the remainder of 1151 * the RTC setup so we have access to the extended functions. 1152 */ 1153 ctrla |= RTC_CTRL_A_DV0; 1154 rtc->write(rtc, RTC_CTRL_A, ctrla); 1155 1156 /* Default to 32768kHz output. */ 1157 rtc->write(rtc, RTC_EXT_CTRL_4B, 1158 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); 1159 1160 /* Set the SET bit in Control B so we can do some housekeeping. */ 1161 rtc->write(rtc, RTC_CTRL_B, 1162 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); 1163 1164 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ 1165 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) 1166 cpu_relax(); 1167 1168 /* 1169 * If the platform supports BCD mode, then set DM=0 in Control B. 1170 * Otherwise, set DM=1 for BIN mode. 1171 */ 1172 ctrlb = rtc->read(rtc, RTC_CTRL_B); 1173 if (pdata->bcd_mode) 1174 ctrlb &= ~(RTC_CTRL_B_DM); 1175 else 1176 ctrlb |= RTC_CTRL_B_DM; 1177 rtc->bcd_mode = pdata->bcd_mode; 1178 1179 /* 1180 * Disable Daylight Savings Time (DSE = 0). 1181 * The RTC has hardcoded timezone information that is rendered 1182 * obselete. We'll let the OS deal with DST settings instead. 1183 */ 1184 if (ctrlb & RTC_CTRL_B_DSE) 1185 ctrlb &= ~(RTC_CTRL_B_DSE); 1186 1187 /* Force 24-hour mode (2412 = 1). */ 1188 if (!(ctrlb & RTC_CTRL_B_2412)) { 1189 /* Reinitialize the time hours. */ 1190 hours = rtc->read(rtc, RTC_HRS); 1191 am_pm = hours & RTC_HRS_AMPM_MASK; 1192 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, 1193 RTC_HRS_12_BIN_MASK); 1194 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); 1195 1196 /* Enable 24-hour mode. */ 1197 ctrlb |= RTC_CTRL_B_2412; 1198 1199 /* Write back to Control B, including DM & DSE bits. */ 1200 rtc->write(rtc, RTC_CTRL_B, ctrlb); 1201 1202 /* Write the time hours back. */ 1203 rtc->write(rtc, RTC_HRS, 1204 ds1685_rtc_bin2bcd(rtc, hours, 1205 RTC_HRS_24_BIN_MASK, 1206 RTC_HRS_24_BCD_MASK)); 1207 1208 /* Reinitialize the alarm hours. */ 1209 hours = rtc->read(rtc, RTC_HRS_ALARM); 1210 am_pm = hours & RTC_HRS_AMPM_MASK; 1211 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, 1212 RTC_HRS_12_BIN_MASK); 1213 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); 1214 1215 /* Write the alarm hours back. */ 1216 rtc->write(rtc, RTC_HRS_ALARM, 1217 ds1685_rtc_bin2bcd(rtc, hours, 1218 RTC_HRS_24_BIN_MASK, 1219 RTC_HRS_24_BCD_MASK)); 1220 } else { 1221 /* 24-hour mode is already set, so write Control B back. */ 1222 rtc->write(rtc, RTC_CTRL_B, ctrlb); 1223 } 1224 1225 /* Unset the SET bit in Control B so the RTC can update. */ 1226 rtc->write(rtc, RTC_CTRL_B, 1227 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); 1228 1229 /* Check the main battery. */ 1230 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) 1231 dev_warn(&pdev->dev, 1232 "Main battery is exhausted! RTC may be invalid!\n"); 1233 1234 /* Check the auxillary battery. It is optional. */ 1235 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) 1236 dev_warn(&pdev->dev, 1237 "Aux battery is exhausted or not available.\n"); 1238 1239 /* Read Ctrl B and clear PIE/AIE/UIE. */ 1240 rtc->write(rtc, RTC_CTRL_B, 1241 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK))); 1242 1243 /* Reading Ctrl C auto-clears PF/AF/UF. */ 1244 rtc->read(rtc, RTC_CTRL_C); 1245 1246 /* Read Ctrl 4B and clear RIE/WIE/KSE. */ 1247 rtc->write(rtc, RTC_EXT_CTRL_4B, 1248 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK))); 1249 1250 /* Clear RF/WF/KF in Ctrl 4A. */ 1251 rtc->write(rtc, RTC_EXT_CTRL_4A, 1252 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK))); 1253 1254 /* 1255 * Re-enable KSE to handle power button events. We do not enable 1256 * WIE or RIE by default. 1257 */ 1258 rtc->write(rtc, RTC_EXT_CTRL_4B, 1259 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE)); 1260 1261 rtc_dev = devm_rtc_allocate_device(&pdev->dev); 1262 if (IS_ERR(rtc_dev)) 1263 return PTR_ERR(rtc_dev); 1264 1265 rtc_dev->ops = &ds1685_rtc_ops; 1266 1267 /* Century bit is useless because leap year fails in 1900 and 2100 */ 1268 rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; 1269 rtc_dev->range_max = RTC_TIMESTAMP_END_2099; 1270 1271 /* Maximum periodic rate is 8192Hz (0.122070ms). */ 1272 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; 1273 1274 /* See if the platform doesn't support UIE. */ 1275 if (pdata->uie_unsupported) 1276 rtc_dev->uie_unsupported = 1; 1277 rtc->uie_unsupported = pdata->uie_unsupported; 1278 1279 rtc->dev = rtc_dev; 1280 1281 /* 1282 * Fetch the IRQ and setup the interrupt handler. 1283 * 1284 * Not all platforms have the IRQF pin tied to something. If not, the 1285 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but 1286 * there won't be an automatic way of notifying the kernel about it, 1287 * unless ctrlc is explicitly polled. 1288 */ 1289 if (!pdata->no_irq) { 1290 ret = platform_get_irq(pdev, 0); 1291 if (ret <= 0) 1292 return ret; 1293 1294 rtc->irq_num = ret; 1295 1296 /* Request an IRQ. */ 1297 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num, 1298 NULL, ds1685_rtc_irq_handler, 1299 IRQF_SHARED | IRQF_ONESHOT, 1300 pdev->name, pdev); 1301 1302 /* Check to see if something came back. */ 1303 if (unlikely(ret)) { 1304 dev_warn(&pdev->dev, 1305 "RTC interrupt not available\n"); 1306 rtc->irq_num = 0; 1307 } 1308 } 1309 rtc->no_irq = pdata->no_irq; 1310 1311 /* Setup complete. */ 1312 ds1685_rtc_switch_to_bank0(rtc); 1313 1314 ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp); 1315 if (ret) 1316 return ret; 1317 1318 rtc_dev->nvram_old_abi = true; 1319 nvmem_cfg.priv = rtc; 1320 ret = rtc_nvmem_register(rtc_dev, &nvmem_cfg); 1321 if (ret) 1322 return ret; 1323 1324 return rtc_register_device(rtc_dev); 1325 } 1326 1327 /** 1328 * ds1685_rtc_remove - removes rtc driver. 1329 * @pdev: pointer to platform_device structure. 1330 */ 1331 static int 1332 ds1685_rtc_remove(struct platform_device *pdev) 1333 { 1334 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 1335 1336 /* Read Ctrl B and clear PIE/AIE/UIE. */ 1337 rtc->write(rtc, RTC_CTRL_B, 1338 (rtc->read(rtc, RTC_CTRL_B) & 1339 ~(RTC_CTRL_B_PAU_MASK))); 1340 1341 /* Reading Ctrl C auto-clears PF/AF/UF. */ 1342 rtc->read(rtc, RTC_CTRL_C); 1343 1344 /* Read Ctrl 4B and clear RIE/WIE/KSE. */ 1345 rtc->write(rtc, RTC_EXT_CTRL_4B, 1346 (rtc->read(rtc, RTC_EXT_CTRL_4B) & 1347 ~(RTC_CTRL_4B_RWK_MASK))); 1348 1349 /* Manually clear RF/WF/KF in Ctrl 4A. */ 1350 rtc->write(rtc, RTC_EXT_CTRL_4A, 1351 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 1352 ~(RTC_CTRL_4A_RWK_MASK))); 1353 1354 return 0; 1355 } 1356 1357 /** 1358 * ds1685_rtc_driver - rtc driver properties. 1359 */ 1360 static struct platform_driver ds1685_rtc_driver = { 1361 .driver = { 1362 .name = "rtc-ds1685", 1363 }, 1364 .probe = ds1685_rtc_probe, 1365 .remove = ds1685_rtc_remove, 1366 }; 1367 module_platform_driver(ds1685_rtc_driver); 1368 /* ----------------------------------------------------------------------- */ 1369 1370 1371 /* ----------------------------------------------------------------------- */ 1372 /* Poweroff function */ 1373 1374 /** 1375 * ds1685_rtc_poweroff - uses the RTC chip to power the system off. 1376 * @pdev: pointer to platform_device structure. 1377 */ 1378 void __noreturn 1379 ds1685_rtc_poweroff(struct platform_device *pdev) 1380 { 1381 u8 ctrla, ctrl4a, ctrl4b; 1382 struct ds1685_priv *rtc; 1383 1384 /* Check for valid RTC data, else, spin forever. */ 1385 if (unlikely(!pdev)) { 1386 pr_emerg("platform device data not available, spinning forever ...\n"); 1387 while(1); 1388 unreachable(); 1389 } else { 1390 /* Get the rtc data. */ 1391 rtc = platform_get_drvdata(pdev); 1392 1393 /* 1394 * Disable our IRQ. We're powering down, so we're not 1395 * going to worry about cleaning up. Most of that should 1396 * have been taken care of by the shutdown scripts and this 1397 * is the final function call. 1398 */ 1399 if (!rtc->no_irq) 1400 disable_irq_nosync(rtc->irq_num); 1401 1402 /* Oscillator must be on and the countdown chain enabled. */ 1403 ctrla = rtc->read(rtc, RTC_CTRL_A); 1404 ctrla |= RTC_CTRL_A_DV1; 1405 ctrla &= ~(RTC_CTRL_A_DV2); 1406 rtc->write(rtc, RTC_CTRL_A, ctrla); 1407 1408 /* 1409 * Read Control 4A and check the status of the auxillary 1410 * battery. This must be present and working (VRT2 = 1) 1411 * for wakeup and kickstart functionality to be useful. 1412 */ 1413 ds1685_rtc_switch_to_bank1(rtc); 1414 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 1415 if (ctrl4a & RTC_CTRL_4A_VRT2) { 1416 /* Clear all of the interrupt flags on Control 4A. */ 1417 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); 1418 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a); 1419 1420 /* 1421 * The auxillary battery is present and working. 1422 * Enable extended functions (ABE=1), enable 1423 * wake-up (WIE=1), and enable kickstart (KSE=1) 1424 * in Control 4B. 1425 */ 1426 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 1427 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | 1428 RTC_CTRL_4B_KSE); 1429 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b); 1430 } 1431 1432 /* Set PAB to 1 in Control 4A to power the system down. */ 1433 dev_warn(&pdev->dev, "Powerdown.\n"); 1434 msleep(20); 1435 rtc->write(rtc, RTC_EXT_CTRL_4A, 1436 (ctrl4a | RTC_CTRL_4A_PAB)); 1437 1438 /* Spin ... we do not switch back to bank0. */ 1439 while(1); 1440 unreachable(); 1441 } 1442 } 1443 EXPORT_SYMBOL(ds1685_rtc_poweroff); 1444 /* ----------------------------------------------------------------------- */ 1445 1446 1447 MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>"); 1448 MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>"); 1449 MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); 1450 MODULE_LICENSE("GPL"); 1451 MODULE_ALIAS("platform:rtc-ds1685"); 1452