1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 4 * 5 * Copyright (C) 2005 James Chapman (ds1337 core) 6 * Copyright (C) 2006 David Brownell 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bcd.h> 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/rtc/ds1307.h> 18 #include <linux/rtc.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* 28 * We can't determine type by probing, but if we expect pre-Linux code 29 * to have set the chip up as a clock (turning on the oscillator and 30 * setting the date and time), Linux can ignore the non-clock features. 31 * That's a natural job for a factory or repair bench. 32 */ 33 enum ds_type { 34 ds_1307, 35 ds_1308, 36 ds_1337, 37 ds_1338, 38 ds_1339, 39 ds_1340, 40 ds_1341, 41 ds_1388, 42 ds_3231, 43 m41t0, 44 m41t00, 45 m41t11, 46 mcp794xx, 47 rx_8025, 48 rx_8130, 49 last_ds_type /* always last */ 50 /* rs5c372 too? different address... */ 51 }; 52 53 /* RTC registers don't differ much, except for the century flag */ 54 #define DS1307_REG_SECS 0x00 /* 00-59 */ 55 # define DS1307_BIT_CH 0x80 56 # define DS1340_BIT_nEOSC 0x80 57 # define MCP794XX_BIT_ST 0x80 58 #define DS1307_REG_MIN 0x01 /* 00-59 */ 59 # define M41T0_BIT_OF 0x80 60 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 61 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 62 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 63 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 64 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 65 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 66 # define MCP794XX_BIT_VBATEN 0x08 67 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 68 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 69 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 70 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 71 72 /* 73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 74 * start at 7, and they differ a LOT. Only control and status matter for 75 * basic RTC date and time functionality; be careful using them. 76 */ 77 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 78 # define DS1307_BIT_OUT 0x80 79 # define DS1338_BIT_OSF 0x20 80 # define DS1307_BIT_SQWE 0x10 81 # define DS1307_BIT_RS1 0x02 82 # define DS1307_BIT_RS0 0x01 83 #define DS1337_REG_CONTROL 0x0e 84 # define DS1337_BIT_nEOSC 0x80 85 # define DS1339_BIT_BBSQI 0x20 86 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 87 # define DS1337_BIT_RS2 0x10 88 # define DS1337_BIT_RS1 0x08 89 # define DS1337_BIT_INTCN 0x04 90 # define DS1337_BIT_A2IE 0x02 91 # define DS1337_BIT_A1IE 0x01 92 #define DS1340_REG_CONTROL 0x07 93 # define DS1340_BIT_OUT 0x80 94 # define DS1340_BIT_FT 0x40 95 # define DS1340_BIT_CALIB_SIGN 0x20 96 # define DS1340_M_CALIBRATION 0x1f 97 #define DS1340_REG_FLAG 0x09 98 # define DS1340_BIT_OSF 0x80 99 #define DS1337_REG_STATUS 0x0f 100 # define DS1337_BIT_OSF 0x80 101 # define DS3231_BIT_EN32KHZ 0x08 102 # define DS1337_BIT_A2I 0x02 103 # define DS1337_BIT_A1I 0x01 104 #define DS1339_REG_ALARM1_SECS 0x07 105 106 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 107 108 #define RX8025_REG_CTRL1 0x0e 109 # define RX8025_BIT_2412 0x20 110 #define RX8025_REG_CTRL2 0x0f 111 # define RX8025_BIT_PON 0x10 112 # define RX8025_BIT_VDET 0x40 113 # define RX8025_BIT_XST 0x20 114 115 #define RX8130_REG_ALARM_MIN 0x17 116 #define RX8130_REG_ALARM_HOUR 0x18 117 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 118 #define RX8130_REG_EXTENSION 0x1c 119 #define RX8130_REG_EXTENSION_WADA BIT(3) 120 #define RX8130_REG_FLAG 0x1d 121 #define RX8130_REG_FLAG_VLF BIT(1) 122 #define RX8130_REG_FLAG_AF BIT(3) 123 #define RX8130_REG_CONTROL0 0x1e 124 #define RX8130_REG_CONTROL0_AIE BIT(3) 125 #define RX8130_REG_CONTROL1 0x1f 126 #define RX8130_REG_CONTROL1_INIEN BIT(4) 127 #define RX8130_REG_CONTROL1_CHGEN BIT(5) 128 129 #define MCP794XX_REG_CONTROL 0x07 130 # define MCP794XX_BIT_ALM0_EN 0x10 131 # define MCP794XX_BIT_ALM1_EN 0x20 132 #define MCP794XX_REG_ALARM0_BASE 0x0a 133 #define MCP794XX_REG_ALARM0_CTRL 0x0d 134 #define MCP794XX_REG_ALARM1_BASE 0x11 135 #define MCP794XX_REG_ALARM1_CTRL 0x14 136 # define MCP794XX_BIT_ALMX_IF BIT(3) 137 # define MCP794XX_BIT_ALMX_C0 BIT(4) 138 # define MCP794XX_BIT_ALMX_C1 BIT(5) 139 # define MCP794XX_BIT_ALMX_C2 BIT(6) 140 # define MCP794XX_BIT_ALMX_POL BIT(7) 141 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 142 MCP794XX_BIT_ALMX_C1 | \ 143 MCP794XX_BIT_ALMX_C2) 144 145 #define M41TXX_REG_CONTROL 0x07 146 # define M41TXX_BIT_OUT BIT(7) 147 # define M41TXX_BIT_FT BIT(6) 148 # define M41TXX_BIT_CALIB_SIGN BIT(5) 149 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 150 151 #define DS1388_REG_WDOG_HUN_SECS 0x08 152 #define DS1388_REG_WDOG_SECS 0x09 153 #define DS1388_REG_FLAG 0x0b 154 # define DS1388_BIT_WF BIT(6) 155 # define DS1388_BIT_OSF BIT(7) 156 #define DS1388_REG_CONTROL 0x0c 157 # define DS1388_BIT_RST BIT(0) 158 # define DS1388_BIT_WDE BIT(1) 159 # define DS1388_BIT_nEOSC BIT(7) 160 161 /* negative offset step is -2.034ppm */ 162 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 163 /* positive offset step is +4.068ppm */ 164 #define M41TXX_POS_OFFSET_STEP_PPB 4068 165 /* Min and max values supported with 'offset' interface by M41TXX */ 166 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 167 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 168 169 struct ds1307 { 170 enum ds_type type; 171 unsigned long flags; 172 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ 173 #define HAS_ALARM 1 /* bit 1 == irq claimed */ 174 struct device *dev; 175 struct regmap *regmap; 176 const char *name; 177 struct rtc_device *rtc; 178 #ifdef CONFIG_COMMON_CLK 179 struct clk_hw clks[2]; 180 #endif 181 }; 182 183 struct chip_desc { 184 unsigned alarm:1; 185 u16 nvram_offset; 186 u16 nvram_size; 187 u8 offset; /* register's offset */ 188 u8 century_reg; 189 u8 century_enable_bit; 190 u8 century_bit; 191 u8 bbsqi_bit; 192 irq_handler_t irq_handler; 193 const struct rtc_class_ops *rtc_ops; 194 u16 trickle_charger_reg; 195 u8 (*do_trickle_setup)(struct ds1307 *, u32, 196 bool); 197 /* Does the RTC require trickle-resistor-ohms to select the value of 198 * the resistor between Vcc and Vbackup? 199 */ 200 bool requires_trickle_resistor; 201 /* Some RTC's batteries and supercaps were charged by default, others 202 * allow charging but were not configured previously to do so. 203 * Remember this behavior to stay backwards compatible. 204 */ 205 bool charge_default; 206 }; 207 208 static const struct chip_desc chips[last_ds_type]; 209 210 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 211 { 212 struct ds1307 *ds1307 = dev_get_drvdata(dev); 213 int tmp, ret; 214 const struct chip_desc *chip = &chips[ds1307->type]; 215 u8 regs[7]; 216 217 if (ds1307->type == rx_8130) { 218 unsigned int regflag; 219 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 220 if (ret) { 221 dev_err(dev, "%s error %d\n", "read", ret); 222 return ret; 223 } 224 225 if (regflag & RX8130_REG_FLAG_VLF) { 226 dev_warn_once(dev, "oscillator failed, set time!\n"); 227 return -EINVAL; 228 } 229 } 230 231 /* read the RTC date and time registers all at once */ 232 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 233 sizeof(regs)); 234 if (ret) { 235 dev_err(dev, "%s error %d\n", "read", ret); 236 return ret; 237 } 238 239 dev_dbg(dev, "%s: %7ph\n", "read", regs); 240 241 /* if oscillator fail bit is set, no data can be trusted */ 242 if (ds1307->type == m41t0 && 243 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 244 dev_warn_once(dev, "oscillator failed, set time!\n"); 245 return -EINVAL; 246 } 247 248 tmp = regs[DS1307_REG_SECS]; 249 switch (ds1307->type) { 250 case ds_1307: 251 case m41t0: 252 case m41t00: 253 case m41t11: 254 if (tmp & DS1307_BIT_CH) 255 return -EINVAL; 256 break; 257 case ds_1308: 258 case ds_1338: 259 if (tmp & DS1307_BIT_CH) 260 return -EINVAL; 261 262 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp); 263 if (ret) 264 return ret; 265 if (tmp & DS1338_BIT_OSF) 266 return -EINVAL; 267 break; 268 case ds_1340: 269 if (tmp & DS1340_BIT_nEOSC) 270 return -EINVAL; 271 272 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 273 if (ret) 274 return ret; 275 if (tmp & DS1340_BIT_OSF) 276 return -EINVAL; 277 break; 278 case ds_1388: 279 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp); 280 if (ret) 281 return ret; 282 if (tmp & DS1388_BIT_OSF) 283 return -EINVAL; 284 break; 285 case mcp794xx: 286 if (!(tmp & MCP794XX_BIT_ST)) 287 return -EINVAL; 288 289 break; 290 default: 291 break; 292 } 293 294 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 295 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 296 tmp = regs[DS1307_REG_HOUR] & 0x3f; 297 t->tm_hour = bcd2bin(tmp); 298 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 299 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 300 tmp = regs[DS1307_REG_MONTH] & 0x1f; 301 t->tm_mon = bcd2bin(tmp) - 1; 302 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 303 304 if (regs[chip->century_reg] & chip->century_bit && 305 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 306 t->tm_year += 100; 307 308 dev_dbg(dev, "%s secs=%d, mins=%d, " 309 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 310 "read", t->tm_sec, t->tm_min, 311 t->tm_hour, t->tm_mday, 312 t->tm_mon, t->tm_year, t->tm_wday); 313 314 return 0; 315 } 316 317 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 318 { 319 struct ds1307 *ds1307 = dev_get_drvdata(dev); 320 const struct chip_desc *chip = &chips[ds1307->type]; 321 int result; 322 int tmp; 323 u8 regs[7]; 324 325 dev_dbg(dev, "%s secs=%d, mins=%d, " 326 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 327 "write", t->tm_sec, t->tm_min, 328 t->tm_hour, t->tm_mday, 329 t->tm_mon, t->tm_year, t->tm_wday); 330 331 if (t->tm_year < 100) 332 return -EINVAL; 333 334 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 335 if (t->tm_year > (chip->century_bit ? 299 : 199)) 336 return -EINVAL; 337 #else 338 if (t->tm_year > 199) 339 return -EINVAL; 340 #endif 341 342 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 343 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 344 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 345 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 346 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 347 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 348 349 /* assume 20YY not 19YY */ 350 tmp = t->tm_year - 100; 351 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 352 353 if (chip->century_enable_bit) 354 regs[chip->century_reg] |= chip->century_enable_bit; 355 if (t->tm_year > 199 && chip->century_bit) 356 regs[chip->century_reg] |= chip->century_bit; 357 358 switch (ds1307->type) { 359 case ds_1308: 360 case ds_1338: 361 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 362 DS1338_BIT_OSF, 0); 363 break; 364 case ds_1340: 365 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG, 366 DS1340_BIT_OSF, 0); 367 break; 368 case ds_1388: 369 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 370 DS1388_BIT_OSF, 0); 371 break; 372 case mcp794xx: 373 /* 374 * these bits were cleared when preparing the date/time 375 * values and need to be set again before writing the 376 * regsfer out to the device. 377 */ 378 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 379 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 380 break; 381 default: 382 break; 383 } 384 385 dev_dbg(dev, "%s: %7ph\n", "write", regs); 386 387 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 388 sizeof(regs)); 389 if (result) { 390 dev_err(dev, "%s error %d\n", "write", result); 391 return result; 392 } 393 394 if (ds1307->type == rx_8130) { 395 /* clear Voltage Loss Flag as data is available now */ 396 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 397 ~(u8)RX8130_REG_FLAG_VLF); 398 if (result) { 399 dev_err(dev, "%s error %d\n", "write", result); 400 return result; 401 } 402 } 403 404 return 0; 405 } 406 407 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 408 { 409 struct ds1307 *ds1307 = dev_get_drvdata(dev); 410 int ret; 411 u8 regs[9]; 412 413 if (!test_bit(HAS_ALARM, &ds1307->flags)) 414 return -EINVAL; 415 416 /* read all ALARM1, ALARM2, and status registers at once */ 417 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 418 regs, sizeof(regs)); 419 if (ret) { 420 dev_err(dev, "%s error %d\n", "alarm read", ret); 421 return ret; 422 } 423 424 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 425 ®s[0], ®s[4], ®s[7]); 426 427 /* 428 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 429 * and that all four fields are checked matches 430 */ 431 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 432 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 433 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 434 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 435 436 /* ... and status */ 437 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 438 t->pending = !!(regs[8] & DS1337_BIT_A1I); 439 440 dev_dbg(dev, "%s secs=%d, mins=%d, " 441 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 442 "alarm read", t->time.tm_sec, t->time.tm_min, 443 t->time.tm_hour, t->time.tm_mday, 444 t->enabled, t->pending); 445 446 return 0; 447 } 448 449 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 450 { 451 struct ds1307 *ds1307 = dev_get_drvdata(dev); 452 unsigned char regs[9]; 453 u8 control, status; 454 int ret; 455 456 if (!test_bit(HAS_ALARM, &ds1307->flags)) 457 return -EINVAL; 458 459 dev_dbg(dev, "%s secs=%d, mins=%d, " 460 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 461 "alarm set", t->time.tm_sec, t->time.tm_min, 462 t->time.tm_hour, t->time.tm_mday, 463 t->enabled, t->pending); 464 465 /* read current status of both alarms and the chip */ 466 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 467 sizeof(regs)); 468 if (ret) { 469 dev_err(dev, "%s error %d\n", "alarm write", ret); 470 return ret; 471 } 472 control = regs[7]; 473 status = regs[8]; 474 475 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 476 ®s[0], ®s[4], control, status); 477 478 /* set ALARM1, using 24 hour and day-of-month modes */ 479 regs[0] = bin2bcd(t->time.tm_sec); 480 regs[1] = bin2bcd(t->time.tm_min); 481 regs[2] = bin2bcd(t->time.tm_hour); 482 regs[3] = bin2bcd(t->time.tm_mday); 483 484 /* set ALARM2 to non-garbage */ 485 regs[4] = 0; 486 regs[5] = 0; 487 regs[6] = 0; 488 489 /* disable alarms */ 490 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 491 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 492 493 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 494 sizeof(regs)); 495 if (ret) { 496 dev_err(dev, "can't set alarm time\n"); 497 return ret; 498 } 499 500 /* optionally enable ALARM1 */ 501 if (t->enabled) { 502 dev_dbg(dev, "alarm IRQ armed\n"); 503 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 504 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 505 } 506 507 return 0; 508 } 509 510 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 511 { 512 struct ds1307 *ds1307 = dev_get_drvdata(dev); 513 514 if (!test_bit(HAS_ALARM, &ds1307->flags)) 515 return -ENOTTY; 516 517 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 518 DS1337_BIT_A1IE, 519 enabled ? DS1337_BIT_A1IE : 0); 520 } 521 522 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 523 { 524 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 525 DS1307_TRICKLE_CHARGER_NO_DIODE; 526 527 setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 528 529 switch (ohms) { 530 case 250: 531 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 532 break; 533 case 2000: 534 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 535 break; 536 case 4000: 537 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 538 break; 539 default: 540 dev_warn(ds1307->dev, 541 "Unsupported ohm value %u in dt\n", ohms); 542 return 0; 543 } 544 return setup; 545 } 546 547 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode) 548 { 549 /* make sure that the backup battery is enabled */ 550 u8 setup = RX8130_REG_CONTROL1_INIEN; 551 if (diode) 552 setup |= RX8130_REG_CONTROL1_CHGEN; 553 554 return setup; 555 } 556 557 static irqreturn_t rx8130_irq(int irq, void *dev_id) 558 { 559 struct ds1307 *ds1307 = dev_id; 560 struct mutex *lock = &ds1307->rtc->ops_lock; 561 u8 ctl[3]; 562 int ret; 563 564 mutex_lock(lock); 565 566 /* Read control registers. */ 567 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 568 sizeof(ctl)); 569 if (ret < 0) 570 goto out; 571 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 572 goto out; 573 ctl[1] &= ~RX8130_REG_FLAG_AF; 574 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 575 576 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 577 sizeof(ctl)); 578 if (ret < 0) 579 goto out; 580 581 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 582 583 out: 584 mutex_unlock(lock); 585 586 return IRQ_HANDLED; 587 } 588 589 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 590 { 591 struct ds1307 *ds1307 = dev_get_drvdata(dev); 592 u8 ald[3], ctl[3]; 593 int ret; 594 595 if (!test_bit(HAS_ALARM, &ds1307->flags)) 596 return -EINVAL; 597 598 /* Read alarm registers. */ 599 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 600 sizeof(ald)); 601 if (ret < 0) 602 return ret; 603 604 /* Read control registers. */ 605 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 606 sizeof(ctl)); 607 if (ret < 0) 608 return ret; 609 610 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 611 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 612 613 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 614 t->time.tm_sec = -1; 615 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 616 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 617 t->time.tm_wday = -1; 618 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 619 t->time.tm_mon = -1; 620 t->time.tm_year = -1; 621 t->time.tm_yday = -1; 622 t->time.tm_isdst = -1; 623 624 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 625 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 626 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 627 628 return 0; 629 } 630 631 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 632 { 633 struct ds1307 *ds1307 = dev_get_drvdata(dev); 634 u8 ald[3], ctl[3]; 635 int ret; 636 637 if (!test_bit(HAS_ALARM, &ds1307->flags)) 638 return -EINVAL; 639 640 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 641 "enabled=%d pending=%d\n", __func__, 642 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 643 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 644 t->enabled, t->pending); 645 646 /* Read control registers. */ 647 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 648 sizeof(ctl)); 649 if (ret < 0) 650 return ret; 651 652 ctl[0] &= RX8130_REG_EXTENSION_WADA; 653 ctl[1] &= ~RX8130_REG_FLAG_AF; 654 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 655 656 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 657 sizeof(ctl)); 658 if (ret < 0) 659 return ret; 660 661 /* Hardware alarm precision is 1 minute! */ 662 ald[0] = bin2bcd(t->time.tm_min); 663 ald[1] = bin2bcd(t->time.tm_hour); 664 ald[2] = bin2bcd(t->time.tm_mday); 665 666 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 667 sizeof(ald)); 668 if (ret < 0) 669 return ret; 670 671 if (!t->enabled) 672 return 0; 673 674 ctl[2] |= RX8130_REG_CONTROL0_AIE; 675 676 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 677 } 678 679 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 680 { 681 struct ds1307 *ds1307 = dev_get_drvdata(dev); 682 int ret, reg; 683 684 if (!test_bit(HAS_ALARM, &ds1307->flags)) 685 return -EINVAL; 686 687 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 688 if (ret < 0) 689 return ret; 690 691 if (enabled) 692 reg |= RX8130_REG_CONTROL0_AIE; 693 else 694 reg &= ~RX8130_REG_CONTROL0_AIE; 695 696 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 697 } 698 699 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 700 { 701 struct ds1307 *ds1307 = dev_id; 702 struct mutex *lock = &ds1307->rtc->ops_lock; 703 int reg, ret; 704 705 mutex_lock(lock); 706 707 /* Check and clear alarm 0 interrupt flag. */ 708 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 709 if (ret) 710 goto out; 711 if (!(reg & MCP794XX_BIT_ALMX_IF)) 712 goto out; 713 reg &= ~MCP794XX_BIT_ALMX_IF; 714 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 715 if (ret) 716 goto out; 717 718 /* Disable alarm 0. */ 719 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 720 MCP794XX_BIT_ALM0_EN, 0); 721 if (ret) 722 goto out; 723 724 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 725 726 out: 727 mutex_unlock(lock); 728 729 return IRQ_HANDLED; 730 } 731 732 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 733 { 734 struct ds1307 *ds1307 = dev_get_drvdata(dev); 735 u8 regs[10]; 736 int ret; 737 738 if (!test_bit(HAS_ALARM, &ds1307->flags)) 739 return -EINVAL; 740 741 /* Read control and alarm 0 registers. */ 742 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 743 sizeof(regs)); 744 if (ret) 745 return ret; 746 747 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 748 749 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 750 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 751 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 752 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 753 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 754 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 755 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 756 t->time.tm_year = -1; 757 t->time.tm_yday = -1; 758 t->time.tm_isdst = -1; 759 760 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 761 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 762 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 763 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 764 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 765 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 766 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 767 768 return 0; 769 } 770 771 /* 772 * We may have a random RTC weekday, therefore calculate alarm weekday based 773 * on current weekday we read from the RTC timekeeping regs 774 */ 775 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 776 { 777 struct rtc_time tm_now; 778 int days_now, days_alarm, ret; 779 780 ret = ds1307_get_time(dev, &tm_now); 781 if (ret) 782 return ret; 783 784 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 785 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 786 787 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 788 } 789 790 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 791 { 792 struct ds1307 *ds1307 = dev_get_drvdata(dev); 793 unsigned char regs[10]; 794 int wday, ret; 795 796 if (!test_bit(HAS_ALARM, &ds1307->flags)) 797 return -EINVAL; 798 799 wday = mcp794xx_alm_weekday(dev, &t->time); 800 if (wday < 0) 801 return wday; 802 803 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 804 "enabled=%d pending=%d\n", __func__, 805 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 806 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 807 t->enabled, t->pending); 808 809 /* Read control and alarm 0 registers. */ 810 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 811 sizeof(regs)); 812 if (ret) 813 return ret; 814 815 /* Set alarm 0, using 24-hour and day-of-month modes. */ 816 regs[3] = bin2bcd(t->time.tm_sec); 817 regs[4] = bin2bcd(t->time.tm_min); 818 regs[5] = bin2bcd(t->time.tm_hour); 819 regs[6] = wday; 820 regs[7] = bin2bcd(t->time.tm_mday); 821 regs[8] = bin2bcd(t->time.tm_mon + 1); 822 823 /* Clear the alarm 0 interrupt flag. */ 824 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 825 /* Set alarm match: second, minute, hour, day, date, month. */ 826 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 827 /* Disable interrupt. We will not enable until completely programmed */ 828 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 829 830 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 831 sizeof(regs)); 832 if (ret) 833 return ret; 834 835 if (!t->enabled) 836 return 0; 837 regs[0] |= MCP794XX_BIT_ALM0_EN; 838 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 839 } 840 841 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 842 { 843 struct ds1307 *ds1307 = dev_get_drvdata(dev); 844 845 if (!test_bit(HAS_ALARM, &ds1307->flags)) 846 return -EINVAL; 847 848 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 849 MCP794XX_BIT_ALM0_EN, 850 enabled ? MCP794XX_BIT_ALM0_EN : 0); 851 } 852 853 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 854 { 855 struct ds1307 *ds1307 = dev_get_drvdata(dev); 856 unsigned int ctrl_reg; 857 u8 val; 858 859 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 860 861 val = ctrl_reg & M41TXX_M_CALIBRATION; 862 863 /* check if positive */ 864 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 865 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 866 else 867 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 868 869 return 0; 870 } 871 872 static int m41txx_rtc_set_offset(struct device *dev, long offset) 873 { 874 struct ds1307 *ds1307 = dev_get_drvdata(dev); 875 unsigned int ctrl_reg; 876 877 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 878 return -ERANGE; 879 880 if (offset >= 0) { 881 ctrl_reg = DIV_ROUND_CLOSEST(offset, 882 M41TXX_POS_OFFSET_STEP_PPB); 883 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 884 } else { 885 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 886 M41TXX_NEG_OFFSET_STEP_PPB); 887 } 888 889 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 890 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 891 ctrl_reg); 892 } 893 894 #ifdef CONFIG_WATCHDOG_CORE 895 static int ds1388_wdt_start(struct watchdog_device *wdt_dev) 896 { 897 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 898 u8 regs[2]; 899 int ret; 900 901 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 902 DS1388_BIT_WF, 0); 903 if (ret) 904 return ret; 905 906 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 907 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 908 if (ret) 909 return ret; 910 911 /* 912 * watchdog timeouts are measured in seconds. So ignore hundredths of 913 * seconds field. 914 */ 915 regs[0] = 0; 916 regs[1] = bin2bcd(wdt_dev->timeout); 917 918 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 919 sizeof(regs)); 920 if (ret) 921 return ret; 922 923 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 924 DS1388_BIT_WDE | DS1388_BIT_RST, 925 DS1388_BIT_WDE | DS1388_BIT_RST); 926 } 927 928 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) 929 { 930 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 931 932 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 933 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 934 } 935 936 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) 937 { 938 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 939 u8 regs[2]; 940 941 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 942 sizeof(regs)); 943 } 944 945 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev, 946 unsigned int val) 947 { 948 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 949 u8 regs[2]; 950 951 wdt_dev->timeout = val; 952 regs[0] = 0; 953 regs[1] = bin2bcd(wdt_dev->timeout); 954 955 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 956 sizeof(regs)); 957 } 958 #endif 959 960 static const struct rtc_class_ops rx8130_rtc_ops = { 961 .read_time = ds1307_get_time, 962 .set_time = ds1307_set_time, 963 .read_alarm = rx8130_read_alarm, 964 .set_alarm = rx8130_set_alarm, 965 .alarm_irq_enable = rx8130_alarm_irq_enable, 966 }; 967 968 static const struct rtc_class_ops mcp794xx_rtc_ops = { 969 .read_time = ds1307_get_time, 970 .set_time = ds1307_set_time, 971 .read_alarm = mcp794xx_read_alarm, 972 .set_alarm = mcp794xx_set_alarm, 973 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 974 }; 975 976 static const struct rtc_class_ops m41txx_rtc_ops = { 977 .read_time = ds1307_get_time, 978 .set_time = ds1307_set_time, 979 .read_alarm = ds1337_read_alarm, 980 .set_alarm = ds1337_set_alarm, 981 .alarm_irq_enable = ds1307_alarm_irq_enable, 982 .read_offset = m41txx_rtc_read_offset, 983 .set_offset = m41txx_rtc_set_offset, 984 }; 985 986 static const struct chip_desc chips[last_ds_type] = { 987 [ds_1307] = { 988 .nvram_offset = 8, 989 .nvram_size = 56, 990 }, 991 [ds_1308] = { 992 .nvram_offset = 8, 993 .nvram_size = 56, 994 }, 995 [ds_1337] = { 996 .alarm = 1, 997 .century_reg = DS1307_REG_MONTH, 998 .century_bit = DS1337_BIT_CENTURY, 999 }, 1000 [ds_1338] = { 1001 .nvram_offset = 8, 1002 .nvram_size = 56, 1003 }, 1004 [ds_1339] = { 1005 .alarm = 1, 1006 .century_reg = DS1307_REG_MONTH, 1007 .century_bit = DS1337_BIT_CENTURY, 1008 .bbsqi_bit = DS1339_BIT_BBSQI, 1009 .trickle_charger_reg = 0x10, 1010 .do_trickle_setup = &do_trickle_setup_ds1339, 1011 .requires_trickle_resistor = true, 1012 .charge_default = true, 1013 }, 1014 [ds_1340] = { 1015 .century_reg = DS1307_REG_HOUR, 1016 .century_enable_bit = DS1340_BIT_CENTURY_EN, 1017 .century_bit = DS1340_BIT_CENTURY, 1018 .do_trickle_setup = &do_trickle_setup_ds1339, 1019 .trickle_charger_reg = 0x08, 1020 .requires_trickle_resistor = true, 1021 .charge_default = true, 1022 }, 1023 [ds_1341] = { 1024 .century_reg = DS1307_REG_MONTH, 1025 .century_bit = DS1337_BIT_CENTURY, 1026 }, 1027 [ds_1388] = { 1028 .offset = 1, 1029 .trickle_charger_reg = 0x0a, 1030 }, 1031 [ds_3231] = { 1032 .alarm = 1, 1033 .century_reg = DS1307_REG_MONTH, 1034 .century_bit = DS1337_BIT_CENTURY, 1035 .bbsqi_bit = DS3231_BIT_BBSQW, 1036 }, 1037 [rx_8130] = { 1038 .alarm = 1, 1039 /* this is battery backed SRAM */ 1040 .nvram_offset = 0x20, 1041 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 1042 .offset = 0x10, 1043 .irq_handler = rx8130_irq, 1044 .rtc_ops = &rx8130_rtc_ops, 1045 .trickle_charger_reg = RX8130_REG_CONTROL1, 1046 .do_trickle_setup = &do_trickle_setup_rx8130, 1047 }, 1048 [m41t0] = { 1049 .rtc_ops = &m41txx_rtc_ops, 1050 }, 1051 [m41t00] = { 1052 .rtc_ops = &m41txx_rtc_ops, 1053 }, 1054 [m41t11] = { 1055 /* this is battery backed SRAM */ 1056 .nvram_offset = 8, 1057 .nvram_size = 56, 1058 .rtc_ops = &m41txx_rtc_ops, 1059 }, 1060 [mcp794xx] = { 1061 .alarm = 1, 1062 /* this is battery backed SRAM */ 1063 .nvram_offset = 0x20, 1064 .nvram_size = 0x40, 1065 .irq_handler = mcp794xx_irq, 1066 .rtc_ops = &mcp794xx_rtc_ops, 1067 }, 1068 }; 1069 1070 static const struct i2c_device_id ds1307_id[] = { 1071 { "ds1307", ds_1307 }, 1072 { "ds1308", ds_1308 }, 1073 { "ds1337", ds_1337 }, 1074 { "ds1338", ds_1338 }, 1075 { "ds1339", ds_1339 }, 1076 { "ds1388", ds_1388 }, 1077 { "ds1340", ds_1340 }, 1078 { "ds1341", ds_1341 }, 1079 { "ds3231", ds_3231 }, 1080 { "m41t0", m41t0 }, 1081 { "m41t00", m41t00 }, 1082 { "m41t11", m41t11 }, 1083 { "mcp7940x", mcp794xx }, 1084 { "mcp7941x", mcp794xx }, 1085 { "pt7c4338", ds_1307 }, 1086 { "rx8025", rx_8025 }, 1087 { "isl12057", ds_1337 }, 1088 { "rx8130", rx_8130 }, 1089 { } 1090 }; 1091 MODULE_DEVICE_TABLE(i2c, ds1307_id); 1092 1093 #ifdef CONFIG_OF 1094 static const struct of_device_id ds1307_of_match[] = { 1095 { 1096 .compatible = "dallas,ds1307", 1097 .data = (void *)ds_1307 1098 }, 1099 { 1100 .compatible = "dallas,ds1308", 1101 .data = (void *)ds_1308 1102 }, 1103 { 1104 .compatible = "dallas,ds1337", 1105 .data = (void *)ds_1337 1106 }, 1107 { 1108 .compatible = "dallas,ds1338", 1109 .data = (void *)ds_1338 1110 }, 1111 { 1112 .compatible = "dallas,ds1339", 1113 .data = (void *)ds_1339 1114 }, 1115 { 1116 .compatible = "dallas,ds1388", 1117 .data = (void *)ds_1388 1118 }, 1119 { 1120 .compatible = "dallas,ds1340", 1121 .data = (void *)ds_1340 1122 }, 1123 { 1124 .compatible = "dallas,ds1341", 1125 .data = (void *)ds_1341 1126 }, 1127 { 1128 .compatible = "maxim,ds3231", 1129 .data = (void *)ds_3231 1130 }, 1131 { 1132 .compatible = "st,m41t0", 1133 .data = (void *)m41t0 1134 }, 1135 { 1136 .compatible = "st,m41t00", 1137 .data = (void *)m41t00 1138 }, 1139 { 1140 .compatible = "st,m41t11", 1141 .data = (void *)m41t11 1142 }, 1143 { 1144 .compatible = "microchip,mcp7940x", 1145 .data = (void *)mcp794xx 1146 }, 1147 { 1148 .compatible = "microchip,mcp7941x", 1149 .data = (void *)mcp794xx 1150 }, 1151 { 1152 .compatible = "pericom,pt7c4338", 1153 .data = (void *)ds_1307 1154 }, 1155 { 1156 .compatible = "epson,rx8025", 1157 .data = (void *)rx_8025 1158 }, 1159 { 1160 .compatible = "isil,isl12057", 1161 .data = (void *)ds_1337 1162 }, 1163 { 1164 .compatible = "epson,rx8130", 1165 .data = (void *)rx_8130 1166 }, 1167 { } 1168 }; 1169 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1170 #endif 1171 1172 #ifdef CONFIG_ACPI 1173 static const struct acpi_device_id ds1307_acpi_ids[] = { 1174 { .id = "DS1307", .driver_data = ds_1307 }, 1175 { .id = "DS1308", .driver_data = ds_1308 }, 1176 { .id = "DS1337", .driver_data = ds_1337 }, 1177 { .id = "DS1338", .driver_data = ds_1338 }, 1178 { .id = "DS1339", .driver_data = ds_1339 }, 1179 { .id = "DS1388", .driver_data = ds_1388 }, 1180 { .id = "DS1340", .driver_data = ds_1340 }, 1181 { .id = "DS1341", .driver_data = ds_1341 }, 1182 { .id = "DS3231", .driver_data = ds_3231 }, 1183 { .id = "M41T0", .driver_data = m41t0 }, 1184 { .id = "M41T00", .driver_data = m41t00 }, 1185 { .id = "M41T11", .driver_data = m41t11 }, 1186 { .id = "MCP7940X", .driver_data = mcp794xx }, 1187 { .id = "MCP7941X", .driver_data = mcp794xx }, 1188 { .id = "PT7C4338", .driver_data = ds_1307 }, 1189 { .id = "RX8025", .driver_data = rx_8025 }, 1190 { .id = "ISL12057", .driver_data = ds_1337 }, 1191 { .id = "RX8130", .driver_data = rx_8130 }, 1192 { } 1193 }; 1194 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); 1195 #endif 1196 1197 /* 1198 * The ds1337 and ds1339 both have two alarms, but we only use the first 1199 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1200 * signal; ds1339 chips have only one alarm signal. 1201 */ 1202 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1203 { 1204 struct ds1307 *ds1307 = dev_id; 1205 struct mutex *lock = &ds1307->rtc->ops_lock; 1206 int stat, ret; 1207 1208 mutex_lock(lock); 1209 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1210 if (ret) 1211 goto out; 1212 1213 if (stat & DS1337_BIT_A1I) { 1214 stat &= ~DS1337_BIT_A1I; 1215 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1216 1217 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1218 DS1337_BIT_A1IE, 0); 1219 if (ret) 1220 goto out; 1221 1222 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1223 } 1224 1225 out: 1226 mutex_unlock(lock); 1227 1228 return IRQ_HANDLED; 1229 } 1230 1231 /*----------------------------------------------------------------------*/ 1232 1233 static const struct rtc_class_ops ds13xx_rtc_ops = { 1234 .read_time = ds1307_get_time, 1235 .set_time = ds1307_set_time, 1236 .read_alarm = ds1337_read_alarm, 1237 .set_alarm = ds1337_set_alarm, 1238 .alarm_irq_enable = ds1307_alarm_irq_enable, 1239 }; 1240 1241 static ssize_t frequency_test_store(struct device *dev, 1242 struct device_attribute *attr, 1243 const char *buf, size_t count) 1244 { 1245 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1246 bool freq_test_en; 1247 int ret; 1248 1249 ret = kstrtobool(buf, &freq_test_en); 1250 if (ret) { 1251 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1252 return ret; 1253 } 1254 1255 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1256 freq_test_en ? M41TXX_BIT_FT : 0); 1257 1258 return count; 1259 } 1260 1261 static ssize_t frequency_test_show(struct device *dev, 1262 struct device_attribute *attr, 1263 char *buf) 1264 { 1265 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1266 unsigned int ctrl_reg; 1267 1268 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1269 1270 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : 1271 "off\n"); 1272 } 1273 1274 static DEVICE_ATTR_RW(frequency_test); 1275 1276 static struct attribute *rtc_freq_test_attrs[] = { 1277 &dev_attr_frequency_test.attr, 1278 NULL, 1279 }; 1280 1281 static const struct attribute_group rtc_freq_test_attr_group = { 1282 .attrs = rtc_freq_test_attrs, 1283 }; 1284 1285 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1286 { 1287 int err; 1288 1289 switch (ds1307->type) { 1290 case m41t0: 1291 case m41t00: 1292 case m41t11: 1293 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1294 if (err) 1295 return err; 1296 break; 1297 default: 1298 break; 1299 } 1300 1301 return 0; 1302 } 1303 1304 /*----------------------------------------------------------------------*/ 1305 1306 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1307 size_t bytes) 1308 { 1309 struct ds1307 *ds1307 = priv; 1310 const struct chip_desc *chip = &chips[ds1307->type]; 1311 1312 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1313 val, bytes); 1314 } 1315 1316 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1317 size_t bytes) 1318 { 1319 struct ds1307 *ds1307 = priv; 1320 const struct chip_desc *chip = &chips[ds1307->type]; 1321 1322 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1323 val, bytes); 1324 } 1325 1326 /*----------------------------------------------------------------------*/ 1327 1328 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1329 const struct chip_desc *chip) 1330 { 1331 u32 ohms, chargeable; 1332 bool diode = chip->charge_default; 1333 1334 if (!chip->do_trickle_setup) 1335 return 0; 1336 1337 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1338 &ohms) && chip->requires_trickle_resistor) 1339 return 0; 1340 1341 /* aux-voltage-chargeable takes precedence over the deprecated 1342 * trickle-diode-disable 1343 */ 1344 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable", 1345 &chargeable)) { 1346 switch (chargeable) { 1347 case 0: 1348 diode = false; 1349 break; 1350 case 1: 1351 diode = true; 1352 break; 1353 default: 1354 dev_warn(ds1307->dev, 1355 "unsupported aux-voltage-chargeable value\n"); 1356 break; 1357 } 1358 } else if (device_property_read_bool(ds1307->dev, 1359 "trickle-diode-disable")) { 1360 diode = false; 1361 } 1362 1363 return chip->do_trickle_setup(ds1307, ohms, diode); 1364 } 1365 1366 /*----------------------------------------------------------------------*/ 1367 1368 #if IS_REACHABLE(CONFIG_HWMON) 1369 1370 /* 1371 * Temperature sensor support for ds3231 devices. 1372 */ 1373 1374 #define DS3231_REG_TEMPERATURE 0x11 1375 1376 /* 1377 * A user-initiated temperature conversion is not started by this function, 1378 * so the temperature is updated once every 64 seconds. 1379 */ 1380 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1381 { 1382 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1383 u8 temp_buf[2]; 1384 s16 temp; 1385 int ret; 1386 1387 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1388 temp_buf, sizeof(temp_buf)); 1389 if (ret) 1390 return ret; 1391 /* 1392 * Temperature is represented as a 10-bit code with a resolution of 1393 * 0.25 degree celsius and encoded in two's complement format. 1394 */ 1395 temp = (temp_buf[0] << 8) | temp_buf[1]; 1396 temp >>= 6; 1397 *mC = temp * 250; 1398 1399 return 0; 1400 } 1401 1402 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1403 struct device_attribute *attr, char *buf) 1404 { 1405 int ret; 1406 s32 temp; 1407 1408 ret = ds3231_hwmon_read_temp(dev, &temp); 1409 if (ret) 1410 return ret; 1411 1412 return sprintf(buf, "%d\n", temp); 1413 } 1414 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1415 NULL, 0); 1416 1417 static struct attribute *ds3231_hwmon_attrs[] = { 1418 &sensor_dev_attr_temp1_input.dev_attr.attr, 1419 NULL, 1420 }; 1421 ATTRIBUTE_GROUPS(ds3231_hwmon); 1422 1423 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1424 { 1425 struct device *dev; 1426 1427 if (ds1307->type != ds_3231) 1428 return; 1429 1430 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1431 ds1307, 1432 ds3231_hwmon_groups); 1433 if (IS_ERR(dev)) { 1434 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1435 PTR_ERR(dev)); 1436 } 1437 } 1438 1439 #else 1440 1441 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1442 { 1443 } 1444 1445 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ 1446 1447 /*----------------------------------------------------------------------*/ 1448 1449 /* 1450 * Square-wave output support for DS3231 1451 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1452 */ 1453 #ifdef CONFIG_COMMON_CLK 1454 1455 enum { 1456 DS3231_CLK_SQW = 0, 1457 DS3231_CLK_32KHZ, 1458 }; 1459 1460 #define clk_sqw_to_ds1307(clk) \ 1461 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1462 #define clk_32khz_to_ds1307(clk) \ 1463 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1464 1465 static int ds3231_clk_sqw_rates[] = { 1466 1, 1467 1024, 1468 4096, 1469 8192, 1470 }; 1471 1472 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1473 { 1474 struct mutex *lock = &ds1307->rtc->ops_lock; 1475 int ret; 1476 1477 mutex_lock(lock); 1478 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1479 mask, value); 1480 mutex_unlock(lock); 1481 1482 return ret; 1483 } 1484 1485 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1486 unsigned long parent_rate) 1487 { 1488 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1489 int control, ret; 1490 int rate_sel = 0; 1491 1492 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1493 if (ret) 1494 return ret; 1495 if (control & DS1337_BIT_RS1) 1496 rate_sel += 1; 1497 if (control & DS1337_BIT_RS2) 1498 rate_sel += 2; 1499 1500 return ds3231_clk_sqw_rates[rate_sel]; 1501 } 1502 1503 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, 1504 unsigned long *prate) 1505 { 1506 int i; 1507 1508 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1509 if (ds3231_clk_sqw_rates[i] <= rate) 1510 return ds3231_clk_sqw_rates[i]; 1511 } 1512 1513 return 0; 1514 } 1515 1516 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1517 unsigned long parent_rate) 1518 { 1519 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1520 int control = 0; 1521 int rate_sel; 1522 1523 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1524 rate_sel++) { 1525 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1526 break; 1527 } 1528 1529 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1530 return -EINVAL; 1531 1532 if (rate_sel & 1) 1533 control |= DS1337_BIT_RS1; 1534 if (rate_sel & 2) 1535 control |= DS1337_BIT_RS2; 1536 1537 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1538 control); 1539 } 1540 1541 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1542 { 1543 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1544 1545 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1546 } 1547 1548 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1549 { 1550 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1551 1552 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1553 } 1554 1555 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1556 { 1557 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1558 int control, ret; 1559 1560 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1561 if (ret) 1562 return ret; 1563 1564 return !(control & DS1337_BIT_INTCN); 1565 } 1566 1567 static const struct clk_ops ds3231_clk_sqw_ops = { 1568 .prepare = ds3231_clk_sqw_prepare, 1569 .unprepare = ds3231_clk_sqw_unprepare, 1570 .is_prepared = ds3231_clk_sqw_is_prepared, 1571 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1572 .round_rate = ds3231_clk_sqw_round_rate, 1573 .set_rate = ds3231_clk_sqw_set_rate, 1574 }; 1575 1576 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1577 unsigned long parent_rate) 1578 { 1579 return 32768; 1580 } 1581 1582 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1583 { 1584 struct mutex *lock = &ds1307->rtc->ops_lock; 1585 int ret; 1586 1587 mutex_lock(lock); 1588 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1589 DS3231_BIT_EN32KHZ, 1590 enable ? DS3231_BIT_EN32KHZ : 0); 1591 mutex_unlock(lock); 1592 1593 return ret; 1594 } 1595 1596 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1597 { 1598 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1599 1600 return ds3231_clk_32khz_control(ds1307, true); 1601 } 1602 1603 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1604 { 1605 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1606 1607 ds3231_clk_32khz_control(ds1307, false); 1608 } 1609 1610 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1611 { 1612 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1613 int status, ret; 1614 1615 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1616 if (ret) 1617 return ret; 1618 1619 return !!(status & DS3231_BIT_EN32KHZ); 1620 } 1621 1622 static const struct clk_ops ds3231_clk_32khz_ops = { 1623 .prepare = ds3231_clk_32khz_prepare, 1624 .unprepare = ds3231_clk_32khz_unprepare, 1625 .is_prepared = ds3231_clk_32khz_is_prepared, 1626 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1627 }; 1628 1629 static struct clk_init_data ds3231_clks_init[] = { 1630 [DS3231_CLK_SQW] = { 1631 .name = "ds3231_clk_sqw", 1632 .ops = &ds3231_clk_sqw_ops, 1633 }, 1634 [DS3231_CLK_32KHZ] = { 1635 .name = "ds3231_clk_32khz", 1636 .ops = &ds3231_clk_32khz_ops, 1637 }, 1638 }; 1639 1640 static int ds3231_clks_register(struct ds1307 *ds1307) 1641 { 1642 struct device_node *node = ds1307->dev->of_node; 1643 struct clk_onecell_data *onecell; 1644 int i; 1645 1646 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1647 if (!onecell) 1648 return -ENOMEM; 1649 1650 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1651 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1652 sizeof(onecell->clks[0]), GFP_KERNEL); 1653 if (!onecell->clks) 1654 return -ENOMEM; 1655 1656 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1657 struct clk_init_data init = ds3231_clks_init[i]; 1658 1659 /* 1660 * Interrupt signal due to alarm conditions and square-wave 1661 * output share same pin, so don't initialize both. 1662 */ 1663 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags)) 1664 continue; 1665 1666 /* optional override of the clockname */ 1667 of_property_read_string_index(node, "clock-output-names", i, 1668 &init.name); 1669 ds1307->clks[i].init = &init; 1670 1671 onecell->clks[i] = devm_clk_register(ds1307->dev, 1672 &ds1307->clks[i]); 1673 if (IS_ERR(onecell->clks[i])) 1674 return PTR_ERR(onecell->clks[i]); 1675 } 1676 1677 if (!node) 1678 return 0; 1679 1680 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1681 1682 return 0; 1683 } 1684 1685 static void ds1307_clks_register(struct ds1307 *ds1307) 1686 { 1687 int ret; 1688 1689 if (ds1307->type != ds_3231) 1690 return; 1691 1692 ret = ds3231_clks_register(ds1307); 1693 if (ret) { 1694 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1695 ret); 1696 } 1697 } 1698 1699 #else 1700 1701 static void ds1307_clks_register(struct ds1307 *ds1307) 1702 { 1703 } 1704 1705 #endif /* CONFIG_COMMON_CLK */ 1706 1707 #ifdef CONFIG_WATCHDOG_CORE 1708 static const struct watchdog_info ds1388_wdt_info = { 1709 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 1710 .identity = "DS1388 watchdog", 1711 }; 1712 1713 static const struct watchdog_ops ds1388_wdt_ops = { 1714 .owner = THIS_MODULE, 1715 .start = ds1388_wdt_start, 1716 .stop = ds1388_wdt_stop, 1717 .ping = ds1388_wdt_ping, 1718 .set_timeout = ds1388_wdt_set_timeout, 1719 1720 }; 1721 1722 static void ds1307_wdt_register(struct ds1307 *ds1307) 1723 { 1724 struct watchdog_device *wdt; 1725 int err; 1726 int val; 1727 1728 if (ds1307->type != ds_1388) 1729 return; 1730 1731 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL); 1732 if (!wdt) 1733 return; 1734 1735 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val); 1736 if (!err && val & DS1388_BIT_WF) 1737 wdt->bootstatus = WDIOF_CARDRESET; 1738 1739 wdt->info = &ds1388_wdt_info; 1740 wdt->ops = &ds1388_wdt_ops; 1741 wdt->timeout = 99; 1742 wdt->max_timeout = 99; 1743 wdt->min_timeout = 1; 1744 1745 watchdog_init_timeout(wdt, 0, ds1307->dev); 1746 watchdog_set_drvdata(wdt, ds1307); 1747 devm_watchdog_register_device(ds1307->dev, wdt); 1748 } 1749 #else 1750 static void ds1307_wdt_register(struct ds1307 *ds1307) 1751 { 1752 } 1753 #endif /* CONFIG_WATCHDOG_CORE */ 1754 1755 static const struct regmap_config regmap_config = { 1756 .reg_bits = 8, 1757 .val_bits = 8, 1758 }; 1759 1760 static int ds1307_probe(struct i2c_client *client, 1761 const struct i2c_device_id *id) 1762 { 1763 struct ds1307 *ds1307; 1764 int err = -ENODEV; 1765 int tmp; 1766 const struct chip_desc *chip; 1767 bool want_irq; 1768 bool ds1307_can_wakeup_device = false; 1769 unsigned char regs[8]; 1770 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1771 u8 trickle_charger_setup = 0; 1772 1773 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1774 if (!ds1307) 1775 return -ENOMEM; 1776 1777 dev_set_drvdata(&client->dev, ds1307); 1778 ds1307->dev = &client->dev; 1779 ds1307->name = client->name; 1780 1781 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1782 if (IS_ERR(ds1307->regmap)) { 1783 dev_err(ds1307->dev, "regmap allocation failed\n"); 1784 return PTR_ERR(ds1307->regmap); 1785 } 1786 1787 i2c_set_clientdata(client, ds1307); 1788 1789 if (client->dev.of_node) { 1790 ds1307->type = (enum ds_type) 1791 of_device_get_match_data(&client->dev); 1792 chip = &chips[ds1307->type]; 1793 } else if (id) { 1794 chip = &chips[id->driver_data]; 1795 ds1307->type = id->driver_data; 1796 } else { 1797 const struct acpi_device_id *acpi_id; 1798 1799 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids), 1800 ds1307->dev); 1801 if (!acpi_id) 1802 return -ENODEV; 1803 chip = &chips[acpi_id->driver_data]; 1804 ds1307->type = acpi_id->driver_data; 1805 } 1806 1807 want_irq = client->irq > 0 && chip->alarm; 1808 1809 if (!pdata) 1810 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1811 else if (pdata->trickle_charger_setup) 1812 trickle_charger_setup = pdata->trickle_charger_setup; 1813 1814 if (trickle_charger_setup && chip->trickle_charger_reg) { 1815 dev_dbg(ds1307->dev, 1816 "writing trickle charger info 0x%x to 0x%x\n", 1817 trickle_charger_setup, chip->trickle_charger_reg); 1818 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1819 trickle_charger_setup); 1820 } 1821 1822 #ifdef CONFIG_OF 1823 /* 1824 * For devices with no IRQ directly connected to the SoC, the RTC chip 1825 * can be forced as a wakeup source by stating that explicitly in 1826 * the device's .dts file using the "wakeup-source" boolean property. 1827 * If the "wakeup-source" property is set, don't request an IRQ. 1828 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1829 * if supported by the RTC. 1830 */ 1831 if (chip->alarm && of_property_read_bool(client->dev.of_node, 1832 "wakeup-source")) 1833 ds1307_can_wakeup_device = true; 1834 #endif 1835 1836 switch (ds1307->type) { 1837 case ds_1337: 1838 case ds_1339: 1839 case ds_1341: 1840 case ds_3231: 1841 /* get registers that the "rtc" read below won't read... */ 1842 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1843 regs, 2); 1844 if (err) { 1845 dev_dbg(ds1307->dev, "read error %d\n", err); 1846 goto exit; 1847 } 1848 1849 /* oscillator off? turn it on, so clock can tick. */ 1850 if (regs[0] & DS1337_BIT_nEOSC) 1851 regs[0] &= ~DS1337_BIT_nEOSC; 1852 1853 /* 1854 * Using IRQ or defined as wakeup-source? 1855 * Disable the square wave and both alarms. 1856 * For some variants, be sure alarms can trigger when we're 1857 * running on Vbackup (BBSQI/BBSQW) 1858 */ 1859 if (want_irq || ds1307_can_wakeup_device) { 1860 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1861 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); 1862 } 1863 1864 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1865 regs[0]); 1866 1867 /* oscillator fault? clear flag, and warn */ 1868 if (regs[1] & DS1337_BIT_OSF) { 1869 regmap_write(ds1307->regmap, DS1337_REG_STATUS, 1870 regs[1] & ~DS1337_BIT_OSF); 1871 dev_warn(ds1307->dev, "SET TIME!\n"); 1872 } 1873 break; 1874 1875 case rx_8025: 1876 err = regmap_bulk_read(ds1307->regmap, 1877 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1878 if (err) { 1879 dev_dbg(ds1307->dev, "read error %d\n", err); 1880 goto exit; 1881 } 1882 1883 /* oscillator off? turn it on, so clock can tick. */ 1884 if (!(regs[1] & RX8025_BIT_XST)) { 1885 regs[1] |= RX8025_BIT_XST; 1886 regmap_write(ds1307->regmap, 1887 RX8025_REG_CTRL2 << 4 | 0x08, 1888 regs[1]); 1889 dev_warn(ds1307->dev, 1890 "oscillator stop detected - SET TIME!\n"); 1891 } 1892 1893 if (regs[1] & RX8025_BIT_PON) { 1894 regs[1] &= ~RX8025_BIT_PON; 1895 regmap_write(ds1307->regmap, 1896 RX8025_REG_CTRL2 << 4 | 0x08, 1897 regs[1]); 1898 dev_warn(ds1307->dev, "power-on detected\n"); 1899 } 1900 1901 if (regs[1] & RX8025_BIT_VDET) { 1902 regs[1] &= ~RX8025_BIT_VDET; 1903 regmap_write(ds1307->regmap, 1904 RX8025_REG_CTRL2 << 4 | 0x08, 1905 regs[1]); 1906 dev_warn(ds1307->dev, "voltage drop detected\n"); 1907 } 1908 1909 /* make sure we are running in 24hour mode */ 1910 if (!(regs[0] & RX8025_BIT_2412)) { 1911 u8 hour; 1912 1913 /* switch to 24 hour mode */ 1914 regmap_write(ds1307->regmap, 1915 RX8025_REG_CTRL1 << 4 | 0x08, 1916 regs[0] | RX8025_BIT_2412); 1917 1918 err = regmap_bulk_read(ds1307->regmap, 1919 RX8025_REG_CTRL1 << 4 | 0x08, 1920 regs, 2); 1921 if (err) { 1922 dev_dbg(ds1307->dev, "read error %d\n", err); 1923 goto exit; 1924 } 1925 1926 /* correct hour */ 1927 hour = bcd2bin(regs[DS1307_REG_HOUR]); 1928 if (hour == 12) 1929 hour = 0; 1930 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1931 hour += 12; 1932 1933 regmap_write(ds1307->regmap, 1934 DS1307_REG_HOUR << 4 | 0x08, hour); 1935 } 1936 break; 1937 case ds_1388: 1938 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp); 1939 if (err) { 1940 dev_dbg(ds1307->dev, "read error %d\n", err); 1941 goto exit; 1942 } 1943 1944 /* oscillator off? turn it on, so clock can tick. */ 1945 if (tmp & DS1388_BIT_nEOSC) { 1946 tmp &= ~DS1388_BIT_nEOSC; 1947 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp); 1948 } 1949 break; 1950 default: 1951 break; 1952 } 1953 1954 /* read RTC registers */ 1955 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 1956 sizeof(regs)); 1957 if (err) { 1958 dev_dbg(ds1307->dev, "read error %d\n", err); 1959 goto exit; 1960 } 1961 1962 if (ds1307->type == mcp794xx && 1963 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 1964 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 1965 regs[DS1307_REG_WDAY] | 1966 MCP794XX_BIT_VBATEN); 1967 } 1968 1969 tmp = regs[DS1307_REG_HOUR]; 1970 switch (ds1307->type) { 1971 case ds_1340: 1972 case m41t0: 1973 case m41t00: 1974 case m41t11: 1975 /* 1976 * NOTE: ignores century bits; fix before deploying 1977 * systems that will run through year 2100. 1978 */ 1979 break; 1980 case rx_8025: 1981 break; 1982 default: 1983 if (!(tmp & DS1307_BIT_12HR)) 1984 break; 1985 1986 /* 1987 * Be sure we're in 24 hour mode. Multi-master systems 1988 * take note... 1989 */ 1990 tmp = bcd2bin(tmp & 0x1f); 1991 if (tmp == 12) 1992 tmp = 0; 1993 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1994 tmp += 12; 1995 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 1996 bin2bcd(tmp)); 1997 } 1998 1999 if (want_irq || ds1307_can_wakeup_device) { 2000 device_set_wakeup_capable(ds1307->dev, true); 2001 set_bit(HAS_ALARM, &ds1307->flags); 2002 } 2003 2004 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 2005 if (IS_ERR(ds1307->rtc)) 2006 return PTR_ERR(ds1307->rtc); 2007 2008 if (ds1307_can_wakeup_device && !want_irq) { 2009 dev_info(ds1307->dev, 2010 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 2011 /* We cannot support UIE mode if we do not have an IRQ line */ 2012 ds1307->rtc->uie_unsupported = 1; 2013 } 2014 2015 if (want_irq) { 2016 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 2017 chip->irq_handler ?: ds1307_irq, 2018 IRQF_SHARED | IRQF_ONESHOT, 2019 ds1307->name, ds1307); 2020 if (err) { 2021 client->irq = 0; 2022 device_set_wakeup_capable(ds1307->dev, false); 2023 clear_bit(HAS_ALARM, &ds1307->flags); 2024 dev_err(ds1307->dev, "unable to request IRQ!\n"); 2025 } else { 2026 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 2027 } 2028 } 2029 2030 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 2031 err = ds1307_add_frequency_test(ds1307); 2032 if (err) 2033 return err; 2034 2035 err = rtc_register_device(ds1307->rtc); 2036 if (err) 2037 return err; 2038 2039 if (chip->nvram_size) { 2040 struct nvmem_config nvmem_cfg = { 2041 .name = "ds1307_nvram", 2042 .word_size = 1, 2043 .stride = 1, 2044 .size = chip->nvram_size, 2045 .reg_read = ds1307_nvram_read, 2046 .reg_write = ds1307_nvram_write, 2047 .priv = ds1307, 2048 }; 2049 2050 ds1307->rtc->nvram_old_abi = true; 2051 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 2052 } 2053 2054 ds1307_hwmon_register(ds1307); 2055 ds1307_clks_register(ds1307); 2056 ds1307_wdt_register(ds1307); 2057 2058 return 0; 2059 2060 exit: 2061 return err; 2062 } 2063 2064 static struct i2c_driver ds1307_driver = { 2065 .driver = { 2066 .name = "rtc-ds1307", 2067 .of_match_table = of_match_ptr(ds1307_of_match), 2068 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids), 2069 }, 2070 .probe = ds1307_probe, 2071 .id_table = ds1307_id, 2072 }; 2073 2074 module_i2c_driver(ds1307_driver); 2075 2076 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 2077 MODULE_LICENSE("GPL"); 2078