1 /* 2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 3 * 4 * Copyright (C) 2005 James Chapman (ds1337 core) 5 * Copyright (C) 2006 David Brownell 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/acpi.h> 15 #include <linux/bcd.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/rtc/ds1307.h> 21 #include <linux/rtc.h> 22 #include <linux/slab.h> 23 #include <linux/string.h> 24 #include <linux/hwmon.h> 25 #include <linux/hwmon-sysfs.h> 26 #include <linux/clk-provider.h> 27 #include <linux/regmap.h> 28 29 /* 30 * We can't determine type by probing, but if we expect pre-Linux code 31 * to have set the chip up as a clock (turning on the oscillator and 32 * setting the date and time), Linux can ignore the non-clock features. 33 * That's a natural job for a factory or repair bench. 34 */ 35 enum ds_type { 36 ds_1307, 37 ds_1308, 38 ds_1337, 39 ds_1338, 40 ds_1339, 41 ds_1340, 42 ds_1341, 43 ds_1388, 44 ds_3231, 45 m41t0, 46 m41t00, 47 m41t11, 48 mcp794xx, 49 rx_8025, 50 rx_8130, 51 last_ds_type /* always last */ 52 /* rs5c372 too? different address... */ 53 }; 54 55 /* RTC registers don't differ much, except for the century flag */ 56 #define DS1307_REG_SECS 0x00 /* 00-59 */ 57 # define DS1307_BIT_CH 0x80 58 # define DS1340_BIT_nEOSC 0x80 59 # define MCP794XX_BIT_ST 0x80 60 #define DS1307_REG_MIN 0x01 /* 00-59 */ 61 # define M41T0_BIT_OF 0x80 62 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 63 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 64 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 65 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 66 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 67 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 68 # define MCP794XX_BIT_VBATEN 0x08 69 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 70 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 71 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 72 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 73 74 /* 75 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 76 * start at 7, and they differ a LOT. Only control and status matter for 77 * basic RTC date and time functionality; be careful using them. 78 */ 79 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 80 # define DS1307_BIT_OUT 0x80 81 # define DS1338_BIT_OSF 0x20 82 # define DS1307_BIT_SQWE 0x10 83 # define DS1307_BIT_RS1 0x02 84 # define DS1307_BIT_RS0 0x01 85 #define DS1337_REG_CONTROL 0x0e 86 # define DS1337_BIT_nEOSC 0x80 87 # define DS1339_BIT_BBSQI 0x20 88 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 89 # define DS1337_BIT_RS2 0x10 90 # define DS1337_BIT_RS1 0x08 91 # define DS1337_BIT_INTCN 0x04 92 # define DS1337_BIT_A2IE 0x02 93 # define DS1337_BIT_A1IE 0x01 94 #define DS1340_REG_CONTROL 0x07 95 # define DS1340_BIT_OUT 0x80 96 # define DS1340_BIT_FT 0x40 97 # define DS1340_BIT_CALIB_SIGN 0x20 98 # define DS1340_M_CALIBRATION 0x1f 99 #define DS1340_REG_FLAG 0x09 100 # define DS1340_BIT_OSF 0x80 101 #define DS1337_REG_STATUS 0x0f 102 # define DS1337_BIT_OSF 0x80 103 # define DS3231_BIT_EN32KHZ 0x08 104 # define DS1337_BIT_A2I 0x02 105 # define DS1337_BIT_A1I 0x01 106 #define DS1339_REG_ALARM1_SECS 0x07 107 108 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 109 110 #define RX8025_REG_CTRL1 0x0e 111 # define RX8025_BIT_2412 0x20 112 #define RX8025_REG_CTRL2 0x0f 113 # define RX8025_BIT_PON 0x10 114 # define RX8025_BIT_VDET 0x40 115 # define RX8025_BIT_XST 0x20 116 117 #define RX8130_REG_ALARM_MIN 0x17 118 #define RX8130_REG_ALARM_HOUR 0x18 119 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 120 #define RX8130_REG_EXTENSION 0x1c 121 #define RX8130_REG_EXTENSION_WADA BIT(3) 122 #define RX8130_REG_FLAG 0x1d 123 #define RX8130_REG_FLAG_VLF BIT(1) 124 #define RX8130_REG_FLAG_AF BIT(3) 125 #define RX8130_REG_CONTROL0 0x1e 126 #define RX8130_REG_CONTROL0_AIE BIT(3) 127 128 #define MCP794XX_REG_CONTROL 0x07 129 # define MCP794XX_BIT_ALM0_EN 0x10 130 # define MCP794XX_BIT_ALM1_EN 0x20 131 #define MCP794XX_REG_ALARM0_BASE 0x0a 132 #define MCP794XX_REG_ALARM0_CTRL 0x0d 133 #define MCP794XX_REG_ALARM1_BASE 0x11 134 #define MCP794XX_REG_ALARM1_CTRL 0x14 135 # define MCP794XX_BIT_ALMX_IF BIT(3) 136 # define MCP794XX_BIT_ALMX_C0 BIT(4) 137 # define MCP794XX_BIT_ALMX_C1 BIT(5) 138 # define MCP794XX_BIT_ALMX_C2 BIT(6) 139 # define MCP794XX_BIT_ALMX_POL BIT(7) 140 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 141 MCP794XX_BIT_ALMX_C1 | \ 142 MCP794XX_BIT_ALMX_C2) 143 144 #define M41TXX_REG_CONTROL 0x07 145 # define M41TXX_BIT_OUT BIT(7) 146 # define M41TXX_BIT_FT BIT(6) 147 # define M41TXX_BIT_CALIB_SIGN BIT(5) 148 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 149 150 /* negative offset step is -2.034ppm */ 151 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 152 /* positive offset step is +4.068ppm */ 153 #define M41TXX_POS_OFFSET_STEP_PPB 4068 154 /* Min and max values supported with 'offset' interface by M41TXX */ 155 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 156 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 157 158 struct ds1307 { 159 enum ds_type type; 160 unsigned long flags; 161 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ 162 #define HAS_ALARM 1 /* bit 1 == irq claimed */ 163 struct device *dev; 164 struct regmap *regmap; 165 const char *name; 166 struct rtc_device *rtc; 167 #ifdef CONFIG_COMMON_CLK 168 struct clk_hw clks[2]; 169 #endif 170 }; 171 172 struct chip_desc { 173 unsigned alarm:1; 174 u16 nvram_offset; 175 u16 nvram_size; 176 u8 offset; /* register's offset */ 177 u8 century_reg; 178 u8 century_enable_bit; 179 u8 century_bit; 180 u8 bbsqi_bit; 181 irq_handler_t irq_handler; 182 const struct rtc_class_ops *rtc_ops; 183 u16 trickle_charger_reg; 184 u8 (*do_trickle_setup)(struct ds1307 *, u32, 185 bool); 186 }; 187 188 static const struct chip_desc chips[last_ds_type]; 189 190 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 191 { 192 struct ds1307 *ds1307 = dev_get_drvdata(dev); 193 int tmp, ret; 194 const struct chip_desc *chip = &chips[ds1307->type]; 195 u8 regs[7]; 196 197 if (ds1307->type == rx_8130) { 198 unsigned int regflag; 199 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 200 if (ret) { 201 dev_err(dev, "%s error %d\n", "read", ret); 202 return ret; 203 } 204 205 if (regflag & RX8130_REG_FLAG_VLF) { 206 dev_warn_once(dev, "oscillator failed, set time!\n"); 207 return -EINVAL; 208 } 209 } 210 211 /* read the RTC date and time registers all at once */ 212 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 213 sizeof(regs)); 214 if (ret) { 215 dev_err(dev, "%s error %d\n", "read", ret); 216 return ret; 217 } 218 219 dev_dbg(dev, "%s: %7ph\n", "read", regs); 220 221 /* if oscillator fail bit is set, no data can be trusted */ 222 if (ds1307->type == m41t0 && 223 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 224 dev_warn_once(dev, "oscillator failed, set time!\n"); 225 return -EINVAL; 226 } 227 228 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 229 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 230 tmp = regs[DS1307_REG_HOUR] & 0x3f; 231 t->tm_hour = bcd2bin(tmp); 232 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 233 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 234 tmp = regs[DS1307_REG_MONTH] & 0x1f; 235 t->tm_mon = bcd2bin(tmp) - 1; 236 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 237 238 if (regs[chip->century_reg] & chip->century_bit && 239 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 240 t->tm_year += 100; 241 242 dev_dbg(dev, "%s secs=%d, mins=%d, " 243 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 244 "read", t->tm_sec, t->tm_min, 245 t->tm_hour, t->tm_mday, 246 t->tm_mon, t->tm_year, t->tm_wday); 247 248 return 0; 249 } 250 251 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 252 { 253 struct ds1307 *ds1307 = dev_get_drvdata(dev); 254 const struct chip_desc *chip = &chips[ds1307->type]; 255 int result; 256 int tmp; 257 u8 regs[7]; 258 259 dev_dbg(dev, "%s secs=%d, mins=%d, " 260 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 261 "write", t->tm_sec, t->tm_min, 262 t->tm_hour, t->tm_mday, 263 t->tm_mon, t->tm_year, t->tm_wday); 264 265 if (t->tm_year < 100) 266 return -EINVAL; 267 268 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 269 if (t->tm_year > (chip->century_bit ? 299 : 199)) 270 return -EINVAL; 271 #else 272 if (t->tm_year > 199) 273 return -EINVAL; 274 #endif 275 276 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 277 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 278 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 279 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 280 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 281 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 282 283 /* assume 20YY not 19YY */ 284 tmp = t->tm_year - 100; 285 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 286 287 if (chip->century_enable_bit) 288 regs[chip->century_reg] |= chip->century_enable_bit; 289 if (t->tm_year > 199 && chip->century_bit) 290 regs[chip->century_reg] |= chip->century_bit; 291 292 if (ds1307->type == mcp794xx) { 293 /* 294 * these bits were cleared when preparing the date/time 295 * values and need to be set again before writing the 296 * regsfer out to the device. 297 */ 298 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 299 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 300 } 301 302 dev_dbg(dev, "%s: %7ph\n", "write", regs); 303 304 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 305 sizeof(regs)); 306 if (result) { 307 dev_err(dev, "%s error %d\n", "write", result); 308 return result; 309 } 310 311 if (ds1307->type == rx_8130) { 312 /* clear Voltage Loss Flag as data is available now */ 313 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 314 ~(u8)RX8130_REG_FLAG_VLF); 315 if (result) { 316 dev_err(dev, "%s error %d\n", "write", result); 317 return result; 318 } 319 } 320 321 return 0; 322 } 323 324 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 325 { 326 struct ds1307 *ds1307 = dev_get_drvdata(dev); 327 int ret; 328 u8 regs[9]; 329 330 if (!test_bit(HAS_ALARM, &ds1307->flags)) 331 return -EINVAL; 332 333 /* read all ALARM1, ALARM2, and status registers at once */ 334 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 335 regs, sizeof(regs)); 336 if (ret) { 337 dev_err(dev, "%s error %d\n", "alarm read", ret); 338 return ret; 339 } 340 341 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 342 ®s[0], ®s[4], ®s[7]); 343 344 /* 345 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 346 * and that all four fields are checked matches 347 */ 348 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 349 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 350 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 351 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 352 353 /* ... and status */ 354 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 355 t->pending = !!(regs[8] & DS1337_BIT_A1I); 356 357 dev_dbg(dev, "%s secs=%d, mins=%d, " 358 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 359 "alarm read", t->time.tm_sec, t->time.tm_min, 360 t->time.tm_hour, t->time.tm_mday, 361 t->enabled, t->pending); 362 363 return 0; 364 } 365 366 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 367 { 368 struct ds1307 *ds1307 = dev_get_drvdata(dev); 369 unsigned char regs[9]; 370 u8 control, status; 371 int ret; 372 373 if (!test_bit(HAS_ALARM, &ds1307->flags)) 374 return -EINVAL; 375 376 dev_dbg(dev, "%s secs=%d, mins=%d, " 377 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 378 "alarm set", t->time.tm_sec, t->time.tm_min, 379 t->time.tm_hour, t->time.tm_mday, 380 t->enabled, t->pending); 381 382 /* read current status of both alarms and the chip */ 383 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 384 sizeof(regs)); 385 if (ret) { 386 dev_err(dev, "%s error %d\n", "alarm write", ret); 387 return ret; 388 } 389 control = regs[7]; 390 status = regs[8]; 391 392 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 393 ®s[0], ®s[4], control, status); 394 395 /* set ALARM1, using 24 hour and day-of-month modes */ 396 regs[0] = bin2bcd(t->time.tm_sec); 397 regs[1] = bin2bcd(t->time.tm_min); 398 regs[2] = bin2bcd(t->time.tm_hour); 399 regs[3] = bin2bcd(t->time.tm_mday); 400 401 /* set ALARM2 to non-garbage */ 402 regs[4] = 0; 403 regs[5] = 0; 404 regs[6] = 0; 405 406 /* disable alarms */ 407 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 408 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 409 410 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 411 sizeof(regs)); 412 if (ret) { 413 dev_err(dev, "can't set alarm time\n"); 414 return ret; 415 } 416 417 /* optionally enable ALARM1 */ 418 if (t->enabled) { 419 dev_dbg(dev, "alarm IRQ armed\n"); 420 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 421 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 422 } 423 424 return 0; 425 } 426 427 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 428 { 429 struct ds1307 *ds1307 = dev_get_drvdata(dev); 430 431 if (!test_bit(HAS_ALARM, &ds1307->flags)) 432 return -ENOTTY; 433 434 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 435 DS1337_BIT_A1IE, 436 enabled ? DS1337_BIT_A1IE : 0); 437 } 438 439 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 440 { 441 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 442 DS1307_TRICKLE_CHARGER_NO_DIODE; 443 444 switch (ohms) { 445 case 250: 446 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 447 break; 448 case 2000: 449 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 450 break; 451 case 4000: 452 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 453 break; 454 default: 455 dev_warn(ds1307->dev, 456 "Unsupported ohm value %u in dt\n", ohms); 457 return 0; 458 } 459 return setup; 460 } 461 462 static irqreturn_t rx8130_irq(int irq, void *dev_id) 463 { 464 struct ds1307 *ds1307 = dev_id; 465 struct mutex *lock = &ds1307->rtc->ops_lock; 466 u8 ctl[3]; 467 int ret; 468 469 mutex_lock(lock); 470 471 /* Read control registers. */ 472 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 473 sizeof(ctl)); 474 if (ret < 0) 475 goto out; 476 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 477 goto out; 478 ctl[1] &= ~RX8130_REG_FLAG_AF; 479 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 480 481 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 482 sizeof(ctl)); 483 if (ret < 0) 484 goto out; 485 486 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 487 488 out: 489 mutex_unlock(lock); 490 491 return IRQ_HANDLED; 492 } 493 494 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 495 { 496 struct ds1307 *ds1307 = dev_get_drvdata(dev); 497 u8 ald[3], ctl[3]; 498 int ret; 499 500 if (!test_bit(HAS_ALARM, &ds1307->flags)) 501 return -EINVAL; 502 503 /* Read alarm registers. */ 504 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 505 sizeof(ald)); 506 if (ret < 0) 507 return ret; 508 509 /* Read control registers. */ 510 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 511 sizeof(ctl)); 512 if (ret < 0) 513 return ret; 514 515 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 516 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 517 518 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 519 t->time.tm_sec = -1; 520 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 521 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 522 t->time.tm_wday = -1; 523 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 524 t->time.tm_mon = -1; 525 t->time.tm_year = -1; 526 t->time.tm_yday = -1; 527 t->time.tm_isdst = -1; 528 529 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 530 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 531 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 532 533 return 0; 534 } 535 536 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 537 { 538 struct ds1307 *ds1307 = dev_get_drvdata(dev); 539 u8 ald[3], ctl[3]; 540 int ret; 541 542 if (!test_bit(HAS_ALARM, &ds1307->flags)) 543 return -EINVAL; 544 545 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 546 "enabled=%d pending=%d\n", __func__, 547 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 548 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 549 t->enabled, t->pending); 550 551 /* Read control registers. */ 552 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 553 sizeof(ctl)); 554 if (ret < 0) 555 return ret; 556 557 ctl[0] &= RX8130_REG_EXTENSION_WADA; 558 ctl[1] &= ~RX8130_REG_FLAG_AF; 559 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 560 561 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 562 sizeof(ctl)); 563 if (ret < 0) 564 return ret; 565 566 /* Hardware alarm precision is 1 minute! */ 567 ald[0] = bin2bcd(t->time.tm_min); 568 ald[1] = bin2bcd(t->time.tm_hour); 569 ald[2] = bin2bcd(t->time.tm_mday); 570 571 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 572 sizeof(ald)); 573 if (ret < 0) 574 return ret; 575 576 if (!t->enabled) 577 return 0; 578 579 ctl[2] |= RX8130_REG_CONTROL0_AIE; 580 581 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 582 } 583 584 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 585 { 586 struct ds1307 *ds1307 = dev_get_drvdata(dev); 587 int ret, reg; 588 589 if (!test_bit(HAS_ALARM, &ds1307->flags)) 590 return -EINVAL; 591 592 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 593 if (ret < 0) 594 return ret; 595 596 if (enabled) 597 reg |= RX8130_REG_CONTROL0_AIE; 598 else 599 reg &= ~RX8130_REG_CONTROL0_AIE; 600 601 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 602 } 603 604 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 605 { 606 struct ds1307 *ds1307 = dev_id; 607 struct mutex *lock = &ds1307->rtc->ops_lock; 608 int reg, ret; 609 610 mutex_lock(lock); 611 612 /* Check and clear alarm 0 interrupt flag. */ 613 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 614 if (ret) 615 goto out; 616 if (!(reg & MCP794XX_BIT_ALMX_IF)) 617 goto out; 618 reg &= ~MCP794XX_BIT_ALMX_IF; 619 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 620 if (ret) 621 goto out; 622 623 /* Disable alarm 0. */ 624 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 625 MCP794XX_BIT_ALM0_EN, 0); 626 if (ret) 627 goto out; 628 629 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 630 631 out: 632 mutex_unlock(lock); 633 634 return IRQ_HANDLED; 635 } 636 637 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 638 { 639 struct ds1307 *ds1307 = dev_get_drvdata(dev); 640 u8 regs[10]; 641 int ret; 642 643 if (!test_bit(HAS_ALARM, &ds1307->flags)) 644 return -EINVAL; 645 646 /* Read control and alarm 0 registers. */ 647 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 648 sizeof(regs)); 649 if (ret) 650 return ret; 651 652 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 653 654 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 655 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 656 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 657 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 658 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 659 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 660 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 661 t->time.tm_year = -1; 662 t->time.tm_yday = -1; 663 t->time.tm_isdst = -1; 664 665 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 666 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 667 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 668 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 669 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 670 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 671 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 672 673 return 0; 674 } 675 676 /* 677 * We may have a random RTC weekday, therefore calculate alarm weekday based 678 * on current weekday we read from the RTC timekeeping regs 679 */ 680 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 681 { 682 struct rtc_time tm_now; 683 int days_now, days_alarm, ret; 684 685 ret = ds1307_get_time(dev, &tm_now); 686 if (ret) 687 return ret; 688 689 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 690 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 691 692 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 693 } 694 695 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 696 { 697 struct ds1307 *ds1307 = dev_get_drvdata(dev); 698 unsigned char regs[10]; 699 int wday, ret; 700 701 if (!test_bit(HAS_ALARM, &ds1307->flags)) 702 return -EINVAL; 703 704 wday = mcp794xx_alm_weekday(dev, &t->time); 705 if (wday < 0) 706 return wday; 707 708 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 709 "enabled=%d pending=%d\n", __func__, 710 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 711 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 712 t->enabled, t->pending); 713 714 /* Read control and alarm 0 registers. */ 715 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 716 sizeof(regs)); 717 if (ret) 718 return ret; 719 720 /* Set alarm 0, using 24-hour and day-of-month modes. */ 721 regs[3] = bin2bcd(t->time.tm_sec); 722 regs[4] = bin2bcd(t->time.tm_min); 723 regs[5] = bin2bcd(t->time.tm_hour); 724 regs[6] = wday; 725 regs[7] = bin2bcd(t->time.tm_mday); 726 regs[8] = bin2bcd(t->time.tm_mon + 1); 727 728 /* Clear the alarm 0 interrupt flag. */ 729 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 730 /* Set alarm match: second, minute, hour, day, date, month. */ 731 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 732 /* Disable interrupt. We will not enable until completely programmed */ 733 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 734 735 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 736 sizeof(regs)); 737 if (ret) 738 return ret; 739 740 if (!t->enabled) 741 return 0; 742 regs[0] |= MCP794XX_BIT_ALM0_EN; 743 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 744 } 745 746 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 747 { 748 struct ds1307 *ds1307 = dev_get_drvdata(dev); 749 750 if (!test_bit(HAS_ALARM, &ds1307->flags)) 751 return -EINVAL; 752 753 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 754 MCP794XX_BIT_ALM0_EN, 755 enabled ? MCP794XX_BIT_ALM0_EN : 0); 756 } 757 758 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 759 { 760 struct ds1307 *ds1307 = dev_get_drvdata(dev); 761 unsigned int ctrl_reg; 762 u8 val; 763 764 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 765 766 val = ctrl_reg & M41TXX_M_CALIBRATION; 767 768 /* check if positive */ 769 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 770 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 771 else 772 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 773 774 return 0; 775 } 776 777 static int m41txx_rtc_set_offset(struct device *dev, long offset) 778 { 779 struct ds1307 *ds1307 = dev_get_drvdata(dev); 780 unsigned int ctrl_reg; 781 782 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 783 return -ERANGE; 784 785 if (offset >= 0) { 786 ctrl_reg = DIV_ROUND_CLOSEST(offset, 787 M41TXX_POS_OFFSET_STEP_PPB); 788 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 789 } else { 790 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 791 M41TXX_NEG_OFFSET_STEP_PPB); 792 } 793 794 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 795 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 796 ctrl_reg); 797 } 798 799 static const struct rtc_class_ops rx8130_rtc_ops = { 800 .read_time = ds1307_get_time, 801 .set_time = ds1307_set_time, 802 .read_alarm = rx8130_read_alarm, 803 .set_alarm = rx8130_set_alarm, 804 .alarm_irq_enable = rx8130_alarm_irq_enable, 805 }; 806 807 static const struct rtc_class_ops mcp794xx_rtc_ops = { 808 .read_time = ds1307_get_time, 809 .set_time = ds1307_set_time, 810 .read_alarm = mcp794xx_read_alarm, 811 .set_alarm = mcp794xx_set_alarm, 812 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 813 }; 814 815 static const struct rtc_class_ops m41txx_rtc_ops = { 816 .read_time = ds1307_get_time, 817 .set_time = ds1307_set_time, 818 .read_alarm = ds1337_read_alarm, 819 .set_alarm = ds1337_set_alarm, 820 .alarm_irq_enable = ds1307_alarm_irq_enable, 821 .read_offset = m41txx_rtc_read_offset, 822 .set_offset = m41txx_rtc_set_offset, 823 }; 824 825 static const struct chip_desc chips[last_ds_type] = { 826 [ds_1307] = { 827 .nvram_offset = 8, 828 .nvram_size = 56, 829 }, 830 [ds_1308] = { 831 .nvram_offset = 8, 832 .nvram_size = 56, 833 }, 834 [ds_1337] = { 835 .alarm = 1, 836 .century_reg = DS1307_REG_MONTH, 837 .century_bit = DS1337_BIT_CENTURY, 838 }, 839 [ds_1338] = { 840 .nvram_offset = 8, 841 .nvram_size = 56, 842 }, 843 [ds_1339] = { 844 .alarm = 1, 845 .century_reg = DS1307_REG_MONTH, 846 .century_bit = DS1337_BIT_CENTURY, 847 .bbsqi_bit = DS1339_BIT_BBSQI, 848 .trickle_charger_reg = 0x10, 849 .do_trickle_setup = &do_trickle_setup_ds1339, 850 }, 851 [ds_1340] = { 852 .century_reg = DS1307_REG_HOUR, 853 .century_enable_bit = DS1340_BIT_CENTURY_EN, 854 .century_bit = DS1340_BIT_CENTURY, 855 .do_trickle_setup = &do_trickle_setup_ds1339, 856 .trickle_charger_reg = 0x08, 857 }, 858 [ds_1341] = { 859 .century_reg = DS1307_REG_MONTH, 860 .century_bit = DS1337_BIT_CENTURY, 861 }, 862 [ds_1388] = { 863 .offset = 1, 864 .trickle_charger_reg = 0x0a, 865 }, 866 [ds_3231] = { 867 .alarm = 1, 868 .century_reg = DS1307_REG_MONTH, 869 .century_bit = DS1337_BIT_CENTURY, 870 .bbsqi_bit = DS3231_BIT_BBSQW, 871 }, 872 [rx_8130] = { 873 .alarm = 1, 874 /* this is battery backed SRAM */ 875 .nvram_offset = 0x20, 876 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 877 .offset = 0x10, 878 .irq_handler = rx8130_irq, 879 .rtc_ops = &rx8130_rtc_ops, 880 }, 881 [m41t0] = { 882 .rtc_ops = &m41txx_rtc_ops, 883 }, 884 [m41t00] = { 885 .rtc_ops = &m41txx_rtc_ops, 886 }, 887 [m41t11] = { 888 /* this is battery backed SRAM */ 889 .nvram_offset = 8, 890 .nvram_size = 56, 891 .rtc_ops = &m41txx_rtc_ops, 892 }, 893 [mcp794xx] = { 894 .alarm = 1, 895 /* this is battery backed SRAM */ 896 .nvram_offset = 0x20, 897 .nvram_size = 0x40, 898 .irq_handler = mcp794xx_irq, 899 .rtc_ops = &mcp794xx_rtc_ops, 900 }, 901 }; 902 903 static const struct i2c_device_id ds1307_id[] = { 904 { "ds1307", ds_1307 }, 905 { "ds1308", ds_1308 }, 906 { "ds1337", ds_1337 }, 907 { "ds1338", ds_1338 }, 908 { "ds1339", ds_1339 }, 909 { "ds1388", ds_1388 }, 910 { "ds1340", ds_1340 }, 911 { "ds1341", ds_1341 }, 912 { "ds3231", ds_3231 }, 913 { "m41t0", m41t0 }, 914 { "m41t00", m41t00 }, 915 { "m41t11", m41t11 }, 916 { "mcp7940x", mcp794xx }, 917 { "mcp7941x", mcp794xx }, 918 { "pt7c4338", ds_1307 }, 919 { "rx8025", rx_8025 }, 920 { "isl12057", ds_1337 }, 921 { "rx8130", rx_8130 }, 922 { } 923 }; 924 MODULE_DEVICE_TABLE(i2c, ds1307_id); 925 926 #ifdef CONFIG_OF 927 static const struct of_device_id ds1307_of_match[] = { 928 { 929 .compatible = "dallas,ds1307", 930 .data = (void *)ds_1307 931 }, 932 { 933 .compatible = "dallas,ds1308", 934 .data = (void *)ds_1308 935 }, 936 { 937 .compatible = "dallas,ds1337", 938 .data = (void *)ds_1337 939 }, 940 { 941 .compatible = "dallas,ds1338", 942 .data = (void *)ds_1338 943 }, 944 { 945 .compatible = "dallas,ds1339", 946 .data = (void *)ds_1339 947 }, 948 { 949 .compatible = "dallas,ds1388", 950 .data = (void *)ds_1388 951 }, 952 { 953 .compatible = "dallas,ds1340", 954 .data = (void *)ds_1340 955 }, 956 { 957 .compatible = "dallas,ds1341", 958 .data = (void *)ds_1341 959 }, 960 { 961 .compatible = "maxim,ds3231", 962 .data = (void *)ds_3231 963 }, 964 { 965 .compatible = "st,m41t0", 966 .data = (void *)m41t0 967 }, 968 { 969 .compatible = "st,m41t00", 970 .data = (void *)m41t00 971 }, 972 { 973 .compatible = "st,m41t11", 974 .data = (void *)m41t11 975 }, 976 { 977 .compatible = "microchip,mcp7940x", 978 .data = (void *)mcp794xx 979 }, 980 { 981 .compatible = "microchip,mcp7941x", 982 .data = (void *)mcp794xx 983 }, 984 { 985 .compatible = "pericom,pt7c4338", 986 .data = (void *)ds_1307 987 }, 988 { 989 .compatible = "epson,rx8025", 990 .data = (void *)rx_8025 991 }, 992 { 993 .compatible = "isil,isl12057", 994 .data = (void *)ds_1337 995 }, 996 { 997 .compatible = "epson,rx8130", 998 .data = (void *)rx_8130 999 }, 1000 { } 1001 }; 1002 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1003 #endif 1004 1005 #ifdef CONFIG_ACPI 1006 static const struct acpi_device_id ds1307_acpi_ids[] = { 1007 { .id = "DS1307", .driver_data = ds_1307 }, 1008 { .id = "DS1308", .driver_data = ds_1308 }, 1009 { .id = "DS1337", .driver_data = ds_1337 }, 1010 { .id = "DS1338", .driver_data = ds_1338 }, 1011 { .id = "DS1339", .driver_data = ds_1339 }, 1012 { .id = "DS1388", .driver_data = ds_1388 }, 1013 { .id = "DS1340", .driver_data = ds_1340 }, 1014 { .id = "DS1341", .driver_data = ds_1341 }, 1015 { .id = "DS3231", .driver_data = ds_3231 }, 1016 { .id = "M41T0", .driver_data = m41t0 }, 1017 { .id = "M41T00", .driver_data = m41t00 }, 1018 { .id = "M41T11", .driver_data = m41t11 }, 1019 { .id = "MCP7940X", .driver_data = mcp794xx }, 1020 { .id = "MCP7941X", .driver_data = mcp794xx }, 1021 { .id = "PT7C4338", .driver_data = ds_1307 }, 1022 { .id = "RX8025", .driver_data = rx_8025 }, 1023 { .id = "ISL12057", .driver_data = ds_1337 }, 1024 { .id = "RX8130", .driver_data = rx_8130 }, 1025 { } 1026 }; 1027 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); 1028 #endif 1029 1030 /* 1031 * The ds1337 and ds1339 both have two alarms, but we only use the first 1032 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1033 * signal; ds1339 chips have only one alarm signal. 1034 */ 1035 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1036 { 1037 struct ds1307 *ds1307 = dev_id; 1038 struct mutex *lock = &ds1307->rtc->ops_lock; 1039 int stat, ret; 1040 1041 mutex_lock(lock); 1042 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1043 if (ret) 1044 goto out; 1045 1046 if (stat & DS1337_BIT_A1I) { 1047 stat &= ~DS1337_BIT_A1I; 1048 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1049 1050 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1051 DS1337_BIT_A1IE, 0); 1052 if (ret) 1053 goto out; 1054 1055 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1056 } 1057 1058 out: 1059 mutex_unlock(lock); 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 /*----------------------------------------------------------------------*/ 1065 1066 static const struct rtc_class_ops ds13xx_rtc_ops = { 1067 .read_time = ds1307_get_time, 1068 .set_time = ds1307_set_time, 1069 .read_alarm = ds1337_read_alarm, 1070 .set_alarm = ds1337_set_alarm, 1071 .alarm_irq_enable = ds1307_alarm_irq_enable, 1072 }; 1073 1074 static ssize_t frequency_test_store(struct device *dev, 1075 struct device_attribute *attr, 1076 const char *buf, size_t count) 1077 { 1078 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1079 bool freq_test_en; 1080 int ret; 1081 1082 ret = kstrtobool(buf, &freq_test_en); 1083 if (ret) { 1084 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1085 return ret; 1086 } 1087 1088 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1089 freq_test_en ? M41TXX_BIT_FT : 0); 1090 1091 return count; 1092 } 1093 1094 static ssize_t frequency_test_show(struct device *dev, 1095 struct device_attribute *attr, 1096 char *buf) 1097 { 1098 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1099 unsigned int ctrl_reg; 1100 1101 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1102 1103 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : 1104 "off\n"); 1105 } 1106 1107 static DEVICE_ATTR_RW(frequency_test); 1108 1109 static struct attribute *rtc_freq_test_attrs[] = { 1110 &dev_attr_frequency_test.attr, 1111 NULL, 1112 }; 1113 1114 static const struct attribute_group rtc_freq_test_attr_group = { 1115 .attrs = rtc_freq_test_attrs, 1116 }; 1117 1118 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1119 { 1120 int err; 1121 1122 switch (ds1307->type) { 1123 case m41t0: 1124 case m41t00: 1125 case m41t11: 1126 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1127 if (err) 1128 return err; 1129 break; 1130 default: 1131 break; 1132 } 1133 1134 return 0; 1135 } 1136 1137 /*----------------------------------------------------------------------*/ 1138 1139 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1140 size_t bytes) 1141 { 1142 struct ds1307 *ds1307 = priv; 1143 const struct chip_desc *chip = &chips[ds1307->type]; 1144 1145 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1146 val, bytes); 1147 } 1148 1149 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1150 size_t bytes) 1151 { 1152 struct ds1307 *ds1307 = priv; 1153 const struct chip_desc *chip = &chips[ds1307->type]; 1154 1155 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1156 val, bytes); 1157 } 1158 1159 /*----------------------------------------------------------------------*/ 1160 1161 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1162 const struct chip_desc *chip) 1163 { 1164 u32 ohms; 1165 bool diode = true; 1166 1167 if (!chip->do_trickle_setup) 1168 return 0; 1169 1170 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1171 &ohms)) 1172 return 0; 1173 1174 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable")) 1175 diode = false; 1176 1177 return chip->do_trickle_setup(ds1307, ohms, diode); 1178 } 1179 1180 /*----------------------------------------------------------------------*/ 1181 1182 #if IS_REACHABLE(CONFIG_HWMON) 1183 1184 /* 1185 * Temperature sensor support for ds3231 devices. 1186 */ 1187 1188 #define DS3231_REG_TEMPERATURE 0x11 1189 1190 /* 1191 * A user-initiated temperature conversion is not started by this function, 1192 * so the temperature is updated once every 64 seconds. 1193 */ 1194 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1195 { 1196 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1197 u8 temp_buf[2]; 1198 s16 temp; 1199 int ret; 1200 1201 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1202 temp_buf, sizeof(temp_buf)); 1203 if (ret) 1204 return ret; 1205 /* 1206 * Temperature is represented as a 10-bit code with a resolution of 1207 * 0.25 degree celsius and encoded in two's complement format. 1208 */ 1209 temp = (temp_buf[0] << 8) | temp_buf[1]; 1210 temp >>= 6; 1211 *mC = temp * 250; 1212 1213 return 0; 1214 } 1215 1216 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1217 struct device_attribute *attr, char *buf) 1218 { 1219 int ret; 1220 s32 temp; 1221 1222 ret = ds3231_hwmon_read_temp(dev, &temp); 1223 if (ret) 1224 return ret; 1225 1226 return sprintf(buf, "%d\n", temp); 1227 } 1228 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1229 NULL, 0); 1230 1231 static struct attribute *ds3231_hwmon_attrs[] = { 1232 &sensor_dev_attr_temp1_input.dev_attr.attr, 1233 NULL, 1234 }; 1235 ATTRIBUTE_GROUPS(ds3231_hwmon); 1236 1237 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1238 { 1239 struct device *dev; 1240 1241 if (ds1307->type != ds_3231) 1242 return; 1243 1244 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1245 ds1307, 1246 ds3231_hwmon_groups); 1247 if (IS_ERR(dev)) { 1248 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1249 PTR_ERR(dev)); 1250 } 1251 } 1252 1253 #else 1254 1255 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1256 { 1257 } 1258 1259 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ 1260 1261 /*----------------------------------------------------------------------*/ 1262 1263 /* 1264 * Square-wave output support for DS3231 1265 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1266 */ 1267 #ifdef CONFIG_COMMON_CLK 1268 1269 enum { 1270 DS3231_CLK_SQW = 0, 1271 DS3231_CLK_32KHZ, 1272 }; 1273 1274 #define clk_sqw_to_ds1307(clk) \ 1275 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1276 #define clk_32khz_to_ds1307(clk) \ 1277 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1278 1279 static int ds3231_clk_sqw_rates[] = { 1280 1, 1281 1024, 1282 4096, 1283 8192, 1284 }; 1285 1286 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1287 { 1288 struct mutex *lock = &ds1307->rtc->ops_lock; 1289 int ret; 1290 1291 mutex_lock(lock); 1292 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1293 mask, value); 1294 mutex_unlock(lock); 1295 1296 return ret; 1297 } 1298 1299 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1300 unsigned long parent_rate) 1301 { 1302 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1303 int control, ret; 1304 int rate_sel = 0; 1305 1306 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1307 if (ret) 1308 return ret; 1309 if (control & DS1337_BIT_RS1) 1310 rate_sel += 1; 1311 if (control & DS1337_BIT_RS2) 1312 rate_sel += 2; 1313 1314 return ds3231_clk_sqw_rates[rate_sel]; 1315 } 1316 1317 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, 1318 unsigned long *prate) 1319 { 1320 int i; 1321 1322 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1323 if (ds3231_clk_sqw_rates[i] <= rate) 1324 return ds3231_clk_sqw_rates[i]; 1325 } 1326 1327 return 0; 1328 } 1329 1330 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1331 unsigned long parent_rate) 1332 { 1333 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1334 int control = 0; 1335 int rate_sel; 1336 1337 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1338 rate_sel++) { 1339 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1340 break; 1341 } 1342 1343 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1344 return -EINVAL; 1345 1346 if (rate_sel & 1) 1347 control |= DS1337_BIT_RS1; 1348 if (rate_sel & 2) 1349 control |= DS1337_BIT_RS2; 1350 1351 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1352 control); 1353 } 1354 1355 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1356 { 1357 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1358 1359 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1360 } 1361 1362 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1363 { 1364 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1365 1366 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1367 } 1368 1369 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1370 { 1371 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1372 int control, ret; 1373 1374 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1375 if (ret) 1376 return ret; 1377 1378 return !(control & DS1337_BIT_INTCN); 1379 } 1380 1381 static const struct clk_ops ds3231_clk_sqw_ops = { 1382 .prepare = ds3231_clk_sqw_prepare, 1383 .unprepare = ds3231_clk_sqw_unprepare, 1384 .is_prepared = ds3231_clk_sqw_is_prepared, 1385 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1386 .round_rate = ds3231_clk_sqw_round_rate, 1387 .set_rate = ds3231_clk_sqw_set_rate, 1388 }; 1389 1390 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1391 unsigned long parent_rate) 1392 { 1393 return 32768; 1394 } 1395 1396 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1397 { 1398 struct mutex *lock = &ds1307->rtc->ops_lock; 1399 int ret; 1400 1401 mutex_lock(lock); 1402 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1403 DS3231_BIT_EN32KHZ, 1404 enable ? DS3231_BIT_EN32KHZ : 0); 1405 mutex_unlock(lock); 1406 1407 return ret; 1408 } 1409 1410 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1411 { 1412 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1413 1414 return ds3231_clk_32khz_control(ds1307, true); 1415 } 1416 1417 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1418 { 1419 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1420 1421 ds3231_clk_32khz_control(ds1307, false); 1422 } 1423 1424 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1425 { 1426 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1427 int status, ret; 1428 1429 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1430 if (ret) 1431 return ret; 1432 1433 return !!(status & DS3231_BIT_EN32KHZ); 1434 } 1435 1436 static const struct clk_ops ds3231_clk_32khz_ops = { 1437 .prepare = ds3231_clk_32khz_prepare, 1438 .unprepare = ds3231_clk_32khz_unprepare, 1439 .is_prepared = ds3231_clk_32khz_is_prepared, 1440 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1441 }; 1442 1443 static struct clk_init_data ds3231_clks_init[] = { 1444 [DS3231_CLK_SQW] = { 1445 .name = "ds3231_clk_sqw", 1446 .ops = &ds3231_clk_sqw_ops, 1447 }, 1448 [DS3231_CLK_32KHZ] = { 1449 .name = "ds3231_clk_32khz", 1450 .ops = &ds3231_clk_32khz_ops, 1451 }, 1452 }; 1453 1454 static int ds3231_clks_register(struct ds1307 *ds1307) 1455 { 1456 struct device_node *node = ds1307->dev->of_node; 1457 struct clk_onecell_data *onecell; 1458 int i; 1459 1460 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1461 if (!onecell) 1462 return -ENOMEM; 1463 1464 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1465 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1466 sizeof(onecell->clks[0]), GFP_KERNEL); 1467 if (!onecell->clks) 1468 return -ENOMEM; 1469 1470 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1471 struct clk_init_data init = ds3231_clks_init[i]; 1472 1473 /* 1474 * Interrupt signal due to alarm conditions and square-wave 1475 * output share same pin, so don't initialize both. 1476 */ 1477 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags)) 1478 continue; 1479 1480 /* optional override of the clockname */ 1481 of_property_read_string_index(node, "clock-output-names", i, 1482 &init.name); 1483 ds1307->clks[i].init = &init; 1484 1485 onecell->clks[i] = devm_clk_register(ds1307->dev, 1486 &ds1307->clks[i]); 1487 if (IS_ERR(onecell->clks[i])) 1488 return PTR_ERR(onecell->clks[i]); 1489 } 1490 1491 if (!node) 1492 return 0; 1493 1494 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1495 1496 return 0; 1497 } 1498 1499 static void ds1307_clks_register(struct ds1307 *ds1307) 1500 { 1501 int ret; 1502 1503 if (ds1307->type != ds_3231) 1504 return; 1505 1506 ret = ds3231_clks_register(ds1307); 1507 if (ret) { 1508 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1509 ret); 1510 } 1511 } 1512 1513 #else 1514 1515 static void ds1307_clks_register(struct ds1307 *ds1307) 1516 { 1517 } 1518 1519 #endif /* CONFIG_COMMON_CLK */ 1520 1521 static const struct regmap_config regmap_config = { 1522 .reg_bits = 8, 1523 .val_bits = 8, 1524 }; 1525 1526 static int ds1307_probe(struct i2c_client *client, 1527 const struct i2c_device_id *id) 1528 { 1529 struct ds1307 *ds1307; 1530 int err = -ENODEV; 1531 int tmp; 1532 const struct chip_desc *chip; 1533 bool want_irq; 1534 bool ds1307_can_wakeup_device = false; 1535 unsigned char regs[8]; 1536 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1537 u8 trickle_charger_setup = 0; 1538 1539 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1540 if (!ds1307) 1541 return -ENOMEM; 1542 1543 dev_set_drvdata(&client->dev, ds1307); 1544 ds1307->dev = &client->dev; 1545 ds1307->name = client->name; 1546 1547 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1548 if (IS_ERR(ds1307->regmap)) { 1549 dev_err(ds1307->dev, "regmap allocation failed\n"); 1550 return PTR_ERR(ds1307->regmap); 1551 } 1552 1553 i2c_set_clientdata(client, ds1307); 1554 1555 if (client->dev.of_node) { 1556 ds1307->type = (enum ds_type) 1557 of_device_get_match_data(&client->dev); 1558 chip = &chips[ds1307->type]; 1559 } else if (id) { 1560 chip = &chips[id->driver_data]; 1561 ds1307->type = id->driver_data; 1562 } else { 1563 const struct acpi_device_id *acpi_id; 1564 1565 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids), 1566 ds1307->dev); 1567 if (!acpi_id) 1568 return -ENODEV; 1569 chip = &chips[acpi_id->driver_data]; 1570 ds1307->type = acpi_id->driver_data; 1571 } 1572 1573 want_irq = client->irq > 0 && chip->alarm; 1574 1575 if (!pdata) 1576 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1577 else if (pdata->trickle_charger_setup) 1578 trickle_charger_setup = pdata->trickle_charger_setup; 1579 1580 if (trickle_charger_setup && chip->trickle_charger_reg) { 1581 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 1582 dev_dbg(ds1307->dev, 1583 "writing trickle charger info 0x%x to 0x%x\n", 1584 trickle_charger_setup, chip->trickle_charger_reg); 1585 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1586 trickle_charger_setup); 1587 } 1588 1589 #ifdef CONFIG_OF 1590 /* 1591 * For devices with no IRQ directly connected to the SoC, the RTC chip 1592 * can be forced as a wakeup source by stating that explicitly in 1593 * the device's .dts file using the "wakeup-source" boolean property. 1594 * If the "wakeup-source" property is set, don't request an IRQ. 1595 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1596 * if supported by the RTC. 1597 */ 1598 if (chip->alarm && of_property_read_bool(client->dev.of_node, 1599 "wakeup-source")) 1600 ds1307_can_wakeup_device = true; 1601 #endif 1602 1603 switch (ds1307->type) { 1604 case ds_1337: 1605 case ds_1339: 1606 case ds_1341: 1607 case ds_3231: 1608 /* get registers that the "rtc" read below won't read... */ 1609 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1610 regs, 2); 1611 if (err) { 1612 dev_dbg(ds1307->dev, "read error %d\n", err); 1613 goto exit; 1614 } 1615 1616 /* oscillator off? turn it on, so clock can tick. */ 1617 if (regs[0] & DS1337_BIT_nEOSC) 1618 regs[0] &= ~DS1337_BIT_nEOSC; 1619 1620 /* 1621 * Using IRQ or defined as wakeup-source? 1622 * Disable the square wave and both alarms. 1623 * For some variants, be sure alarms can trigger when we're 1624 * running on Vbackup (BBSQI/BBSQW) 1625 */ 1626 if (want_irq || ds1307_can_wakeup_device) { 1627 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1628 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); 1629 } 1630 1631 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1632 regs[0]); 1633 1634 /* oscillator fault? clear flag, and warn */ 1635 if (regs[1] & DS1337_BIT_OSF) { 1636 regmap_write(ds1307->regmap, DS1337_REG_STATUS, 1637 regs[1] & ~DS1337_BIT_OSF); 1638 dev_warn(ds1307->dev, "SET TIME!\n"); 1639 } 1640 break; 1641 1642 case rx_8025: 1643 err = regmap_bulk_read(ds1307->regmap, 1644 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1645 if (err) { 1646 dev_dbg(ds1307->dev, "read error %d\n", err); 1647 goto exit; 1648 } 1649 1650 /* oscillator off? turn it on, so clock can tick. */ 1651 if (!(regs[1] & RX8025_BIT_XST)) { 1652 regs[1] |= RX8025_BIT_XST; 1653 regmap_write(ds1307->regmap, 1654 RX8025_REG_CTRL2 << 4 | 0x08, 1655 regs[1]); 1656 dev_warn(ds1307->dev, 1657 "oscillator stop detected - SET TIME!\n"); 1658 } 1659 1660 if (regs[1] & RX8025_BIT_PON) { 1661 regs[1] &= ~RX8025_BIT_PON; 1662 regmap_write(ds1307->regmap, 1663 RX8025_REG_CTRL2 << 4 | 0x08, 1664 regs[1]); 1665 dev_warn(ds1307->dev, "power-on detected\n"); 1666 } 1667 1668 if (regs[1] & RX8025_BIT_VDET) { 1669 regs[1] &= ~RX8025_BIT_VDET; 1670 regmap_write(ds1307->regmap, 1671 RX8025_REG_CTRL2 << 4 | 0x08, 1672 regs[1]); 1673 dev_warn(ds1307->dev, "voltage drop detected\n"); 1674 } 1675 1676 /* make sure we are running in 24hour mode */ 1677 if (!(regs[0] & RX8025_BIT_2412)) { 1678 u8 hour; 1679 1680 /* switch to 24 hour mode */ 1681 regmap_write(ds1307->regmap, 1682 RX8025_REG_CTRL1 << 4 | 0x08, 1683 regs[0] | RX8025_BIT_2412); 1684 1685 err = regmap_bulk_read(ds1307->regmap, 1686 RX8025_REG_CTRL1 << 4 | 0x08, 1687 regs, 2); 1688 if (err) { 1689 dev_dbg(ds1307->dev, "read error %d\n", err); 1690 goto exit; 1691 } 1692 1693 /* correct hour */ 1694 hour = bcd2bin(regs[DS1307_REG_HOUR]); 1695 if (hour == 12) 1696 hour = 0; 1697 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1698 hour += 12; 1699 1700 regmap_write(ds1307->regmap, 1701 DS1307_REG_HOUR << 4 | 0x08, hour); 1702 } 1703 break; 1704 default: 1705 break; 1706 } 1707 1708 read_rtc: 1709 /* read RTC registers */ 1710 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 1711 sizeof(regs)); 1712 if (err) { 1713 dev_dbg(ds1307->dev, "read error %d\n", err); 1714 goto exit; 1715 } 1716 1717 /* 1718 * minimal sanity checking; some chips (like DS1340) don't 1719 * specify the extra bits as must-be-zero, but there are 1720 * still a few values that are clearly out-of-range. 1721 */ 1722 tmp = regs[DS1307_REG_SECS]; 1723 switch (ds1307->type) { 1724 case ds_1307: 1725 case m41t0: 1726 case m41t00: 1727 case m41t11: 1728 /* clock halted? turn it on, so clock can tick. */ 1729 if (tmp & DS1307_BIT_CH) { 1730 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1731 dev_warn(ds1307->dev, "SET TIME!\n"); 1732 goto read_rtc; 1733 } 1734 break; 1735 case ds_1308: 1736 case ds_1338: 1737 /* clock halted? turn it on, so clock can tick. */ 1738 if (tmp & DS1307_BIT_CH) 1739 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1740 1741 /* oscillator fault? clear flag, and warn */ 1742 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { 1743 regmap_write(ds1307->regmap, DS1307_REG_CONTROL, 1744 regs[DS1307_REG_CONTROL] & 1745 ~DS1338_BIT_OSF); 1746 dev_warn(ds1307->dev, "SET TIME!\n"); 1747 goto read_rtc; 1748 } 1749 break; 1750 case ds_1340: 1751 /* clock halted? turn it on, so clock can tick. */ 1752 if (tmp & DS1340_BIT_nEOSC) 1753 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1754 1755 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 1756 if (err) { 1757 dev_dbg(ds1307->dev, "read error %d\n", err); 1758 goto exit; 1759 } 1760 1761 /* oscillator fault? clear flag, and warn */ 1762 if (tmp & DS1340_BIT_OSF) { 1763 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0); 1764 dev_warn(ds1307->dev, "SET TIME!\n"); 1765 } 1766 break; 1767 case mcp794xx: 1768 /* make sure that the backup battery is enabled */ 1769 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 1770 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 1771 regs[DS1307_REG_WDAY] | 1772 MCP794XX_BIT_VBATEN); 1773 } 1774 1775 /* clock halted? turn it on, so clock can tick. */ 1776 if (!(tmp & MCP794XX_BIT_ST)) { 1777 regmap_write(ds1307->regmap, DS1307_REG_SECS, 1778 MCP794XX_BIT_ST); 1779 dev_warn(ds1307->dev, "SET TIME!\n"); 1780 goto read_rtc; 1781 } 1782 1783 break; 1784 default: 1785 break; 1786 } 1787 1788 tmp = regs[DS1307_REG_HOUR]; 1789 switch (ds1307->type) { 1790 case ds_1340: 1791 case m41t0: 1792 case m41t00: 1793 case m41t11: 1794 /* 1795 * NOTE: ignores century bits; fix before deploying 1796 * systems that will run through year 2100. 1797 */ 1798 break; 1799 case rx_8025: 1800 break; 1801 default: 1802 if (!(tmp & DS1307_BIT_12HR)) 1803 break; 1804 1805 /* 1806 * Be sure we're in 24 hour mode. Multi-master systems 1807 * take note... 1808 */ 1809 tmp = bcd2bin(tmp & 0x1f); 1810 if (tmp == 12) 1811 tmp = 0; 1812 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1813 tmp += 12; 1814 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 1815 bin2bcd(tmp)); 1816 } 1817 1818 if (want_irq || ds1307_can_wakeup_device) { 1819 device_set_wakeup_capable(ds1307->dev, true); 1820 set_bit(HAS_ALARM, &ds1307->flags); 1821 } 1822 1823 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 1824 if (IS_ERR(ds1307->rtc)) 1825 return PTR_ERR(ds1307->rtc); 1826 1827 if (ds1307_can_wakeup_device && !want_irq) { 1828 dev_info(ds1307->dev, 1829 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 1830 /* We cannot support UIE mode if we do not have an IRQ line */ 1831 ds1307->rtc->uie_unsupported = 1; 1832 } 1833 1834 if (want_irq) { 1835 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 1836 chip->irq_handler ?: ds1307_irq, 1837 IRQF_SHARED | IRQF_ONESHOT, 1838 ds1307->name, ds1307); 1839 if (err) { 1840 client->irq = 0; 1841 device_set_wakeup_capable(ds1307->dev, false); 1842 clear_bit(HAS_ALARM, &ds1307->flags); 1843 dev_err(ds1307->dev, "unable to request IRQ!\n"); 1844 } else { 1845 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 1846 } 1847 } 1848 1849 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 1850 err = ds1307_add_frequency_test(ds1307); 1851 if (err) 1852 return err; 1853 1854 err = rtc_register_device(ds1307->rtc); 1855 if (err) 1856 return err; 1857 1858 if (chip->nvram_size) { 1859 struct nvmem_config nvmem_cfg = { 1860 .name = "ds1307_nvram", 1861 .word_size = 1, 1862 .stride = 1, 1863 .size = chip->nvram_size, 1864 .reg_read = ds1307_nvram_read, 1865 .reg_write = ds1307_nvram_write, 1866 .priv = ds1307, 1867 }; 1868 1869 ds1307->rtc->nvram_old_abi = true; 1870 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 1871 } 1872 1873 ds1307_hwmon_register(ds1307); 1874 ds1307_clks_register(ds1307); 1875 1876 return 0; 1877 1878 exit: 1879 return err; 1880 } 1881 1882 static struct i2c_driver ds1307_driver = { 1883 .driver = { 1884 .name = "rtc-ds1307", 1885 .of_match_table = of_match_ptr(ds1307_of_match), 1886 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids), 1887 }, 1888 .probe = ds1307_probe, 1889 .id_table = ds1307_id, 1890 }; 1891 1892 module_i2c_driver(ds1307_driver); 1893 1894 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 1895 MODULE_LICENSE("GPL"); 1896