1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 4 * 5 * Copyright (C) 2005 James Chapman (ds1337 core) 6 * Copyright (C) 2006 David Brownell 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bcd.h> 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/rtc/ds1307.h> 18 #include <linux/rtc.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* 28 * We can't determine type by probing, but if we expect pre-Linux code 29 * to have set the chip up as a clock (turning on the oscillator and 30 * setting the date and time), Linux can ignore the non-clock features. 31 * That's a natural job for a factory or repair bench. 32 */ 33 enum ds_type { 34 ds_1307, 35 ds_1308, 36 ds_1337, 37 ds_1338, 38 ds_1339, 39 ds_1340, 40 ds_1341, 41 ds_1388, 42 ds_3231, 43 m41t0, 44 m41t00, 45 m41t11, 46 mcp794xx, 47 rx_8025, 48 rx_8130, 49 last_ds_type /* always last */ 50 /* rs5c372 too? different address... */ 51 }; 52 53 /* RTC registers don't differ much, except for the century flag */ 54 #define DS1307_REG_SECS 0x00 /* 00-59 */ 55 # define DS1307_BIT_CH 0x80 56 # define DS1340_BIT_nEOSC 0x80 57 # define MCP794XX_BIT_ST 0x80 58 #define DS1307_REG_MIN 0x01 /* 00-59 */ 59 # define M41T0_BIT_OF 0x80 60 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 61 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 62 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 63 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 64 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 65 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 66 # define MCP794XX_BIT_VBATEN 0x08 67 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 68 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 69 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 70 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 71 72 /* 73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 74 * start at 7, and they differ a LOT. Only control and status matter for 75 * basic RTC date and time functionality; be careful using them. 76 */ 77 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 78 # define DS1307_BIT_OUT 0x80 79 # define DS1338_BIT_OSF 0x20 80 # define DS1307_BIT_SQWE 0x10 81 # define DS1307_BIT_RS1 0x02 82 # define DS1307_BIT_RS0 0x01 83 #define DS1337_REG_CONTROL 0x0e 84 # define DS1337_BIT_nEOSC 0x80 85 # define DS1339_BIT_BBSQI 0x20 86 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 87 # define DS1337_BIT_RS2 0x10 88 # define DS1337_BIT_RS1 0x08 89 # define DS1337_BIT_INTCN 0x04 90 # define DS1337_BIT_A2IE 0x02 91 # define DS1337_BIT_A1IE 0x01 92 #define DS1340_REG_CONTROL 0x07 93 # define DS1340_BIT_OUT 0x80 94 # define DS1340_BIT_FT 0x40 95 # define DS1340_BIT_CALIB_SIGN 0x20 96 # define DS1340_M_CALIBRATION 0x1f 97 #define DS1340_REG_FLAG 0x09 98 # define DS1340_BIT_OSF 0x80 99 #define DS1337_REG_STATUS 0x0f 100 # define DS1337_BIT_OSF 0x80 101 # define DS3231_BIT_EN32KHZ 0x08 102 # define DS1337_BIT_A2I 0x02 103 # define DS1337_BIT_A1I 0x01 104 #define DS1339_REG_ALARM1_SECS 0x07 105 106 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 107 108 #define RX8025_REG_CTRL1 0x0e 109 # define RX8025_BIT_2412 0x20 110 #define RX8025_REG_CTRL2 0x0f 111 # define RX8025_BIT_PON 0x10 112 # define RX8025_BIT_VDET 0x40 113 # define RX8025_BIT_XST 0x20 114 115 #define RX8130_REG_ALARM_MIN 0x17 116 #define RX8130_REG_ALARM_HOUR 0x18 117 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 118 #define RX8130_REG_EXTENSION 0x1c 119 #define RX8130_REG_EXTENSION_WADA BIT(3) 120 #define RX8130_REG_FLAG 0x1d 121 #define RX8130_REG_FLAG_VLF BIT(1) 122 #define RX8130_REG_FLAG_AF BIT(3) 123 #define RX8130_REG_CONTROL0 0x1e 124 #define RX8130_REG_CONTROL0_AIE BIT(3) 125 126 #define MCP794XX_REG_CONTROL 0x07 127 # define MCP794XX_BIT_ALM0_EN 0x10 128 # define MCP794XX_BIT_ALM1_EN 0x20 129 #define MCP794XX_REG_ALARM0_BASE 0x0a 130 #define MCP794XX_REG_ALARM0_CTRL 0x0d 131 #define MCP794XX_REG_ALARM1_BASE 0x11 132 #define MCP794XX_REG_ALARM1_CTRL 0x14 133 # define MCP794XX_BIT_ALMX_IF BIT(3) 134 # define MCP794XX_BIT_ALMX_C0 BIT(4) 135 # define MCP794XX_BIT_ALMX_C1 BIT(5) 136 # define MCP794XX_BIT_ALMX_C2 BIT(6) 137 # define MCP794XX_BIT_ALMX_POL BIT(7) 138 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 139 MCP794XX_BIT_ALMX_C1 | \ 140 MCP794XX_BIT_ALMX_C2) 141 142 #define M41TXX_REG_CONTROL 0x07 143 # define M41TXX_BIT_OUT BIT(7) 144 # define M41TXX_BIT_FT BIT(6) 145 # define M41TXX_BIT_CALIB_SIGN BIT(5) 146 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 147 148 #define DS1388_REG_WDOG_HUN_SECS 0x08 149 #define DS1388_REG_WDOG_SECS 0x09 150 #define DS1388_REG_FLAG 0x0b 151 # define DS1388_BIT_WF BIT(6) 152 # define DS1388_BIT_OSF BIT(7) 153 #define DS1388_REG_CONTROL 0x0c 154 # define DS1388_BIT_RST BIT(0) 155 # define DS1388_BIT_WDE BIT(1) 156 157 /* negative offset step is -2.034ppm */ 158 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 159 /* positive offset step is +4.068ppm */ 160 #define M41TXX_POS_OFFSET_STEP_PPB 4068 161 /* Min and max values supported with 'offset' interface by M41TXX */ 162 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 163 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 164 165 struct ds1307 { 166 enum ds_type type; 167 unsigned long flags; 168 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ 169 #define HAS_ALARM 1 /* bit 1 == irq claimed */ 170 struct device *dev; 171 struct regmap *regmap; 172 const char *name; 173 struct rtc_device *rtc; 174 #ifdef CONFIG_COMMON_CLK 175 struct clk_hw clks[2]; 176 #endif 177 }; 178 179 struct chip_desc { 180 unsigned alarm:1; 181 u16 nvram_offset; 182 u16 nvram_size; 183 u8 offset; /* register's offset */ 184 u8 century_reg; 185 u8 century_enable_bit; 186 u8 century_bit; 187 u8 bbsqi_bit; 188 irq_handler_t irq_handler; 189 const struct rtc_class_ops *rtc_ops; 190 u16 trickle_charger_reg; 191 u8 (*do_trickle_setup)(struct ds1307 *, u32, 192 bool); 193 }; 194 195 static const struct chip_desc chips[last_ds_type]; 196 197 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 198 { 199 struct ds1307 *ds1307 = dev_get_drvdata(dev); 200 int tmp, ret; 201 const struct chip_desc *chip = &chips[ds1307->type]; 202 u8 regs[7]; 203 204 if (ds1307->type == rx_8130) { 205 unsigned int regflag; 206 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 207 if (ret) { 208 dev_err(dev, "%s error %d\n", "read", ret); 209 return ret; 210 } 211 212 if (regflag & RX8130_REG_FLAG_VLF) { 213 dev_warn_once(dev, "oscillator failed, set time!\n"); 214 return -EINVAL; 215 } 216 } 217 218 /* read the RTC date and time registers all at once */ 219 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 220 sizeof(regs)); 221 if (ret) { 222 dev_err(dev, "%s error %d\n", "read", ret); 223 return ret; 224 } 225 226 dev_dbg(dev, "%s: %7ph\n", "read", regs); 227 228 /* if oscillator fail bit is set, no data can be trusted */ 229 if (ds1307->type == m41t0 && 230 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 231 dev_warn_once(dev, "oscillator failed, set time!\n"); 232 return -EINVAL; 233 } 234 235 tmp = regs[DS1307_REG_SECS]; 236 switch (ds1307->type) { 237 case ds_1307: 238 case m41t0: 239 case m41t00: 240 case m41t11: 241 if (tmp & DS1307_BIT_CH) 242 return -EINVAL; 243 break; 244 case ds_1308: 245 case ds_1338: 246 if (tmp & DS1307_BIT_CH) 247 return -EINVAL; 248 249 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp); 250 if (ret) 251 return ret; 252 if (tmp & DS1338_BIT_OSF) 253 return -EINVAL; 254 break; 255 case ds_1340: 256 if (tmp & DS1340_BIT_nEOSC) 257 return -EINVAL; 258 259 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 260 if (ret) 261 return ret; 262 if (tmp & DS1340_BIT_OSF) 263 return -EINVAL; 264 break; 265 case ds_1388: 266 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp); 267 if (ret) 268 return ret; 269 if (tmp & DS1388_BIT_OSF) 270 return -EINVAL; 271 break; 272 case mcp794xx: 273 if (!(tmp & MCP794XX_BIT_ST)) 274 return -EINVAL; 275 276 break; 277 default: 278 break; 279 } 280 281 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 282 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 283 tmp = regs[DS1307_REG_HOUR] & 0x3f; 284 t->tm_hour = bcd2bin(tmp); 285 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 286 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 287 tmp = regs[DS1307_REG_MONTH] & 0x1f; 288 t->tm_mon = bcd2bin(tmp) - 1; 289 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 290 291 if (regs[chip->century_reg] & chip->century_bit && 292 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 293 t->tm_year += 100; 294 295 dev_dbg(dev, "%s secs=%d, mins=%d, " 296 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 297 "read", t->tm_sec, t->tm_min, 298 t->tm_hour, t->tm_mday, 299 t->tm_mon, t->tm_year, t->tm_wday); 300 301 return 0; 302 } 303 304 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 305 { 306 struct ds1307 *ds1307 = dev_get_drvdata(dev); 307 const struct chip_desc *chip = &chips[ds1307->type]; 308 int result; 309 int tmp; 310 u8 regs[7]; 311 312 dev_dbg(dev, "%s secs=%d, mins=%d, " 313 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 314 "write", t->tm_sec, t->tm_min, 315 t->tm_hour, t->tm_mday, 316 t->tm_mon, t->tm_year, t->tm_wday); 317 318 if (t->tm_year < 100) 319 return -EINVAL; 320 321 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 322 if (t->tm_year > (chip->century_bit ? 299 : 199)) 323 return -EINVAL; 324 #else 325 if (t->tm_year > 199) 326 return -EINVAL; 327 #endif 328 329 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 330 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 331 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 332 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 333 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 334 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 335 336 /* assume 20YY not 19YY */ 337 tmp = t->tm_year - 100; 338 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 339 340 if (chip->century_enable_bit) 341 regs[chip->century_reg] |= chip->century_enable_bit; 342 if (t->tm_year > 199 && chip->century_bit) 343 regs[chip->century_reg] |= chip->century_bit; 344 345 switch (ds1307->type) { 346 case ds_1308: 347 case ds_1338: 348 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 349 DS1338_BIT_OSF, 0); 350 break; 351 case ds_1340: 352 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG, 353 DS1340_BIT_OSF, 0); 354 break; 355 case mcp794xx: 356 /* 357 * these bits were cleared when preparing the date/time 358 * values and need to be set again before writing the 359 * regsfer out to the device. 360 */ 361 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 362 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 363 break; 364 default: 365 break; 366 } 367 368 dev_dbg(dev, "%s: %7ph\n", "write", regs); 369 370 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 371 sizeof(regs)); 372 if (result) { 373 dev_err(dev, "%s error %d\n", "write", result); 374 return result; 375 } 376 377 if (ds1307->type == rx_8130) { 378 /* clear Voltage Loss Flag as data is available now */ 379 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 380 ~(u8)RX8130_REG_FLAG_VLF); 381 if (result) { 382 dev_err(dev, "%s error %d\n", "write", result); 383 return result; 384 } 385 } 386 387 return 0; 388 } 389 390 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 391 { 392 struct ds1307 *ds1307 = dev_get_drvdata(dev); 393 int ret; 394 u8 regs[9]; 395 396 if (!test_bit(HAS_ALARM, &ds1307->flags)) 397 return -EINVAL; 398 399 /* read all ALARM1, ALARM2, and status registers at once */ 400 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 401 regs, sizeof(regs)); 402 if (ret) { 403 dev_err(dev, "%s error %d\n", "alarm read", ret); 404 return ret; 405 } 406 407 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 408 ®s[0], ®s[4], ®s[7]); 409 410 /* 411 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 412 * and that all four fields are checked matches 413 */ 414 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 415 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 416 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 417 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 418 419 /* ... and status */ 420 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 421 t->pending = !!(regs[8] & DS1337_BIT_A1I); 422 423 dev_dbg(dev, "%s secs=%d, mins=%d, " 424 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 425 "alarm read", t->time.tm_sec, t->time.tm_min, 426 t->time.tm_hour, t->time.tm_mday, 427 t->enabled, t->pending); 428 429 return 0; 430 } 431 432 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 433 { 434 struct ds1307 *ds1307 = dev_get_drvdata(dev); 435 unsigned char regs[9]; 436 u8 control, status; 437 int ret; 438 439 if (!test_bit(HAS_ALARM, &ds1307->flags)) 440 return -EINVAL; 441 442 dev_dbg(dev, "%s secs=%d, mins=%d, " 443 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 444 "alarm set", t->time.tm_sec, t->time.tm_min, 445 t->time.tm_hour, t->time.tm_mday, 446 t->enabled, t->pending); 447 448 /* read current status of both alarms and the chip */ 449 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 450 sizeof(regs)); 451 if (ret) { 452 dev_err(dev, "%s error %d\n", "alarm write", ret); 453 return ret; 454 } 455 control = regs[7]; 456 status = regs[8]; 457 458 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 459 ®s[0], ®s[4], control, status); 460 461 /* set ALARM1, using 24 hour and day-of-month modes */ 462 regs[0] = bin2bcd(t->time.tm_sec); 463 regs[1] = bin2bcd(t->time.tm_min); 464 regs[2] = bin2bcd(t->time.tm_hour); 465 regs[3] = bin2bcd(t->time.tm_mday); 466 467 /* set ALARM2 to non-garbage */ 468 regs[4] = 0; 469 regs[5] = 0; 470 regs[6] = 0; 471 472 /* disable alarms */ 473 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 474 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 475 476 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 477 sizeof(regs)); 478 if (ret) { 479 dev_err(dev, "can't set alarm time\n"); 480 return ret; 481 } 482 483 /* optionally enable ALARM1 */ 484 if (t->enabled) { 485 dev_dbg(dev, "alarm IRQ armed\n"); 486 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 487 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 488 } 489 490 return 0; 491 } 492 493 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 494 { 495 struct ds1307 *ds1307 = dev_get_drvdata(dev); 496 497 if (!test_bit(HAS_ALARM, &ds1307->flags)) 498 return -ENOTTY; 499 500 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 501 DS1337_BIT_A1IE, 502 enabled ? DS1337_BIT_A1IE : 0); 503 } 504 505 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 506 { 507 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 508 DS1307_TRICKLE_CHARGER_NO_DIODE; 509 510 switch (ohms) { 511 case 250: 512 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 513 break; 514 case 2000: 515 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 516 break; 517 case 4000: 518 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 519 break; 520 default: 521 dev_warn(ds1307->dev, 522 "Unsupported ohm value %u in dt\n", ohms); 523 return 0; 524 } 525 return setup; 526 } 527 528 static irqreturn_t rx8130_irq(int irq, void *dev_id) 529 { 530 struct ds1307 *ds1307 = dev_id; 531 struct mutex *lock = &ds1307->rtc->ops_lock; 532 u8 ctl[3]; 533 int ret; 534 535 mutex_lock(lock); 536 537 /* Read control registers. */ 538 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 539 sizeof(ctl)); 540 if (ret < 0) 541 goto out; 542 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 543 goto out; 544 ctl[1] &= ~RX8130_REG_FLAG_AF; 545 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 546 547 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 548 sizeof(ctl)); 549 if (ret < 0) 550 goto out; 551 552 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 553 554 out: 555 mutex_unlock(lock); 556 557 return IRQ_HANDLED; 558 } 559 560 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 561 { 562 struct ds1307 *ds1307 = dev_get_drvdata(dev); 563 u8 ald[3], ctl[3]; 564 int ret; 565 566 if (!test_bit(HAS_ALARM, &ds1307->flags)) 567 return -EINVAL; 568 569 /* Read alarm registers. */ 570 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 571 sizeof(ald)); 572 if (ret < 0) 573 return ret; 574 575 /* Read control registers. */ 576 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 577 sizeof(ctl)); 578 if (ret < 0) 579 return ret; 580 581 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 582 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 583 584 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 585 t->time.tm_sec = -1; 586 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 587 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 588 t->time.tm_wday = -1; 589 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 590 t->time.tm_mon = -1; 591 t->time.tm_year = -1; 592 t->time.tm_yday = -1; 593 t->time.tm_isdst = -1; 594 595 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 596 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 597 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 598 599 return 0; 600 } 601 602 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 603 { 604 struct ds1307 *ds1307 = dev_get_drvdata(dev); 605 u8 ald[3], ctl[3]; 606 int ret; 607 608 if (!test_bit(HAS_ALARM, &ds1307->flags)) 609 return -EINVAL; 610 611 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 612 "enabled=%d pending=%d\n", __func__, 613 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 614 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 615 t->enabled, t->pending); 616 617 /* Read control registers. */ 618 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 619 sizeof(ctl)); 620 if (ret < 0) 621 return ret; 622 623 ctl[0] &= RX8130_REG_EXTENSION_WADA; 624 ctl[1] &= ~RX8130_REG_FLAG_AF; 625 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 626 627 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 628 sizeof(ctl)); 629 if (ret < 0) 630 return ret; 631 632 /* Hardware alarm precision is 1 minute! */ 633 ald[0] = bin2bcd(t->time.tm_min); 634 ald[1] = bin2bcd(t->time.tm_hour); 635 ald[2] = bin2bcd(t->time.tm_mday); 636 637 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 638 sizeof(ald)); 639 if (ret < 0) 640 return ret; 641 642 if (!t->enabled) 643 return 0; 644 645 ctl[2] |= RX8130_REG_CONTROL0_AIE; 646 647 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 648 } 649 650 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 651 { 652 struct ds1307 *ds1307 = dev_get_drvdata(dev); 653 int ret, reg; 654 655 if (!test_bit(HAS_ALARM, &ds1307->flags)) 656 return -EINVAL; 657 658 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 659 if (ret < 0) 660 return ret; 661 662 if (enabled) 663 reg |= RX8130_REG_CONTROL0_AIE; 664 else 665 reg &= ~RX8130_REG_CONTROL0_AIE; 666 667 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 668 } 669 670 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 671 { 672 struct ds1307 *ds1307 = dev_id; 673 struct mutex *lock = &ds1307->rtc->ops_lock; 674 int reg, ret; 675 676 mutex_lock(lock); 677 678 /* Check and clear alarm 0 interrupt flag. */ 679 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 680 if (ret) 681 goto out; 682 if (!(reg & MCP794XX_BIT_ALMX_IF)) 683 goto out; 684 reg &= ~MCP794XX_BIT_ALMX_IF; 685 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 686 if (ret) 687 goto out; 688 689 /* Disable alarm 0. */ 690 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 691 MCP794XX_BIT_ALM0_EN, 0); 692 if (ret) 693 goto out; 694 695 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 696 697 out: 698 mutex_unlock(lock); 699 700 return IRQ_HANDLED; 701 } 702 703 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 704 { 705 struct ds1307 *ds1307 = dev_get_drvdata(dev); 706 u8 regs[10]; 707 int ret; 708 709 if (!test_bit(HAS_ALARM, &ds1307->flags)) 710 return -EINVAL; 711 712 /* Read control and alarm 0 registers. */ 713 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 714 sizeof(regs)); 715 if (ret) 716 return ret; 717 718 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 719 720 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 721 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 722 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 723 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 724 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 725 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 726 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 727 t->time.tm_year = -1; 728 t->time.tm_yday = -1; 729 t->time.tm_isdst = -1; 730 731 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 732 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 733 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 734 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 735 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 736 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 737 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 738 739 return 0; 740 } 741 742 /* 743 * We may have a random RTC weekday, therefore calculate alarm weekday based 744 * on current weekday we read from the RTC timekeeping regs 745 */ 746 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 747 { 748 struct rtc_time tm_now; 749 int days_now, days_alarm, ret; 750 751 ret = ds1307_get_time(dev, &tm_now); 752 if (ret) 753 return ret; 754 755 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 756 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 757 758 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 759 } 760 761 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 762 { 763 struct ds1307 *ds1307 = dev_get_drvdata(dev); 764 unsigned char regs[10]; 765 int wday, ret; 766 767 if (!test_bit(HAS_ALARM, &ds1307->flags)) 768 return -EINVAL; 769 770 wday = mcp794xx_alm_weekday(dev, &t->time); 771 if (wday < 0) 772 return wday; 773 774 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 775 "enabled=%d pending=%d\n", __func__, 776 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 777 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 778 t->enabled, t->pending); 779 780 /* Read control and alarm 0 registers. */ 781 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 782 sizeof(regs)); 783 if (ret) 784 return ret; 785 786 /* Set alarm 0, using 24-hour and day-of-month modes. */ 787 regs[3] = bin2bcd(t->time.tm_sec); 788 regs[4] = bin2bcd(t->time.tm_min); 789 regs[5] = bin2bcd(t->time.tm_hour); 790 regs[6] = wday; 791 regs[7] = bin2bcd(t->time.tm_mday); 792 regs[8] = bin2bcd(t->time.tm_mon + 1); 793 794 /* Clear the alarm 0 interrupt flag. */ 795 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 796 /* Set alarm match: second, minute, hour, day, date, month. */ 797 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 798 /* Disable interrupt. We will not enable until completely programmed */ 799 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 800 801 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 802 sizeof(regs)); 803 if (ret) 804 return ret; 805 806 if (!t->enabled) 807 return 0; 808 regs[0] |= MCP794XX_BIT_ALM0_EN; 809 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 810 } 811 812 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 813 { 814 struct ds1307 *ds1307 = dev_get_drvdata(dev); 815 816 if (!test_bit(HAS_ALARM, &ds1307->flags)) 817 return -EINVAL; 818 819 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 820 MCP794XX_BIT_ALM0_EN, 821 enabled ? MCP794XX_BIT_ALM0_EN : 0); 822 } 823 824 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 825 { 826 struct ds1307 *ds1307 = dev_get_drvdata(dev); 827 unsigned int ctrl_reg; 828 u8 val; 829 830 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 831 832 val = ctrl_reg & M41TXX_M_CALIBRATION; 833 834 /* check if positive */ 835 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 836 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 837 else 838 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 839 840 return 0; 841 } 842 843 static int m41txx_rtc_set_offset(struct device *dev, long offset) 844 { 845 struct ds1307 *ds1307 = dev_get_drvdata(dev); 846 unsigned int ctrl_reg; 847 848 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 849 return -ERANGE; 850 851 if (offset >= 0) { 852 ctrl_reg = DIV_ROUND_CLOSEST(offset, 853 M41TXX_POS_OFFSET_STEP_PPB); 854 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 855 } else { 856 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 857 M41TXX_NEG_OFFSET_STEP_PPB); 858 } 859 860 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 861 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 862 ctrl_reg); 863 } 864 865 #ifdef CONFIG_WATCHDOG_CORE 866 static int ds1388_wdt_start(struct watchdog_device *wdt_dev) 867 { 868 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 869 u8 regs[2]; 870 int ret; 871 872 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 873 DS1388_BIT_WF, 0); 874 if (ret) 875 return ret; 876 877 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 878 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 879 if (ret) 880 return ret; 881 882 /* 883 * watchdog timeouts are measured in seconds. So ignore hundredths of 884 * seconds field. 885 */ 886 regs[0] = 0; 887 regs[1] = bin2bcd(wdt_dev->timeout); 888 889 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 890 sizeof(regs)); 891 if (ret) 892 return ret; 893 894 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 895 DS1388_BIT_WDE | DS1388_BIT_RST, 896 DS1388_BIT_WDE | DS1388_BIT_RST); 897 } 898 899 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) 900 { 901 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 902 903 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 904 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 905 } 906 907 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) 908 { 909 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 910 u8 regs[2]; 911 912 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 913 sizeof(regs)); 914 } 915 916 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev, 917 unsigned int val) 918 { 919 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 920 u8 regs[2]; 921 922 wdt_dev->timeout = val; 923 regs[0] = 0; 924 regs[1] = bin2bcd(wdt_dev->timeout); 925 926 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 927 sizeof(regs)); 928 } 929 #endif 930 931 static const struct rtc_class_ops rx8130_rtc_ops = { 932 .read_time = ds1307_get_time, 933 .set_time = ds1307_set_time, 934 .read_alarm = rx8130_read_alarm, 935 .set_alarm = rx8130_set_alarm, 936 .alarm_irq_enable = rx8130_alarm_irq_enable, 937 }; 938 939 static const struct rtc_class_ops mcp794xx_rtc_ops = { 940 .read_time = ds1307_get_time, 941 .set_time = ds1307_set_time, 942 .read_alarm = mcp794xx_read_alarm, 943 .set_alarm = mcp794xx_set_alarm, 944 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 945 }; 946 947 static const struct rtc_class_ops m41txx_rtc_ops = { 948 .read_time = ds1307_get_time, 949 .set_time = ds1307_set_time, 950 .read_alarm = ds1337_read_alarm, 951 .set_alarm = ds1337_set_alarm, 952 .alarm_irq_enable = ds1307_alarm_irq_enable, 953 .read_offset = m41txx_rtc_read_offset, 954 .set_offset = m41txx_rtc_set_offset, 955 }; 956 957 static const struct chip_desc chips[last_ds_type] = { 958 [ds_1307] = { 959 .nvram_offset = 8, 960 .nvram_size = 56, 961 }, 962 [ds_1308] = { 963 .nvram_offset = 8, 964 .nvram_size = 56, 965 }, 966 [ds_1337] = { 967 .alarm = 1, 968 .century_reg = DS1307_REG_MONTH, 969 .century_bit = DS1337_BIT_CENTURY, 970 }, 971 [ds_1338] = { 972 .nvram_offset = 8, 973 .nvram_size = 56, 974 }, 975 [ds_1339] = { 976 .alarm = 1, 977 .century_reg = DS1307_REG_MONTH, 978 .century_bit = DS1337_BIT_CENTURY, 979 .bbsqi_bit = DS1339_BIT_BBSQI, 980 .trickle_charger_reg = 0x10, 981 .do_trickle_setup = &do_trickle_setup_ds1339, 982 }, 983 [ds_1340] = { 984 .century_reg = DS1307_REG_HOUR, 985 .century_enable_bit = DS1340_BIT_CENTURY_EN, 986 .century_bit = DS1340_BIT_CENTURY, 987 .do_trickle_setup = &do_trickle_setup_ds1339, 988 .trickle_charger_reg = 0x08, 989 }, 990 [ds_1341] = { 991 .century_reg = DS1307_REG_MONTH, 992 .century_bit = DS1337_BIT_CENTURY, 993 }, 994 [ds_1388] = { 995 .offset = 1, 996 .trickle_charger_reg = 0x0a, 997 }, 998 [ds_3231] = { 999 .alarm = 1, 1000 .century_reg = DS1307_REG_MONTH, 1001 .century_bit = DS1337_BIT_CENTURY, 1002 .bbsqi_bit = DS3231_BIT_BBSQW, 1003 }, 1004 [rx_8130] = { 1005 .alarm = 1, 1006 /* this is battery backed SRAM */ 1007 .nvram_offset = 0x20, 1008 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 1009 .offset = 0x10, 1010 .irq_handler = rx8130_irq, 1011 .rtc_ops = &rx8130_rtc_ops, 1012 }, 1013 [m41t0] = { 1014 .rtc_ops = &m41txx_rtc_ops, 1015 }, 1016 [m41t00] = { 1017 .rtc_ops = &m41txx_rtc_ops, 1018 }, 1019 [m41t11] = { 1020 /* this is battery backed SRAM */ 1021 .nvram_offset = 8, 1022 .nvram_size = 56, 1023 .rtc_ops = &m41txx_rtc_ops, 1024 }, 1025 [mcp794xx] = { 1026 .alarm = 1, 1027 /* this is battery backed SRAM */ 1028 .nvram_offset = 0x20, 1029 .nvram_size = 0x40, 1030 .irq_handler = mcp794xx_irq, 1031 .rtc_ops = &mcp794xx_rtc_ops, 1032 }, 1033 }; 1034 1035 static const struct i2c_device_id ds1307_id[] = { 1036 { "ds1307", ds_1307 }, 1037 { "ds1308", ds_1308 }, 1038 { "ds1337", ds_1337 }, 1039 { "ds1338", ds_1338 }, 1040 { "ds1339", ds_1339 }, 1041 { "ds1388", ds_1388 }, 1042 { "ds1340", ds_1340 }, 1043 { "ds1341", ds_1341 }, 1044 { "ds3231", ds_3231 }, 1045 { "m41t0", m41t0 }, 1046 { "m41t00", m41t00 }, 1047 { "m41t11", m41t11 }, 1048 { "mcp7940x", mcp794xx }, 1049 { "mcp7941x", mcp794xx }, 1050 { "pt7c4338", ds_1307 }, 1051 { "rx8025", rx_8025 }, 1052 { "isl12057", ds_1337 }, 1053 { "rx8130", rx_8130 }, 1054 { } 1055 }; 1056 MODULE_DEVICE_TABLE(i2c, ds1307_id); 1057 1058 #ifdef CONFIG_OF 1059 static const struct of_device_id ds1307_of_match[] = { 1060 { 1061 .compatible = "dallas,ds1307", 1062 .data = (void *)ds_1307 1063 }, 1064 { 1065 .compatible = "dallas,ds1308", 1066 .data = (void *)ds_1308 1067 }, 1068 { 1069 .compatible = "dallas,ds1337", 1070 .data = (void *)ds_1337 1071 }, 1072 { 1073 .compatible = "dallas,ds1338", 1074 .data = (void *)ds_1338 1075 }, 1076 { 1077 .compatible = "dallas,ds1339", 1078 .data = (void *)ds_1339 1079 }, 1080 { 1081 .compatible = "dallas,ds1388", 1082 .data = (void *)ds_1388 1083 }, 1084 { 1085 .compatible = "dallas,ds1340", 1086 .data = (void *)ds_1340 1087 }, 1088 { 1089 .compatible = "dallas,ds1341", 1090 .data = (void *)ds_1341 1091 }, 1092 { 1093 .compatible = "maxim,ds3231", 1094 .data = (void *)ds_3231 1095 }, 1096 { 1097 .compatible = "st,m41t0", 1098 .data = (void *)m41t0 1099 }, 1100 { 1101 .compatible = "st,m41t00", 1102 .data = (void *)m41t00 1103 }, 1104 { 1105 .compatible = "st,m41t11", 1106 .data = (void *)m41t11 1107 }, 1108 { 1109 .compatible = "microchip,mcp7940x", 1110 .data = (void *)mcp794xx 1111 }, 1112 { 1113 .compatible = "microchip,mcp7941x", 1114 .data = (void *)mcp794xx 1115 }, 1116 { 1117 .compatible = "pericom,pt7c4338", 1118 .data = (void *)ds_1307 1119 }, 1120 { 1121 .compatible = "epson,rx8025", 1122 .data = (void *)rx_8025 1123 }, 1124 { 1125 .compatible = "isil,isl12057", 1126 .data = (void *)ds_1337 1127 }, 1128 { 1129 .compatible = "epson,rx8130", 1130 .data = (void *)rx_8130 1131 }, 1132 { } 1133 }; 1134 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1135 #endif 1136 1137 #ifdef CONFIG_ACPI 1138 static const struct acpi_device_id ds1307_acpi_ids[] = { 1139 { .id = "DS1307", .driver_data = ds_1307 }, 1140 { .id = "DS1308", .driver_data = ds_1308 }, 1141 { .id = "DS1337", .driver_data = ds_1337 }, 1142 { .id = "DS1338", .driver_data = ds_1338 }, 1143 { .id = "DS1339", .driver_data = ds_1339 }, 1144 { .id = "DS1388", .driver_data = ds_1388 }, 1145 { .id = "DS1340", .driver_data = ds_1340 }, 1146 { .id = "DS1341", .driver_data = ds_1341 }, 1147 { .id = "DS3231", .driver_data = ds_3231 }, 1148 { .id = "M41T0", .driver_data = m41t0 }, 1149 { .id = "M41T00", .driver_data = m41t00 }, 1150 { .id = "M41T11", .driver_data = m41t11 }, 1151 { .id = "MCP7940X", .driver_data = mcp794xx }, 1152 { .id = "MCP7941X", .driver_data = mcp794xx }, 1153 { .id = "PT7C4338", .driver_data = ds_1307 }, 1154 { .id = "RX8025", .driver_data = rx_8025 }, 1155 { .id = "ISL12057", .driver_data = ds_1337 }, 1156 { .id = "RX8130", .driver_data = rx_8130 }, 1157 { } 1158 }; 1159 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); 1160 #endif 1161 1162 /* 1163 * The ds1337 and ds1339 both have two alarms, but we only use the first 1164 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1165 * signal; ds1339 chips have only one alarm signal. 1166 */ 1167 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1168 { 1169 struct ds1307 *ds1307 = dev_id; 1170 struct mutex *lock = &ds1307->rtc->ops_lock; 1171 int stat, ret; 1172 1173 mutex_lock(lock); 1174 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1175 if (ret) 1176 goto out; 1177 1178 if (stat & DS1337_BIT_A1I) { 1179 stat &= ~DS1337_BIT_A1I; 1180 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1181 1182 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1183 DS1337_BIT_A1IE, 0); 1184 if (ret) 1185 goto out; 1186 1187 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1188 } 1189 1190 out: 1191 mutex_unlock(lock); 1192 1193 return IRQ_HANDLED; 1194 } 1195 1196 /*----------------------------------------------------------------------*/ 1197 1198 static const struct rtc_class_ops ds13xx_rtc_ops = { 1199 .read_time = ds1307_get_time, 1200 .set_time = ds1307_set_time, 1201 .read_alarm = ds1337_read_alarm, 1202 .set_alarm = ds1337_set_alarm, 1203 .alarm_irq_enable = ds1307_alarm_irq_enable, 1204 }; 1205 1206 static ssize_t frequency_test_store(struct device *dev, 1207 struct device_attribute *attr, 1208 const char *buf, size_t count) 1209 { 1210 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1211 bool freq_test_en; 1212 int ret; 1213 1214 ret = kstrtobool(buf, &freq_test_en); 1215 if (ret) { 1216 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1217 return ret; 1218 } 1219 1220 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1221 freq_test_en ? M41TXX_BIT_FT : 0); 1222 1223 return count; 1224 } 1225 1226 static ssize_t frequency_test_show(struct device *dev, 1227 struct device_attribute *attr, 1228 char *buf) 1229 { 1230 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1231 unsigned int ctrl_reg; 1232 1233 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1234 1235 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : 1236 "off\n"); 1237 } 1238 1239 static DEVICE_ATTR_RW(frequency_test); 1240 1241 static struct attribute *rtc_freq_test_attrs[] = { 1242 &dev_attr_frequency_test.attr, 1243 NULL, 1244 }; 1245 1246 static const struct attribute_group rtc_freq_test_attr_group = { 1247 .attrs = rtc_freq_test_attrs, 1248 }; 1249 1250 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1251 { 1252 int err; 1253 1254 switch (ds1307->type) { 1255 case m41t0: 1256 case m41t00: 1257 case m41t11: 1258 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1259 if (err) 1260 return err; 1261 break; 1262 default: 1263 break; 1264 } 1265 1266 return 0; 1267 } 1268 1269 /*----------------------------------------------------------------------*/ 1270 1271 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1272 size_t bytes) 1273 { 1274 struct ds1307 *ds1307 = priv; 1275 const struct chip_desc *chip = &chips[ds1307->type]; 1276 1277 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1278 val, bytes); 1279 } 1280 1281 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1282 size_t bytes) 1283 { 1284 struct ds1307 *ds1307 = priv; 1285 const struct chip_desc *chip = &chips[ds1307->type]; 1286 1287 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1288 val, bytes); 1289 } 1290 1291 /*----------------------------------------------------------------------*/ 1292 1293 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1294 const struct chip_desc *chip) 1295 { 1296 u32 ohms; 1297 bool diode = true; 1298 1299 if (!chip->do_trickle_setup) 1300 return 0; 1301 1302 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1303 &ohms)) 1304 return 0; 1305 1306 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable")) 1307 diode = false; 1308 1309 return chip->do_trickle_setup(ds1307, ohms, diode); 1310 } 1311 1312 /*----------------------------------------------------------------------*/ 1313 1314 #if IS_REACHABLE(CONFIG_HWMON) 1315 1316 /* 1317 * Temperature sensor support for ds3231 devices. 1318 */ 1319 1320 #define DS3231_REG_TEMPERATURE 0x11 1321 1322 /* 1323 * A user-initiated temperature conversion is not started by this function, 1324 * so the temperature is updated once every 64 seconds. 1325 */ 1326 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1327 { 1328 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1329 u8 temp_buf[2]; 1330 s16 temp; 1331 int ret; 1332 1333 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1334 temp_buf, sizeof(temp_buf)); 1335 if (ret) 1336 return ret; 1337 /* 1338 * Temperature is represented as a 10-bit code with a resolution of 1339 * 0.25 degree celsius and encoded in two's complement format. 1340 */ 1341 temp = (temp_buf[0] << 8) | temp_buf[1]; 1342 temp >>= 6; 1343 *mC = temp * 250; 1344 1345 return 0; 1346 } 1347 1348 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1349 struct device_attribute *attr, char *buf) 1350 { 1351 int ret; 1352 s32 temp; 1353 1354 ret = ds3231_hwmon_read_temp(dev, &temp); 1355 if (ret) 1356 return ret; 1357 1358 return sprintf(buf, "%d\n", temp); 1359 } 1360 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1361 NULL, 0); 1362 1363 static struct attribute *ds3231_hwmon_attrs[] = { 1364 &sensor_dev_attr_temp1_input.dev_attr.attr, 1365 NULL, 1366 }; 1367 ATTRIBUTE_GROUPS(ds3231_hwmon); 1368 1369 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1370 { 1371 struct device *dev; 1372 1373 if (ds1307->type != ds_3231) 1374 return; 1375 1376 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1377 ds1307, 1378 ds3231_hwmon_groups); 1379 if (IS_ERR(dev)) { 1380 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1381 PTR_ERR(dev)); 1382 } 1383 } 1384 1385 #else 1386 1387 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1388 { 1389 } 1390 1391 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ 1392 1393 /*----------------------------------------------------------------------*/ 1394 1395 /* 1396 * Square-wave output support for DS3231 1397 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1398 */ 1399 #ifdef CONFIG_COMMON_CLK 1400 1401 enum { 1402 DS3231_CLK_SQW = 0, 1403 DS3231_CLK_32KHZ, 1404 }; 1405 1406 #define clk_sqw_to_ds1307(clk) \ 1407 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1408 #define clk_32khz_to_ds1307(clk) \ 1409 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1410 1411 static int ds3231_clk_sqw_rates[] = { 1412 1, 1413 1024, 1414 4096, 1415 8192, 1416 }; 1417 1418 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1419 { 1420 struct mutex *lock = &ds1307->rtc->ops_lock; 1421 int ret; 1422 1423 mutex_lock(lock); 1424 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1425 mask, value); 1426 mutex_unlock(lock); 1427 1428 return ret; 1429 } 1430 1431 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1432 unsigned long parent_rate) 1433 { 1434 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1435 int control, ret; 1436 int rate_sel = 0; 1437 1438 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1439 if (ret) 1440 return ret; 1441 if (control & DS1337_BIT_RS1) 1442 rate_sel += 1; 1443 if (control & DS1337_BIT_RS2) 1444 rate_sel += 2; 1445 1446 return ds3231_clk_sqw_rates[rate_sel]; 1447 } 1448 1449 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, 1450 unsigned long *prate) 1451 { 1452 int i; 1453 1454 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1455 if (ds3231_clk_sqw_rates[i] <= rate) 1456 return ds3231_clk_sqw_rates[i]; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1463 unsigned long parent_rate) 1464 { 1465 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1466 int control = 0; 1467 int rate_sel; 1468 1469 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1470 rate_sel++) { 1471 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1472 break; 1473 } 1474 1475 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1476 return -EINVAL; 1477 1478 if (rate_sel & 1) 1479 control |= DS1337_BIT_RS1; 1480 if (rate_sel & 2) 1481 control |= DS1337_BIT_RS2; 1482 1483 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1484 control); 1485 } 1486 1487 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1488 { 1489 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1490 1491 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1492 } 1493 1494 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1495 { 1496 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1497 1498 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1499 } 1500 1501 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1502 { 1503 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1504 int control, ret; 1505 1506 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1507 if (ret) 1508 return ret; 1509 1510 return !(control & DS1337_BIT_INTCN); 1511 } 1512 1513 static const struct clk_ops ds3231_clk_sqw_ops = { 1514 .prepare = ds3231_clk_sqw_prepare, 1515 .unprepare = ds3231_clk_sqw_unprepare, 1516 .is_prepared = ds3231_clk_sqw_is_prepared, 1517 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1518 .round_rate = ds3231_clk_sqw_round_rate, 1519 .set_rate = ds3231_clk_sqw_set_rate, 1520 }; 1521 1522 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1523 unsigned long parent_rate) 1524 { 1525 return 32768; 1526 } 1527 1528 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1529 { 1530 struct mutex *lock = &ds1307->rtc->ops_lock; 1531 int ret; 1532 1533 mutex_lock(lock); 1534 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1535 DS3231_BIT_EN32KHZ, 1536 enable ? DS3231_BIT_EN32KHZ : 0); 1537 mutex_unlock(lock); 1538 1539 return ret; 1540 } 1541 1542 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1543 { 1544 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1545 1546 return ds3231_clk_32khz_control(ds1307, true); 1547 } 1548 1549 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1550 { 1551 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1552 1553 ds3231_clk_32khz_control(ds1307, false); 1554 } 1555 1556 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1557 { 1558 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1559 int status, ret; 1560 1561 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1562 if (ret) 1563 return ret; 1564 1565 return !!(status & DS3231_BIT_EN32KHZ); 1566 } 1567 1568 static const struct clk_ops ds3231_clk_32khz_ops = { 1569 .prepare = ds3231_clk_32khz_prepare, 1570 .unprepare = ds3231_clk_32khz_unprepare, 1571 .is_prepared = ds3231_clk_32khz_is_prepared, 1572 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1573 }; 1574 1575 static struct clk_init_data ds3231_clks_init[] = { 1576 [DS3231_CLK_SQW] = { 1577 .name = "ds3231_clk_sqw", 1578 .ops = &ds3231_clk_sqw_ops, 1579 }, 1580 [DS3231_CLK_32KHZ] = { 1581 .name = "ds3231_clk_32khz", 1582 .ops = &ds3231_clk_32khz_ops, 1583 }, 1584 }; 1585 1586 static int ds3231_clks_register(struct ds1307 *ds1307) 1587 { 1588 struct device_node *node = ds1307->dev->of_node; 1589 struct clk_onecell_data *onecell; 1590 int i; 1591 1592 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1593 if (!onecell) 1594 return -ENOMEM; 1595 1596 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1597 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1598 sizeof(onecell->clks[0]), GFP_KERNEL); 1599 if (!onecell->clks) 1600 return -ENOMEM; 1601 1602 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1603 struct clk_init_data init = ds3231_clks_init[i]; 1604 1605 /* 1606 * Interrupt signal due to alarm conditions and square-wave 1607 * output share same pin, so don't initialize both. 1608 */ 1609 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags)) 1610 continue; 1611 1612 /* optional override of the clockname */ 1613 of_property_read_string_index(node, "clock-output-names", i, 1614 &init.name); 1615 ds1307->clks[i].init = &init; 1616 1617 onecell->clks[i] = devm_clk_register(ds1307->dev, 1618 &ds1307->clks[i]); 1619 if (IS_ERR(onecell->clks[i])) 1620 return PTR_ERR(onecell->clks[i]); 1621 } 1622 1623 if (!node) 1624 return 0; 1625 1626 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1627 1628 return 0; 1629 } 1630 1631 static void ds1307_clks_register(struct ds1307 *ds1307) 1632 { 1633 int ret; 1634 1635 if (ds1307->type != ds_3231) 1636 return; 1637 1638 ret = ds3231_clks_register(ds1307); 1639 if (ret) { 1640 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1641 ret); 1642 } 1643 } 1644 1645 #else 1646 1647 static void ds1307_clks_register(struct ds1307 *ds1307) 1648 { 1649 } 1650 1651 #endif /* CONFIG_COMMON_CLK */ 1652 1653 #ifdef CONFIG_WATCHDOG_CORE 1654 static const struct watchdog_info ds1388_wdt_info = { 1655 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 1656 .identity = "DS1388 watchdog", 1657 }; 1658 1659 static const struct watchdog_ops ds1388_wdt_ops = { 1660 .owner = THIS_MODULE, 1661 .start = ds1388_wdt_start, 1662 .stop = ds1388_wdt_stop, 1663 .ping = ds1388_wdt_ping, 1664 .set_timeout = ds1388_wdt_set_timeout, 1665 1666 }; 1667 1668 static void ds1307_wdt_register(struct ds1307 *ds1307) 1669 { 1670 struct watchdog_device *wdt; 1671 int err; 1672 int val; 1673 1674 if (ds1307->type != ds_1388) 1675 return; 1676 1677 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL); 1678 if (!wdt) 1679 return; 1680 1681 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val); 1682 if (!err && val & DS1388_BIT_WF) 1683 wdt->bootstatus = WDIOF_CARDRESET; 1684 1685 wdt->info = &ds1388_wdt_info; 1686 wdt->ops = &ds1388_wdt_ops; 1687 wdt->timeout = 99; 1688 wdt->max_timeout = 99; 1689 wdt->min_timeout = 1; 1690 1691 watchdog_init_timeout(wdt, 0, ds1307->dev); 1692 watchdog_set_drvdata(wdt, ds1307); 1693 devm_watchdog_register_device(ds1307->dev, wdt); 1694 } 1695 #else 1696 static void ds1307_wdt_register(struct ds1307 *ds1307) 1697 { 1698 } 1699 #endif /* CONFIG_WATCHDOG_CORE */ 1700 1701 static const struct regmap_config regmap_config = { 1702 .reg_bits = 8, 1703 .val_bits = 8, 1704 }; 1705 1706 static int ds1307_probe(struct i2c_client *client, 1707 const struct i2c_device_id *id) 1708 { 1709 struct ds1307 *ds1307; 1710 int err = -ENODEV; 1711 int tmp; 1712 const struct chip_desc *chip; 1713 bool want_irq; 1714 bool ds1307_can_wakeup_device = false; 1715 unsigned char regs[8]; 1716 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1717 u8 trickle_charger_setup = 0; 1718 1719 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1720 if (!ds1307) 1721 return -ENOMEM; 1722 1723 dev_set_drvdata(&client->dev, ds1307); 1724 ds1307->dev = &client->dev; 1725 ds1307->name = client->name; 1726 1727 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1728 if (IS_ERR(ds1307->regmap)) { 1729 dev_err(ds1307->dev, "regmap allocation failed\n"); 1730 return PTR_ERR(ds1307->regmap); 1731 } 1732 1733 i2c_set_clientdata(client, ds1307); 1734 1735 if (client->dev.of_node) { 1736 ds1307->type = (enum ds_type) 1737 of_device_get_match_data(&client->dev); 1738 chip = &chips[ds1307->type]; 1739 } else if (id) { 1740 chip = &chips[id->driver_data]; 1741 ds1307->type = id->driver_data; 1742 } else { 1743 const struct acpi_device_id *acpi_id; 1744 1745 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids), 1746 ds1307->dev); 1747 if (!acpi_id) 1748 return -ENODEV; 1749 chip = &chips[acpi_id->driver_data]; 1750 ds1307->type = acpi_id->driver_data; 1751 } 1752 1753 want_irq = client->irq > 0 && chip->alarm; 1754 1755 if (!pdata) 1756 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1757 else if (pdata->trickle_charger_setup) 1758 trickle_charger_setup = pdata->trickle_charger_setup; 1759 1760 if (trickle_charger_setup && chip->trickle_charger_reg) { 1761 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 1762 dev_dbg(ds1307->dev, 1763 "writing trickle charger info 0x%x to 0x%x\n", 1764 trickle_charger_setup, chip->trickle_charger_reg); 1765 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1766 trickle_charger_setup); 1767 } 1768 1769 #ifdef CONFIG_OF 1770 /* 1771 * For devices with no IRQ directly connected to the SoC, the RTC chip 1772 * can be forced as a wakeup source by stating that explicitly in 1773 * the device's .dts file using the "wakeup-source" boolean property. 1774 * If the "wakeup-source" property is set, don't request an IRQ. 1775 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1776 * if supported by the RTC. 1777 */ 1778 if (chip->alarm && of_property_read_bool(client->dev.of_node, 1779 "wakeup-source")) 1780 ds1307_can_wakeup_device = true; 1781 #endif 1782 1783 switch (ds1307->type) { 1784 case ds_1337: 1785 case ds_1339: 1786 case ds_1341: 1787 case ds_3231: 1788 /* get registers that the "rtc" read below won't read... */ 1789 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1790 regs, 2); 1791 if (err) { 1792 dev_dbg(ds1307->dev, "read error %d\n", err); 1793 goto exit; 1794 } 1795 1796 /* oscillator off? turn it on, so clock can tick. */ 1797 if (regs[0] & DS1337_BIT_nEOSC) 1798 regs[0] &= ~DS1337_BIT_nEOSC; 1799 1800 /* 1801 * Using IRQ or defined as wakeup-source? 1802 * Disable the square wave and both alarms. 1803 * For some variants, be sure alarms can trigger when we're 1804 * running on Vbackup (BBSQI/BBSQW) 1805 */ 1806 if (want_irq || ds1307_can_wakeup_device) { 1807 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1808 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); 1809 } 1810 1811 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1812 regs[0]); 1813 1814 /* oscillator fault? clear flag, and warn */ 1815 if (regs[1] & DS1337_BIT_OSF) { 1816 regmap_write(ds1307->regmap, DS1337_REG_STATUS, 1817 regs[1] & ~DS1337_BIT_OSF); 1818 dev_warn(ds1307->dev, "SET TIME!\n"); 1819 } 1820 break; 1821 1822 case rx_8025: 1823 err = regmap_bulk_read(ds1307->regmap, 1824 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1825 if (err) { 1826 dev_dbg(ds1307->dev, "read error %d\n", err); 1827 goto exit; 1828 } 1829 1830 /* oscillator off? turn it on, so clock can tick. */ 1831 if (!(regs[1] & RX8025_BIT_XST)) { 1832 regs[1] |= RX8025_BIT_XST; 1833 regmap_write(ds1307->regmap, 1834 RX8025_REG_CTRL2 << 4 | 0x08, 1835 regs[1]); 1836 dev_warn(ds1307->dev, 1837 "oscillator stop detected - SET TIME!\n"); 1838 } 1839 1840 if (regs[1] & RX8025_BIT_PON) { 1841 regs[1] &= ~RX8025_BIT_PON; 1842 regmap_write(ds1307->regmap, 1843 RX8025_REG_CTRL2 << 4 | 0x08, 1844 regs[1]); 1845 dev_warn(ds1307->dev, "power-on detected\n"); 1846 } 1847 1848 if (regs[1] & RX8025_BIT_VDET) { 1849 regs[1] &= ~RX8025_BIT_VDET; 1850 regmap_write(ds1307->regmap, 1851 RX8025_REG_CTRL2 << 4 | 0x08, 1852 regs[1]); 1853 dev_warn(ds1307->dev, "voltage drop detected\n"); 1854 } 1855 1856 /* make sure we are running in 24hour mode */ 1857 if (!(regs[0] & RX8025_BIT_2412)) { 1858 u8 hour; 1859 1860 /* switch to 24 hour mode */ 1861 regmap_write(ds1307->regmap, 1862 RX8025_REG_CTRL1 << 4 | 0x08, 1863 regs[0] | RX8025_BIT_2412); 1864 1865 err = regmap_bulk_read(ds1307->regmap, 1866 RX8025_REG_CTRL1 << 4 | 0x08, 1867 regs, 2); 1868 if (err) { 1869 dev_dbg(ds1307->dev, "read error %d\n", err); 1870 goto exit; 1871 } 1872 1873 /* correct hour */ 1874 hour = bcd2bin(regs[DS1307_REG_HOUR]); 1875 if (hour == 12) 1876 hour = 0; 1877 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1878 hour += 12; 1879 1880 regmap_write(ds1307->regmap, 1881 DS1307_REG_HOUR << 4 | 0x08, hour); 1882 } 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 /* read RTC registers */ 1889 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 1890 sizeof(regs)); 1891 if (err) { 1892 dev_dbg(ds1307->dev, "read error %d\n", err); 1893 goto exit; 1894 } 1895 1896 if (ds1307->type == mcp794xx && 1897 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 1898 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 1899 regs[DS1307_REG_WDAY] | 1900 MCP794XX_BIT_VBATEN); 1901 } 1902 1903 tmp = regs[DS1307_REG_HOUR]; 1904 switch (ds1307->type) { 1905 case ds_1340: 1906 case m41t0: 1907 case m41t00: 1908 case m41t11: 1909 /* 1910 * NOTE: ignores century bits; fix before deploying 1911 * systems that will run through year 2100. 1912 */ 1913 break; 1914 case rx_8025: 1915 break; 1916 default: 1917 if (!(tmp & DS1307_BIT_12HR)) 1918 break; 1919 1920 /* 1921 * Be sure we're in 24 hour mode. Multi-master systems 1922 * take note... 1923 */ 1924 tmp = bcd2bin(tmp & 0x1f); 1925 if (tmp == 12) 1926 tmp = 0; 1927 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1928 tmp += 12; 1929 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 1930 bin2bcd(tmp)); 1931 } 1932 1933 if (want_irq || ds1307_can_wakeup_device) { 1934 device_set_wakeup_capable(ds1307->dev, true); 1935 set_bit(HAS_ALARM, &ds1307->flags); 1936 } 1937 1938 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 1939 if (IS_ERR(ds1307->rtc)) 1940 return PTR_ERR(ds1307->rtc); 1941 1942 if (ds1307_can_wakeup_device && !want_irq) { 1943 dev_info(ds1307->dev, 1944 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 1945 /* We cannot support UIE mode if we do not have an IRQ line */ 1946 ds1307->rtc->uie_unsupported = 1; 1947 } 1948 1949 if (want_irq) { 1950 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 1951 chip->irq_handler ?: ds1307_irq, 1952 IRQF_SHARED | IRQF_ONESHOT, 1953 ds1307->name, ds1307); 1954 if (err) { 1955 client->irq = 0; 1956 device_set_wakeup_capable(ds1307->dev, false); 1957 clear_bit(HAS_ALARM, &ds1307->flags); 1958 dev_err(ds1307->dev, "unable to request IRQ!\n"); 1959 } else { 1960 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 1961 } 1962 } 1963 1964 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 1965 err = ds1307_add_frequency_test(ds1307); 1966 if (err) 1967 return err; 1968 1969 err = rtc_register_device(ds1307->rtc); 1970 if (err) 1971 return err; 1972 1973 if (chip->nvram_size) { 1974 struct nvmem_config nvmem_cfg = { 1975 .name = "ds1307_nvram", 1976 .word_size = 1, 1977 .stride = 1, 1978 .size = chip->nvram_size, 1979 .reg_read = ds1307_nvram_read, 1980 .reg_write = ds1307_nvram_write, 1981 .priv = ds1307, 1982 }; 1983 1984 ds1307->rtc->nvram_old_abi = true; 1985 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 1986 } 1987 1988 ds1307_hwmon_register(ds1307); 1989 ds1307_clks_register(ds1307); 1990 ds1307_wdt_register(ds1307); 1991 1992 return 0; 1993 1994 exit: 1995 return err; 1996 } 1997 1998 static struct i2c_driver ds1307_driver = { 1999 .driver = { 2000 .name = "rtc-ds1307", 2001 .of_match_table = of_match_ptr(ds1307_of_match), 2002 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids), 2003 }, 2004 .probe = ds1307_probe, 2005 .id_table = ds1307_id, 2006 }; 2007 2008 module_i2c_driver(ds1307_driver); 2009 2010 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 2011 MODULE_LICENSE("GPL"); 2012