1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 4 * 5 * Copyright (C) 2005 James Chapman (ds1337 core) 6 * Copyright (C) 2006 David Brownell 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bcd.h> 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/rtc/ds1307.h> 18 #include <linux/rtc.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 26 /* 27 * We can't determine type by probing, but if we expect pre-Linux code 28 * to have set the chip up as a clock (turning on the oscillator and 29 * setting the date and time), Linux can ignore the non-clock features. 30 * That's a natural job for a factory or repair bench. 31 */ 32 enum ds_type { 33 ds_1307, 34 ds_1308, 35 ds_1337, 36 ds_1338, 37 ds_1339, 38 ds_1340, 39 ds_1341, 40 ds_1388, 41 ds_3231, 42 m41t0, 43 m41t00, 44 m41t11, 45 mcp794xx, 46 rx_8025, 47 rx_8130, 48 last_ds_type /* always last */ 49 /* rs5c372 too? different address... */ 50 }; 51 52 /* RTC registers don't differ much, except for the century flag */ 53 #define DS1307_REG_SECS 0x00 /* 00-59 */ 54 # define DS1307_BIT_CH 0x80 55 # define DS1340_BIT_nEOSC 0x80 56 # define MCP794XX_BIT_ST 0x80 57 #define DS1307_REG_MIN 0x01 /* 00-59 */ 58 # define M41T0_BIT_OF 0x80 59 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 60 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 61 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 62 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 63 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 64 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 65 # define MCP794XX_BIT_VBATEN 0x08 66 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 67 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 68 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 69 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 70 71 /* 72 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 73 * start at 7, and they differ a LOT. Only control and status matter for 74 * basic RTC date and time functionality; be careful using them. 75 */ 76 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 77 # define DS1307_BIT_OUT 0x80 78 # define DS1338_BIT_OSF 0x20 79 # define DS1307_BIT_SQWE 0x10 80 # define DS1307_BIT_RS1 0x02 81 # define DS1307_BIT_RS0 0x01 82 #define DS1337_REG_CONTROL 0x0e 83 # define DS1337_BIT_nEOSC 0x80 84 # define DS1339_BIT_BBSQI 0x20 85 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 86 # define DS1337_BIT_RS2 0x10 87 # define DS1337_BIT_RS1 0x08 88 # define DS1337_BIT_INTCN 0x04 89 # define DS1337_BIT_A2IE 0x02 90 # define DS1337_BIT_A1IE 0x01 91 #define DS1340_REG_CONTROL 0x07 92 # define DS1340_BIT_OUT 0x80 93 # define DS1340_BIT_FT 0x40 94 # define DS1340_BIT_CALIB_SIGN 0x20 95 # define DS1340_M_CALIBRATION 0x1f 96 #define DS1340_REG_FLAG 0x09 97 # define DS1340_BIT_OSF 0x80 98 #define DS1337_REG_STATUS 0x0f 99 # define DS1337_BIT_OSF 0x80 100 # define DS3231_BIT_EN32KHZ 0x08 101 # define DS1337_BIT_A2I 0x02 102 # define DS1337_BIT_A1I 0x01 103 #define DS1339_REG_ALARM1_SECS 0x07 104 105 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 106 107 #define RX8025_REG_CTRL1 0x0e 108 # define RX8025_BIT_2412 0x20 109 #define RX8025_REG_CTRL2 0x0f 110 # define RX8025_BIT_PON 0x10 111 # define RX8025_BIT_VDET 0x40 112 # define RX8025_BIT_XST 0x20 113 114 #define RX8130_REG_ALARM_MIN 0x17 115 #define RX8130_REG_ALARM_HOUR 0x18 116 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 117 #define RX8130_REG_EXTENSION 0x1c 118 #define RX8130_REG_EXTENSION_WADA BIT(3) 119 #define RX8130_REG_FLAG 0x1d 120 #define RX8130_REG_FLAG_VLF BIT(1) 121 #define RX8130_REG_FLAG_AF BIT(3) 122 #define RX8130_REG_CONTROL0 0x1e 123 #define RX8130_REG_CONTROL0_AIE BIT(3) 124 125 #define MCP794XX_REG_CONTROL 0x07 126 # define MCP794XX_BIT_ALM0_EN 0x10 127 # define MCP794XX_BIT_ALM1_EN 0x20 128 #define MCP794XX_REG_ALARM0_BASE 0x0a 129 #define MCP794XX_REG_ALARM0_CTRL 0x0d 130 #define MCP794XX_REG_ALARM1_BASE 0x11 131 #define MCP794XX_REG_ALARM1_CTRL 0x14 132 # define MCP794XX_BIT_ALMX_IF BIT(3) 133 # define MCP794XX_BIT_ALMX_C0 BIT(4) 134 # define MCP794XX_BIT_ALMX_C1 BIT(5) 135 # define MCP794XX_BIT_ALMX_C2 BIT(6) 136 # define MCP794XX_BIT_ALMX_POL BIT(7) 137 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 138 MCP794XX_BIT_ALMX_C1 | \ 139 MCP794XX_BIT_ALMX_C2) 140 141 #define M41TXX_REG_CONTROL 0x07 142 # define M41TXX_BIT_OUT BIT(7) 143 # define M41TXX_BIT_FT BIT(6) 144 # define M41TXX_BIT_CALIB_SIGN BIT(5) 145 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 146 147 /* negative offset step is -2.034ppm */ 148 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 149 /* positive offset step is +4.068ppm */ 150 #define M41TXX_POS_OFFSET_STEP_PPB 4068 151 /* Min and max values supported with 'offset' interface by M41TXX */ 152 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 153 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 154 155 struct ds1307 { 156 enum ds_type type; 157 unsigned long flags; 158 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ 159 #define HAS_ALARM 1 /* bit 1 == irq claimed */ 160 struct device *dev; 161 struct regmap *regmap; 162 const char *name; 163 struct rtc_device *rtc; 164 #ifdef CONFIG_COMMON_CLK 165 struct clk_hw clks[2]; 166 #endif 167 }; 168 169 struct chip_desc { 170 unsigned alarm:1; 171 u16 nvram_offset; 172 u16 nvram_size; 173 u8 offset; /* register's offset */ 174 u8 century_reg; 175 u8 century_enable_bit; 176 u8 century_bit; 177 u8 bbsqi_bit; 178 irq_handler_t irq_handler; 179 const struct rtc_class_ops *rtc_ops; 180 u16 trickle_charger_reg; 181 u8 (*do_trickle_setup)(struct ds1307 *, u32, 182 bool); 183 }; 184 185 static const struct chip_desc chips[last_ds_type]; 186 187 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 188 { 189 struct ds1307 *ds1307 = dev_get_drvdata(dev); 190 int tmp, ret; 191 const struct chip_desc *chip = &chips[ds1307->type]; 192 u8 regs[7]; 193 194 if (ds1307->type == rx_8130) { 195 unsigned int regflag; 196 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 197 if (ret) { 198 dev_err(dev, "%s error %d\n", "read", ret); 199 return ret; 200 } 201 202 if (regflag & RX8130_REG_FLAG_VLF) { 203 dev_warn_once(dev, "oscillator failed, set time!\n"); 204 return -EINVAL; 205 } 206 } 207 208 /* read the RTC date and time registers all at once */ 209 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 210 sizeof(regs)); 211 if (ret) { 212 dev_err(dev, "%s error %d\n", "read", ret); 213 return ret; 214 } 215 216 dev_dbg(dev, "%s: %7ph\n", "read", regs); 217 218 /* if oscillator fail bit is set, no data can be trusted */ 219 if (ds1307->type == m41t0 && 220 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 221 dev_warn_once(dev, "oscillator failed, set time!\n"); 222 return -EINVAL; 223 } 224 225 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 226 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 227 tmp = regs[DS1307_REG_HOUR] & 0x3f; 228 t->tm_hour = bcd2bin(tmp); 229 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 230 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 231 tmp = regs[DS1307_REG_MONTH] & 0x1f; 232 t->tm_mon = bcd2bin(tmp) - 1; 233 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 234 235 if (regs[chip->century_reg] & chip->century_bit && 236 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 237 t->tm_year += 100; 238 239 dev_dbg(dev, "%s secs=%d, mins=%d, " 240 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 241 "read", t->tm_sec, t->tm_min, 242 t->tm_hour, t->tm_mday, 243 t->tm_mon, t->tm_year, t->tm_wday); 244 245 return 0; 246 } 247 248 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 249 { 250 struct ds1307 *ds1307 = dev_get_drvdata(dev); 251 const struct chip_desc *chip = &chips[ds1307->type]; 252 int result; 253 int tmp; 254 u8 regs[7]; 255 256 dev_dbg(dev, "%s secs=%d, mins=%d, " 257 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 258 "write", t->tm_sec, t->tm_min, 259 t->tm_hour, t->tm_mday, 260 t->tm_mon, t->tm_year, t->tm_wday); 261 262 if (t->tm_year < 100) 263 return -EINVAL; 264 265 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 266 if (t->tm_year > (chip->century_bit ? 299 : 199)) 267 return -EINVAL; 268 #else 269 if (t->tm_year > 199) 270 return -EINVAL; 271 #endif 272 273 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 274 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 275 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 276 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 277 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 278 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 279 280 /* assume 20YY not 19YY */ 281 tmp = t->tm_year - 100; 282 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 283 284 if (chip->century_enable_bit) 285 regs[chip->century_reg] |= chip->century_enable_bit; 286 if (t->tm_year > 199 && chip->century_bit) 287 regs[chip->century_reg] |= chip->century_bit; 288 289 if (ds1307->type == mcp794xx) { 290 /* 291 * these bits were cleared when preparing the date/time 292 * values and need to be set again before writing the 293 * regsfer out to the device. 294 */ 295 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 296 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 297 } 298 299 dev_dbg(dev, "%s: %7ph\n", "write", regs); 300 301 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 302 sizeof(regs)); 303 if (result) { 304 dev_err(dev, "%s error %d\n", "write", result); 305 return result; 306 } 307 308 if (ds1307->type == rx_8130) { 309 /* clear Voltage Loss Flag as data is available now */ 310 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 311 ~(u8)RX8130_REG_FLAG_VLF); 312 if (result) { 313 dev_err(dev, "%s error %d\n", "write", result); 314 return result; 315 } 316 } 317 318 return 0; 319 } 320 321 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 322 { 323 struct ds1307 *ds1307 = dev_get_drvdata(dev); 324 int ret; 325 u8 regs[9]; 326 327 if (!test_bit(HAS_ALARM, &ds1307->flags)) 328 return -EINVAL; 329 330 /* read all ALARM1, ALARM2, and status registers at once */ 331 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 332 regs, sizeof(regs)); 333 if (ret) { 334 dev_err(dev, "%s error %d\n", "alarm read", ret); 335 return ret; 336 } 337 338 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 339 ®s[0], ®s[4], ®s[7]); 340 341 /* 342 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 343 * and that all four fields are checked matches 344 */ 345 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 346 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 347 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 348 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 349 350 /* ... and status */ 351 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 352 t->pending = !!(regs[8] & DS1337_BIT_A1I); 353 354 dev_dbg(dev, "%s secs=%d, mins=%d, " 355 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 356 "alarm read", t->time.tm_sec, t->time.tm_min, 357 t->time.tm_hour, t->time.tm_mday, 358 t->enabled, t->pending); 359 360 return 0; 361 } 362 363 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 364 { 365 struct ds1307 *ds1307 = dev_get_drvdata(dev); 366 unsigned char regs[9]; 367 u8 control, status; 368 int ret; 369 370 if (!test_bit(HAS_ALARM, &ds1307->flags)) 371 return -EINVAL; 372 373 dev_dbg(dev, "%s secs=%d, mins=%d, " 374 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 375 "alarm set", t->time.tm_sec, t->time.tm_min, 376 t->time.tm_hour, t->time.tm_mday, 377 t->enabled, t->pending); 378 379 /* read current status of both alarms and the chip */ 380 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 381 sizeof(regs)); 382 if (ret) { 383 dev_err(dev, "%s error %d\n", "alarm write", ret); 384 return ret; 385 } 386 control = regs[7]; 387 status = regs[8]; 388 389 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 390 ®s[0], ®s[4], control, status); 391 392 /* set ALARM1, using 24 hour and day-of-month modes */ 393 regs[0] = bin2bcd(t->time.tm_sec); 394 regs[1] = bin2bcd(t->time.tm_min); 395 regs[2] = bin2bcd(t->time.tm_hour); 396 regs[3] = bin2bcd(t->time.tm_mday); 397 398 /* set ALARM2 to non-garbage */ 399 regs[4] = 0; 400 regs[5] = 0; 401 regs[6] = 0; 402 403 /* disable alarms */ 404 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 405 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 406 407 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 408 sizeof(regs)); 409 if (ret) { 410 dev_err(dev, "can't set alarm time\n"); 411 return ret; 412 } 413 414 /* optionally enable ALARM1 */ 415 if (t->enabled) { 416 dev_dbg(dev, "alarm IRQ armed\n"); 417 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 418 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 419 } 420 421 return 0; 422 } 423 424 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 425 { 426 struct ds1307 *ds1307 = dev_get_drvdata(dev); 427 428 if (!test_bit(HAS_ALARM, &ds1307->flags)) 429 return -ENOTTY; 430 431 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 432 DS1337_BIT_A1IE, 433 enabled ? DS1337_BIT_A1IE : 0); 434 } 435 436 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 437 { 438 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 439 DS1307_TRICKLE_CHARGER_NO_DIODE; 440 441 switch (ohms) { 442 case 250: 443 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 444 break; 445 case 2000: 446 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 447 break; 448 case 4000: 449 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 450 break; 451 default: 452 dev_warn(ds1307->dev, 453 "Unsupported ohm value %u in dt\n", ohms); 454 return 0; 455 } 456 return setup; 457 } 458 459 static irqreturn_t rx8130_irq(int irq, void *dev_id) 460 { 461 struct ds1307 *ds1307 = dev_id; 462 struct mutex *lock = &ds1307->rtc->ops_lock; 463 u8 ctl[3]; 464 int ret; 465 466 mutex_lock(lock); 467 468 /* Read control registers. */ 469 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 470 sizeof(ctl)); 471 if (ret < 0) 472 goto out; 473 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 474 goto out; 475 ctl[1] &= ~RX8130_REG_FLAG_AF; 476 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 477 478 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 479 sizeof(ctl)); 480 if (ret < 0) 481 goto out; 482 483 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 484 485 out: 486 mutex_unlock(lock); 487 488 return IRQ_HANDLED; 489 } 490 491 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 492 { 493 struct ds1307 *ds1307 = dev_get_drvdata(dev); 494 u8 ald[3], ctl[3]; 495 int ret; 496 497 if (!test_bit(HAS_ALARM, &ds1307->flags)) 498 return -EINVAL; 499 500 /* Read alarm registers. */ 501 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 502 sizeof(ald)); 503 if (ret < 0) 504 return ret; 505 506 /* Read control registers. */ 507 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 508 sizeof(ctl)); 509 if (ret < 0) 510 return ret; 511 512 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 513 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 514 515 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 516 t->time.tm_sec = -1; 517 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 518 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 519 t->time.tm_wday = -1; 520 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 521 t->time.tm_mon = -1; 522 t->time.tm_year = -1; 523 t->time.tm_yday = -1; 524 t->time.tm_isdst = -1; 525 526 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 527 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 528 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 529 530 return 0; 531 } 532 533 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 534 { 535 struct ds1307 *ds1307 = dev_get_drvdata(dev); 536 u8 ald[3], ctl[3]; 537 int ret; 538 539 if (!test_bit(HAS_ALARM, &ds1307->flags)) 540 return -EINVAL; 541 542 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 543 "enabled=%d pending=%d\n", __func__, 544 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 545 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 546 t->enabled, t->pending); 547 548 /* Read control registers. */ 549 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 550 sizeof(ctl)); 551 if (ret < 0) 552 return ret; 553 554 ctl[0] &= RX8130_REG_EXTENSION_WADA; 555 ctl[1] &= ~RX8130_REG_FLAG_AF; 556 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 557 558 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 559 sizeof(ctl)); 560 if (ret < 0) 561 return ret; 562 563 /* Hardware alarm precision is 1 minute! */ 564 ald[0] = bin2bcd(t->time.tm_min); 565 ald[1] = bin2bcd(t->time.tm_hour); 566 ald[2] = bin2bcd(t->time.tm_mday); 567 568 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 569 sizeof(ald)); 570 if (ret < 0) 571 return ret; 572 573 if (!t->enabled) 574 return 0; 575 576 ctl[2] |= RX8130_REG_CONTROL0_AIE; 577 578 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 579 } 580 581 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 582 { 583 struct ds1307 *ds1307 = dev_get_drvdata(dev); 584 int ret, reg; 585 586 if (!test_bit(HAS_ALARM, &ds1307->flags)) 587 return -EINVAL; 588 589 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 590 if (ret < 0) 591 return ret; 592 593 if (enabled) 594 reg |= RX8130_REG_CONTROL0_AIE; 595 else 596 reg &= ~RX8130_REG_CONTROL0_AIE; 597 598 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 599 } 600 601 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 602 { 603 struct ds1307 *ds1307 = dev_id; 604 struct mutex *lock = &ds1307->rtc->ops_lock; 605 int reg, ret; 606 607 mutex_lock(lock); 608 609 /* Check and clear alarm 0 interrupt flag. */ 610 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 611 if (ret) 612 goto out; 613 if (!(reg & MCP794XX_BIT_ALMX_IF)) 614 goto out; 615 reg &= ~MCP794XX_BIT_ALMX_IF; 616 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 617 if (ret) 618 goto out; 619 620 /* Disable alarm 0. */ 621 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 622 MCP794XX_BIT_ALM0_EN, 0); 623 if (ret) 624 goto out; 625 626 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 627 628 out: 629 mutex_unlock(lock); 630 631 return IRQ_HANDLED; 632 } 633 634 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 635 { 636 struct ds1307 *ds1307 = dev_get_drvdata(dev); 637 u8 regs[10]; 638 int ret; 639 640 if (!test_bit(HAS_ALARM, &ds1307->flags)) 641 return -EINVAL; 642 643 /* Read control and alarm 0 registers. */ 644 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 645 sizeof(regs)); 646 if (ret) 647 return ret; 648 649 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 650 651 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 652 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 653 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 654 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 655 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 656 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 657 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 658 t->time.tm_year = -1; 659 t->time.tm_yday = -1; 660 t->time.tm_isdst = -1; 661 662 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 663 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 664 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 665 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 666 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 667 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 668 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 669 670 return 0; 671 } 672 673 /* 674 * We may have a random RTC weekday, therefore calculate alarm weekday based 675 * on current weekday we read from the RTC timekeeping regs 676 */ 677 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 678 { 679 struct rtc_time tm_now; 680 int days_now, days_alarm, ret; 681 682 ret = ds1307_get_time(dev, &tm_now); 683 if (ret) 684 return ret; 685 686 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 687 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 688 689 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 690 } 691 692 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 693 { 694 struct ds1307 *ds1307 = dev_get_drvdata(dev); 695 unsigned char regs[10]; 696 int wday, ret; 697 698 if (!test_bit(HAS_ALARM, &ds1307->flags)) 699 return -EINVAL; 700 701 wday = mcp794xx_alm_weekday(dev, &t->time); 702 if (wday < 0) 703 return wday; 704 705 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 706 "enabled=%d pending=%d\n", __func__, 707 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 708 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 709 t->enabled, t->pending); 710 711 /* Read control and alarm 0 registers. */ 712 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 713 sizeof(regs)); 714 if (ret) 715 return ret; 716 717 /* Set alarm 0, using 24-hour and day-of-month modes. */ 718 regs[3] = bin2bcd(t->time.tm_sec); 719 regs[4] = bin2bcd(t->time.tm_min); 720 regs[5] = bin2bcd(t->time.tm_hour); 721 regs[6] = wday; 722 regs[7] = bin2bcd(t->time.tm_mday); 723 regs[8] = bin2bcd(t->time.tm_mon + 1); 724 725 /* Clear the alarm 0 interrupt flag. */ 726 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 727 /* Set alarm match: second, minute, hour, day, date, month. */ 728 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 729 /* Disable interrupt. We will not enable until completely programmed */ 730 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 731 732 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 733 sizeof(regs)); 734 if (ret) 735 return ret; 736 737 if (!t->enabled) 738 return 0; 739 regs[0] |= MCP794XX_BIT_ALM0_EN; 740 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 741 } 742 743 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 744 { 745 struct ds1307 *ds1307 = dev_get_drvdata(dev); 746 747 if (!test_bit(HAS_ALARM, &ds1307->flags)) 748 return -EINVAL; 749 750 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 751 MCP794XX_BIT_ALM0_EN, 752 enabled ? MCP794XX_BIT_ALM0_EN : 0); 753 } 754 755 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 756 { 757 struct ds1307 *ds1307 = dev_get_drvdata(dev); 758 unsigned int ctrl_reg; 759 u8 val; 760 761 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 762 763 val = ctrl_reg & M41TXX_M_CALIBRATION; 764 765 /* check if positive */ 766 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 767 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 768 else 769 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 770 771 return 0; 772 } 773 774 static int m41txx_rtc_set_offset(struct device *dev, long offset) 775 { 776 struct ds1307 *ds1307 = dev_get_drvdata(dev); 777 unsigned int ctrl_reg; 778 779 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 780 return -ERANGE; 781 782 if (offset >= 0) { 783 ctrl_reg = DIV_ROUND_CLOSEST(offset, 784 M41TXX_POS_OFFSET_STEP_PPB); 785 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 786 } else { 787 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 788 M41TXX_NEG_OFFSET_STEP_PPB); 789 } 790 791 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 792 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 793 ctrl_reg); 794 } 795 796 static const struct rtc_class_ops rx8130_rtc_ops = { 797 .read_time = ds1307_get_time, 798 .set_time = ds1307_set_time, 799 .read_alarm = rx8130_read_alarm, 800 .set_alarm = rx8130_set_alarm, 801 .alarm_irq_enable = rx8130_alarm_irq_enable, 802 }; 803 804 static const struct rtc_class_ops mcp794xx_rtc_ops = { 805 .read_time = ds1307_get_time, 806 .set_time = ds1307_set_time, 807 .read_alarm = mcp794xx_read_alarm, 808 .set_alarm = mcp794xx_set_alarm, 809 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 810 }; 811 812 static const struct rtc_class_ops m41txx_rtc_ops = { 813 .read_time = ds1307_get_time, 814 .set_time = ds1307_set_time, 815 .read_alarm = ds1337_read_alarm, 816 .set_alarm = ds1337_set_alarm, 817 .alarm_irq_enable = ds1307_alarm_irq_enable, 818 .read_offset = m41txx_rtc_read_offset, 819 .set_offset = m41txx_rtc_set_offset, 820 }; 821 822 static const struct chip_desc chips[last_ds_type] = { 823 [ds_1307] = { 824 .nvram_offset = 8, 825 .nvram_size = 56, 826 }, 827 [ds_1308] = { 828 .nvram_offset = 8, 829 .nvram_size = 56, 830 }, 831 [ds_1337] = { 832 .alarm = 1, 833 .century_reg = DS1307_REG_MONTH, 834 .century_bit = DS1337_BIT_CENTURY, 835 }, 836 [ds_1338] = { 837 .nvram_offset = 8, 838 .nvram_size = 56, 839 }, 840 [ds_1339] = { 841 .alarm = 1, 842 .century_reg = DS1307_REG_MONTH, 843 .century_bit = DS1337_BIT_CENTURY, 844 .bbsqi_bit = DS1339_BIT_BBSQI, 845 .trickle_charger_reg = 0x10, 846 .do_trickle_setup = &do_trickle_setup_ds1339, 847 }, 848 [ds_1340] = { 849 .century_reg = DS1307_REG_HOUR, 850 .century_enable_bit = DS1340_BIT_CENTURY_EN, 851 .century_bit = DS1340_BIT_CENTURY, 852 .do_trickle_setup = &do_trickle_setup_ds1339, 853 .trickle_charger_reg = 0x08, 854 }, 855 [ds_1341] = { 856 .century_reg = DS1307_REG_MONTH, 857 .century_bit = DS1337_BIT_CENTURY, 858 }, 859 [ds_1388] = { 860 .offset = 1, 861 .trickle_charger_reg = 0x0a, 862 }, 863 [ds_3231] = { 864 .alarm = 1, 865 .century_reg = DS1307_REG_MONTH, 866 .century_bit = DS1337_BIT_CENTURY, 867 .bbsqi_bit = DS3231_BIT_BBSQW, 868 }, 869 [rx_8130] = { 870 .alarm = 1, 871 /* this is battery backed SRAM */ 872 .nvram_offset = 0x20, 873 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 874 .offset = 0x10, 875 .irq_handler = rx8130_irq, 876 .rtc_ops = &rx8130_rtc_ops, 877 }, 878 [m41t0] = { 879 .rtc_ops = &m41txx_rtc_ops, 880 }, 881 [m41t00] = { 882 .rtc_ops = &m41txx_rtc_ops, 883 }, 884 [m41t11] = { 885 /* this is battery backed SRAM */ 886 .nvram_offset = 8, 887 .nvram_size = 56, 888 .rtc_ops = &m41txx_rtc_ops, 889 }, 890 [mcp794xx] = { 891 .alarm = 1, 892 /* this is battery backed SRAM */ 893 .nvram_offset = 0x20, 894 .nvram_size = 0x40, 895 .irq_handler = mcp794xx_irq, 896 .rtc_ops = &mcp794xx_rtc_ops, 897 }, 898 }; 899 900 static const struct i2c_device_id ds1307_id[] = { 901 { "ds1307", ds_1307 }, 902 { "ds1308", ds_1308 }, 903 { "ds1337", ds_1337 }, 904 { "ds1338", ds_1338 }, 905 { "ds1339", ds_1339 }, 906 { "ds1388", ds_1388 }, 907 { "ds1340", ds_1340 }, 908 { "ds1341", ds_1341 }, 909 { "ds3231", ds_3231 }, 910 { "m41t0", m41t0 }, 911 { "m41t00", m41t00 }, 912 { "m41t11", m41t11 }, 913 { "mcp7940x", mcp794xx }, 914 { "mcp7941x", mcp794xx }, 915 { "pt7c4338", ds_1307 }, 916 { "rx8025", rx_8025 }, 917 { "isl12057", ds_1337 }, 918 { "rx8130", rx_8130 }, 919 { } 920 }; 921 MODULE_DEVICE_TABLE(i2c, ds1307_id); 922 923 #ifdef CONFIG_OF 924 static const struct of_device_id ds1307_of_match[] = { 925 { 926 .compatible = "dallas,ds1307", 927 .data = (void *)ds_1307 928 }, 929 { 930 .compatible = "dallas,ds1308", 931 .data = (void *)ds_1308 932 }, 933 { 934 .compatible = "dallas,ds1337", 935 .data = (void *)ds_1337 936 }, 937 { 938 .compatible = "dallas,ds1338", 939 .data = (void *)ds_1338 940 }, 941 { 942 .compatible = "dallas,ds1339", 943 .data = (void *)ds_1339 944 }, 945 { 946 .compatible = "dallas,ds1388", 947 .data = (void *)ds_1388 948 }, 949 { 950 .compatible = "dallas,ds1340", 951 .data = (void *)ds_1340 952 }, 953 { 954 .compatible = "dallas,ds1341", 955 .data = (void *)ds_1341 956 }, 957 { 958 .compatible = "maxim,ds3231", 959 .data = (void *)ds_3231 960 }, 961 { 962 .compatible = "st,m41t0", 963 .data = (void *)m41t0 964 }, 965 { 966 .compatible = "st,m41t00", 967 .data = (void *)m41t00 968 }, 969 { 970 .compatible = "st,m41t11", 971 .data = (void *)m41t11 972 }, 973 { 974 .compatible = "microchip,mcp7940x", 975 .data = (void *)mcp794xx 976 }, 977 { 978 .compatible = "microchip,mcp7941x", 979 .data = (void *)mcp794xx 980 }, 981 { 982 .compatible = "pericom,pt7c4338", 983 .data = (void *)ds_1307 984 }, 985 { 986 .compatible = "epson,rx8025", 987 .data = (void *)rx_8025 988 }, 989 { 990 .compatible = "isil,isl12057", 991 .data = (void *)ds_1337 992 }, 993 { 994 .compatible = "epson,rx8130", 995 .data = (void *)rx_8130 996 }, 997 { } 998 }; 999 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1000 #endif 1001 1002 #ifdef CONFIG_ACPI 1003 static const struct acpi_device_id ds1307_acpi_ids[] = { 1004 { .id = "DS1307", .driver_data = ds_1307 }, 1005 { .id = "DS1308", .driver_data = ds_1308 }, 1006 { .id = "DS1337", .driver_data = ds_1337 }, 1007 { .id = "DS1338", .driver_data = ds_1338 }, 1008 { .id = "DS1339", .driver_data = ds_1339 }, 1009 { .id = "DS1388", .driver_data = ds_1388 }, 1010 { .id = "DS1340", .driver_data = ds_1340 }, 1011 { .id = "DS1341", .driver_data = ds_1341 }, 1012 { .id = "DS3231", .driver_data = ds_3231 }, 1013 { .id = "M41T0", .driver_data = m41t0 }, 1014 { .id = "M41T00", .driver_data = m41t00 }, 1015 { .id = "M41T11", .driver_data = m41t11 }, 1016 { .id = "MCP7940X", .driver_data = mcp794xx }, 1017 { .id = "MCP7941X", .driver_data = mcp794xx }, 1018 { .id = "PT7C4338", .driver_data = ds_1307 }, 1019 { .id = "RX8025", .driver_data = rx_8025 }, 1020 { .id = "ISL12057", .driver_data = ds_1337 }, 1021 { .id = "RX8130", .driver_data = rx_8130 }, 1022 { } 1023 }; 1024 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); 1025 #endif 1026 1027 /* 1028 * The ds1337 and ds1339 both have two alarms, but we only use the first 1029 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1030 * signal; ds1339 chips have only one alarm signal. 1031 */ 1032 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1033 { 1034 struct ds1307 *ds1307 = dev_id; 1035 struct mutex *lock = &ds1307->rtc->ops_lock; 1036 int stat, ret; 1037 1038 mutex_lock(lock); 1039 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1040 if (ret) 1041 goto out; 1042 1043 if (stat & DS1337_BIT_A1I) { 1044 stat &= ~DS1337_BIT_A1I; 1045 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1046 1047 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1048 DS1337_BIT_A1IE, 0); 1049 if (ret) 1050 goto out; 1051 1052 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1053 } 1054 1055 out: 1056 mutex_unlock(lock); 1057 1058 return IRQ_HANDLED; 1059 } 1060 1061 /*----------------------------------------------------------------------*/ 1062 1063 static const struct rtc_class_ops ds13xx_rtc_ops = { 1064 .read_time = ds1307_get_time, 1065 .set_time = ds1307_set_time, 1066 .read_alarm = ds1337_read_alarm, 1067 .set_alarm = ds1337_set_alarm, 1068 .alarm_irq_enable = ds1307_alarm_irq_enable, 1069 }; 1070 1071 static ssize_t frequency_test_store(struct device *dev, 1072 struct device_attribute *attr, 1073 const char *buf, size_t count) 1074 { 1075 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1076 bool freq_test_en; 1077 int ret; 1078 1079 ret = kstrtobool(buf, &freq_test_en); 1080 if (ret) { 1081 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1082 return ret; 1083 } 1084 1085 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1086 freq_test_en ? M41TXX_BIT_FT : 0); 1087 1088 return count; 1089 } 1090 1091 static ssize_t frequency_test_show(struct device *dev, 1092 struct device_attribute *attr, 1093 char *buf) 1094 { 1095 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1096 unsigned int ctrl_reg; 1097 1098 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1099 1100 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : 1101 "off\n"); 1102 } 1103 1104 static DEVICE_ATTR_RW(frequency_test); 1105 1106 static struct attribute *rtc_freq_test_attrs[] = { 1107 &dev_attr_frequency_test.attr, 1108 NULL, 1109 }; 1110 1111 static const struct attribute_group rtc_freq_test_attr_group = { 1112 .attrs = rtc_freq_test_attrs, 1113 }; 1114 1115 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1116 { 1117 int err; 1118 1119 switch (ds1307->type) { 1120 case m41t0: 1121 case m41t00: 1122 case m41t11: 1123 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1124 if (err) 1125 return err; 1126 break; 1127 default: 1128 break; 1129 } 1130 1131 return 0; 1132 } 1133 1134 /*----------------------------------------------------------------------*/ 1135 1136 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1137 size_t bytes) 1138 { 1139 struct ds1307 *ds1307 = priv; 1140 const struct chip_desc *chip = &chips[ds1307->type]; 1141 1142 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1143 val, bytes); 1144 } 1145 1146 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1147 size_t bytes) 1148 { 1149 struct ds1307 *ds1307 = priv; 1150 const struct chip_desc *chip = &chips[ds1307->type]; 1151 1152 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1153 val, bytes); 1154 } 1155 1156 /*----------------------------------------------------------------------*/ 1157 1158 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1159 const struct chip_desc *chip) 1160 { 1161 u32 ohms; 1162 bool diode = true; 1163 1164 if (!chip->do_trickle_setup) 1165 return 0; 1166 1167 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1168 &ohms)) 1169 return 0; 1170 1171 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable")) 1172 diode = false; 1173 1174 return chip->do_trickle_setup(ds1307, ohms, diode); 1175 } 1176 1177 /*----------------------------------------------------------------------*/ 1178 1179 #if IS_REACHABLE(CONFIG_HWMON) 1180 1181 /* 1182 * Temperature sensor support for ds3231 devices. 1183 */ 1184 1185 #define DS3231_REG_TEMPERATURE 0x11 1186 1187 /* 1188 * A user-initiated temperature conversion is not started by this function, 1189 * so the temperature is updated once every 64 seconds. 1190 */ 1191 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1192 { 1193 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1194 u8 temp_buf[2]; 1195 s16 temp; 1196 int ret; 1197 1198 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1199 temp_buf, sizeof(temp_buf)); 1200 if (ret) 1201 return ret; 1202 /* 1203 * Temperature is represented as a 10-bit code with a resolution of 1204 * 0.25 degree celsius and encoded in two's complement format. 1205 */ 1206 temp = (temp_buf[0] << 8) | temp_buf[1]; 1207 temp >>= 6; 1208 *mC = temp * 250; 1209 1210 return 0; 1211 } 1212 1213 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1214 struct device_attribute *attr, char *buf) 1215 { 1216 int ret; 1217 s32 temp; 1218 1219 ret = ds3231_hwmon_read_temp(dev, &temp); 1220 if (ret) 1221 return ret; 1222 1223 return sprintf(buf, "%d\n", temp); 1224 } 1225 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1226 NULL, 0); 1227 1228 static struct attribute *ds3231_hwmon_attrs[] = { 1229 &sensor_dev_attr_temp1_input.dev_attr.attr, 1230 NULL, 1231 }; 1232 ATTRIBUTE_GROUPS(ds3231_hwmon); 1233 1234 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1235 { 1236 struct device *dev; 1237 1238 if (ds1307->type != ds_3231) 1239 return; 1240 1241 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1242 ds1307, 1243 ds3231_hwmon_groups); 1244 if (IS_ERR(dev)) { 1245 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1246 PTR_ERR(dev)); 1247 } 1248 } 1249 1250 #else 1251 1252 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1253 { 1254 } 1255 1256 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ 1257 1258 /*----------------------------------------------------------------------*/ 1259 1260 /* 1261 * Square-wave output support for DS3231 1262 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1263 */ 1264 #ifdef CONFIG_COMMON_CLK 1265 1266 enum { 1267 DS3231_CLK_SQW = 0, 1268 DS3231_CLK_32KHZ, 1269 }; 1270 1271 #define clk_sqw_to_ds1307(clk) \ 1272 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1273 #define clk_32khz_to_ds1307(clk) \ 1274 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1275 1276 static int ds3231_clk_sqw_rates[] = { 1277 1, 1278 1024, 1279 4096, 1280 8192, 1281 }; 1282 1283 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1284 { 1285 struct mutex *lock = &ds1307->rtc->ops_lock; 1286 int ret; 1287 1288 mutex_lock(lock); 1289 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1290 mask, value); 1291 mutex_unlock(lock); 1292 1293 return ret; 1294 } 1295 1296 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1297 unsigned long parent_rate) 1298 { 1299 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1300 int control, ret; 1301 int rate_sel = 0; 1302 1303 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1304 if (ret) 1305 return ret; 1306 if (control & DS1337_BIT_RS1) 1307 rate_sel += 1; 1308 if (control & DS1337_BIT_RS2) 1309 rate_sel += 2; 1310 1311 return ds3231_clk_sqw_rates[rate_sel]; 1312 } 1313 1314 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, 1315 unsigned long *prate) 1316 { 1317 int i; 1318 1319 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1320 if (ds3231_clk_sqw_rates[i] <= rate) 1321 return ds3231_clk_sqw_rates[i]; 1322 } 1323 1324 return 0; 1325 } 1326 1327 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1328 unsigned long parent_rate) 1329 { 1330 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1331 int control = 0; 1332 int rate_sel; 1333 1334 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1335 rate_sel++) { 1336 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1337 break; 1338 } 1339 1340 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1341 return -EINVAL; 1342 1343 if (rate_sel & 1) 1344 control |= DS1337_BIT_RS1; 1345 if (rate_sel & 2) 1346 control |= DS1337_BIT_RS2; 1347 1348 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1349 control); 1350 } 1351 1352 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1353 { 1354 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1355 1356 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1357 } 1358 1359 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1360 { 1361 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1362 1363 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1364 } 1365 1366 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1367 { 1368 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1369 int control, ret; 1370 1371 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1372 if (ret) 1373 return ret; 1374 1375 return !(control & DS1337_BIT_INTCN); 1376 } 1377 1378 static const struct clk_ops ds3231_clk_sqw_ops = { 1379 .prepare = ds3231_clk_sqw_prepare, 1380 .unprepare = ds3231_clk_sqw_unprepare, 1381 .is_prepared = ds3231_clk_sqw_is_prepared, 1382 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1383 .round_rate = ds3231_clk_sqw_round_rate, 1384 .set_rate = ds3231_clk_sqw_set_rate, 1385 }; 1386 1387 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1388 unsigned long parent_rate) 1389 { 1390 return 32768; 1391 } 1392 1393 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1394 { 1395 struct mutex *lock = &ds1307->rtc->ops_lock; 1396 int ret; 1397 1398 mutex_lock(lock); 1399 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1400 DS3231_BIT_EN32KHZ, 1401 enable ? DS3231_BIT_EN32KHZ : 0); 1402 mutex_unlock(lock); 1403 1404 return ret; 1405 } 1406 1407 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1408 { 1409 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1410 1411 return ds3231_clk_32khz_control(ds1307, true); 1412 } 1413 1414 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1415 { 1416 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1417 1418 ds3231_clk_32khz_control(ds1307, false); 1419 } 1420 1421 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1422 { 1423 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1424 int status, ret; 1425 1426 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1427 if (ret) 1428 return ret; 1429 1430 return !!(status & DS3231_BIT_EN32KHZ); 1431 } 1432 1433 static const struct clk_ops ds3231_clk_32khz_ops = { 1434 .prepare = ds3231_clk_32khz_prepare, 1435 .unprepare = ds3231_clk_32khz_unprepare, 1436 .is_prepared = ds3231_clk_32khz_is_prepared, 1437 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1438 }; 1439 1440 static struct clk_init_data ds3231_clks_init[] = { 1441 [DS3231_CLK_SQW] = { 1442 .name = "ds3231_clk_sqw", 1443 .ops = &ds3231_clk_sqw_ops, 1444 }, 1445 [DS3231_CLK_32KHZ] = { 1446 .name = "ds3231_clk_32khz", 1447 .ops = &ds3231_clk_32khz_ops, 1448 }, 1449 }; 1450 1451 static int ds3231_clks_register(struct ds1307 *ds1307) 1452 { 1453 struct device_node *node = ds1307->dev->of_node; 1454 struct clk_onecell_data *onecell; 1455 int i; 1456 1457 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1458 if (!onecell) 1459 return -ENOMEM; 1460 1461 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1462 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1463 sizeof(onecell->clks[0]), GFP_KERNEL); 1464 if (!onecell->clks) 1465 return -ENOMEM; 1466 1467 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1468 struct clk_init_data init = ds3231_clks_init[i]; 1469 1470 /* 1471 * Interrupt signal due to alarm conditions and square-wave 1472 * output share same pin, so don't initialize both. 1473 */ 1474 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags)) 1475 continue; 1476 1477 /* optional override of the clockname */ 1478 of_property_read_string_index(node, "clock-output-names", i, 1479 &init.name); 1480 ds1307->clks[i].init = &init; 1481 1482 onecell->clks[i] = devm_clk_register(ds1307->dev, 1483 &ds1307->clks[i]); 1484 if (IS_ERR(onecell->clks[i])) 1485 return PTR_ERR(onecell->clks[i]); 1486 } 1487 1488 if (!node) 1489 return 0; 1490 1491 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1492 1493 return 0; 1494 } 1495 1496 static void ds1307_clks_register(struct ds1307 *ds1307) 1497 { 1498 int ret; 1499 1500 if (ds1307->type != ds_3231) 1501 return; 1502 1503 ret = ds3231_clks_register(ds1307); 1504 if (ret) { 1505 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1506 ret); 1507 } 1508 } 1509 1510 #else 1511 1512 static void ds1307_clks_register(struct ds1307 *ds1307) 1513 { 1514 } 1515 1516 #endif /* CONFIG_COMMON_CLK */ 1517 1518 static const struct regmap_config regmap_config = { 1519 .reg_bits = 8, 1520 .val_bits = 8, 1521 }; 1522 1523 static int ds1307_probe(struct i2c_client *client, 1524 const struct i2c_device_id *id) 1525 { 1526 struct ds1307 *ds1307; 1527 int err = -ENODEV; 1528 int tmp; 1529 const struct chip_desc *chip; 1530 bool want_irq; 1531 bool ds1307_can_wakeup_device = false; 1532 unsigned char regs[8]; 1533 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1534 u8 trickle_charger_setup = 0; 1535 1536 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1537 if (!ds1307) 1538 return -ENOMEM; 1539 1540 dev_set_drvdata(&client->dev, ds1307); 1541 ds1307->dev = &client->dev; 1542 ds1307->name = client->name; 1543 1544 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1545 if (IS_ERR(ds1307->regmap)) { 1546 dev_err(ds1307->dev, "regmap allocation failed\n"); 1547 return PTR_ERR(ds1307->regmap); 1548 } 1549 1550 i2c_set_clientdata(client, ds1307); 1551 1552 if (client->dev.of_node) { 1553 ds1307->type = (enum ds_type) 1554 of_device_get_match_data(&client->dev); 1555 chip = &chips[ds1307->type]; 1556 } else if (id) { 1557 chip = &chips[id->driver_data]; 1558 ds1307->type = id->driver_data; 1559 } else { 1560 const struct acpi_device_id *acpi_id; 1561 1562 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids), 1563 ds1307->dev); 1564 if (!acpi_id) 1565 return -ENODEV; 1566 chip = &chips[acpi_id->driver_data]; 1567 ds1307->type = acpi_id->driver_data; 1568 } 1569 1570 want_irq = client->irq > 0 && chip->alarm; 1571 1572 if (!pdata) 1573 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1574 else if (pdata->trickle_charger_setup) 1575 trickle_charger_setup = pdata->trickle_charger_setup; 1576 1577 if (trickle_charger_setup && chip->trickle_charger_reg) { 1578 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 1579 dev_dbg(ds1307->dev, 1580 "writing trickle charger info 0x%x to 0x%x\n", 1581 trickle_charger_setup, chip->trickle_charger_reg); 1582 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1583 trickle_charger_setup); 1584 } 1585 1586 #ifdef CONFIG_OF 1587 /* 1588 * For devices with no IRQ directly connected to the SoC, the RTC chip 1589 * can be forced as a wakeup source by stating that explicitly in 1590 * the device's .dts file using the "wakeup-source" boolean property. 1591 * If the "wakeup-source" property is set, don't request an IRQ. 1592 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1593 * if supported by the RTC. 1594 */ 1595 if (chip->alarm && of_property_read_bool(client->dev.of_node, 1596 "wakeup-source")) 1597 ds1307_can_wakeup_device = true; 1598 #endif 1599 1600 switch (ds1307->type) { 1601 case ds_1337: 1602 case ds_1339: 1603 case ds_1341: 1604 case ds_3231: 1605 /* get registers that the "rtc" read below won't read... */ 1606 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1607 regs, 2); 1608 if (err) { 1609 dev_dbg(ds1307->dev, "read error %d\n", err); 1610 goto exit; 1611 } 1612 1613 /* oscillator off? turn it on, so clock can tick. */ 1614 if (regs[0] & DS1337_BIT_nEOSC) 1615 regs[0] &= ~DS1337_BIT_nEOSC; 1616 1617 /* 1618 * Using IRQ or defined as wakeup-source? 1619 * Disable the square wave and both alarms. 1620 * For some variants, be sure alarms can trigger when we're 1621 * running on Vbackup (BBSQI/BBSQW) 1622 */ 1623 if (want_irq || ds1307_can_wakeup_device) { 1624 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1625 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); 1626 } 1627 1628 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1629 regs[0]); 1630 1631 /* oscillator fault? clear flag, and warn */ 1632 if (regs[1] & DS1337_BIT_OSF) { 1633 regmap_write(ds1307->regmap, DS1337_REG_STATUS, 1634 regs[1] & ~DS1337_BIT_OSF); 1635 dev_warn(ds1307->dev, "SET TIME!\n"); 1636 } 1637 break; 1638 1639 case rx_8025: 1640 err = regmap_bulk_read(ds1307->regmap, 1641 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1642 if (err) { 1643 dev_dbg(ds1307->dev, "read error %d\n", err); 1644 goto exit; 1645 } 1646 1647 /* oscillator off? turn it on, so clock can tick. */ 1648 if (!(regs[1] & RX8025_BIT_XST)) { 1649 regs[1] |= RX8025_BIT_XST; 1650 regmap_write(ds1307->regmap, 1651 RX8025_REG_CTRL2 << 4 | 0x08, 1652 regs[1]); 1653 dev_warn(ds1307->dev, 1654 "oscillator stop detected - SET TIME!\n"); 1655 } 1656 1657 if (regs[1] & RX8025_BIT_PON) { 1658 regs[1] &= ~RX8025_BIT_PON; 1659 regmap_write(ds1307->regmap, 1660 RX8025_REG_CTRL2 << 4 | 0x08, 1661 regs[1]); 1662 dev_warn(ds1307->dev, "power-on detected\n"); 1663 } 1664 1665 if (regs[1] & RX8025_BIT_VDET) { 1666 regs[1] &= ~RX8025_BIT_VDET; 1667 regmap_write(ds1307->regmap, 1668 RX8025_REG_CTRL2 << 4 | 0x08, 1669 regs[1]); 1670 dev_warn(ds1307->dev, "voltage drop detected\n"); 1671 } 1672 1673 /* make sure we are running in 24hour mode */ 1674 if (!(regs[0] & RX8025_BIT_2412)) { 1675 u8 hour; 1676 1677 /* switch to 24 hour mode */ 1678 regmap_write(ds1307->regmap, 1679 RX8025_REG_CTRL1 << 4 | 0x08, 1680 regs[0] | RX8025_BIT_2412); 1681 1682 err = regmap_bulk_read(ds1307->regmap, 1683 RX8025_REG_CTRL1 << 4 | 0x08, 1684 regs, 2); 1685 if (err) { 1686 dev_dbg(ds1307->dev, "read error %d\n", err); 1687 goto exit; 1688 } 1689 1690 /* correct hour */ 1691 hour = bcd2bin(regs[DS1307_REG_HOUR]); 1692 if (hour == 12) 1693 hour = 0; 1694 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1695 hour += 12; 1696 1697 regmap_write(ds1307->regmap, 1698 DS1307_REG_HOUR << 4 | 0x08, hour); 1699 } 1700 break; 1701 default: 1702 break; 1703 } 1704 1705 read_rtc: 1706 /* read RTC registers */ 1707 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 1708 sizeof(regs)); 1709 if (err) { 1710 dev_dbg(ds1307->dev, "read error %d\n", err); 1711 goto exit; 1712 } 1713 1714 /* 1715 * minimal sanity checking; some chips (like DS1340) don't 1716 * specify the extra bits as must-be-zero, but there are 1717 * still a few values that are clearly out-of-range. 1718 */ 1719 tmp = regs[DS1307_REG_SECS]; 1720 switch (ds1307->type) { 1721 case ds_1307: 1722 case m41t0: 1723 case m41t00: 1724 case m41t11: 1725 /* clock halted? turn it on, so clock can tick. */ 1726 if (tmp & DS1307_BIT_CH) { 1727 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1728 dev_warn(ds1307->dev, "SET TIME!\n"); 1729 goto read_rtc; 1730 } 1731 break; 1732 case ds_1308: 1733 case ds_1338: 1734 /* clock halted? turn it on, so clock can tick. */ 1735 if (tmp & DS1307_BIT_CH) 1736 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1737 1738 /* oscillator fault? clear flag, and warn */ 1739 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { 1740 regmap_write(ds1307->regmap, DS1307_REG_CONTROL, 1741 regs[DS1307_REG_CONTROL] & 1742 ~DS1338_BIT_OSF); 1743 dev_warn(ds1307->dev, "SET TIME!\n"); 1744 goto read_rtc; 1745 } 1746 break; 1747 case ds_1340: 1748 /* clock halted? turn it on, so clock can tick. */ 1749 if (tmp & DS1340_BIT_nEOSC) 1750 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1751 1752 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 1753 if (err) { 1754 dev_dbg(ds1307->dev, "read error %d\n", err); 1755 goto exit; 1756 } 1757 1758 /* oscillator fault? clear flag, and warn */ 1759 if (tmp & DS1340_BIT_OSF) { 1760 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0); 1761 dev_warn(ds1307->dev, "SET TIME!\n"); 1762 } 1763 break; 1764 case mcp794xx: 1765 /* make sure that the backup battery is enabled */ 1766 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 1767 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 1768 regs[DS1307_REG_WDAY] | 1769 MCP794XX_BIT_VBATEN); 1770 } 1771 1772 /* clock halted? turn it on, so clock can tick. */ 1773 if (!(tmp & MCP794XX_BIT_ST)) { 1774 regmap_write(ds1307->regmap, DS1307_REG_SECS, 1775 MCP794XX_BIT_ST); 1776 dev_warn(ds1307->dev, "SET TIME!\n"); 1777 goto read_rtc; 1778 } 1779 1780 break; 1781 default: 1782 break; 1783 } 1784 1785 tmp = regs[DS1307_REG_HOUR]; 1786 switch (ds1307->type) { 1787 case ds_1340: 1788 case m41t0: 1789 case m41t00: 1790 case m41t11: 1791 /* 1792 * NOTE: ignores century bits; fix before deploying 1793 * systems that will run through year 2100. 1794 */ 1795 break; 1796 case rx_8025: 1797 break; 1798 default: 1799 if (!(tmp & DS1307_BIT_12HR)) 1800 break; 1801 1802 /* 1803 * Be sure we're in 24 hour mode. Multi-master systems 1804 * take note... 1805 */ 1806 tmp = bcd2bin(tmp & 0x1f); 1807 if (tmp == 12) 1808 tmp = 0; 1809 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1810 tmp += 12; 1811 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 1812 bin2bcd(tmp)); 1813 } 1814 1815 if (want_irq || ds1307_can_wakeup_device) { 1816 device_set_wakeup_capable(ds1307->dev, true); 1817 set_bit(HAS_ALARM, &ds1307->flags); 1818 } 1819 1820 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 1821 if (IS_ERR(ds1307->rtc)) 1822 return PTR_ERR(ds1307->rtc); 1823 1824 if (ds1307_can_wakeup_device && !want_irq) { 1825 dev_info(ds1307->dev, 1826 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 1827 /* We cannot support UIE mode if we do not have an IRQ line */ 1828 ds1307->rtc->uie_unsupported = 1; 1829 } 1830 1831 if (want_irq) { 1832 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 1833 chip->irq_handler ?: ds1307_irq, 1834 IRQF_SHARED | IRQF_ONESHOT, 1835 ds1307->name, ds1307); 1836 if (err) { 1837 client->irq = 0; 1838 device_set_wakeup_capable(ds1307->dev, false); 1839 clear_bit(HAS_ALARM, &ds1307->flags); 1840 dev_err(ds1307->dev, "unable to request IRQ!\n"); 1841 } else { 1842 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 1843 } 1844 } 1845 1846 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 1847 err = ds1307_add_frequency_test(ds1307); 1848 if (err) 1849 return err; 1850 1851 err = rtc_register_device(ds1307->rtc); 1852 if (err) 1853 return err; 1854 1855 if (chip->nvram_size) { 1856 struct nvmem_config nvmem_cfg = { 1857 .name = "ds1307_nvram", 1858 .word_size = 1, 1859 .stride = 1, 1860 .size = chip->nvram_size, 1861 .reg_read = ds1307_nvram_read, 1862 .reg_write = ds1307_nvram_write, 1863 .priv = ds1307, 1864 }; 1865 1866 ds1307->rtc->nvram_old_abi = true; 1867 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 1868 } 1869 1870 ds1307_hwmon_register(ds1307); 1871 ds1307_clks_register(ds1307); 1872 1873 return 0; 1874 1875 exit: 1876 return err; 1877 } 1878 1879 static struct i2c_driver ds1307_driver = { 1880 .driver = { 1881 .name = "rtc-ds1307", 1882 .of_match_table = of_match_ptr(ds1307_of_match), 1883 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids), 1884 }, 1885 .probe = ds1307_probe, 1886 .id_table = ds1307_id, 1887 }; 1888 1889 module_i2c_driver(ds1307_driver); 1890 1891 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 1892 MODULE_LICENSE("GPL"); 1893