1 /* 2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 3 * 4 * Copyright (C) 2005 James Chapman (ds1337 core) 5 * Copyright (C) 2006 David Brownell 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/acpi.h> 15 #include <linux/bcd.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/rtc/ds1307.h> 21 #include <linux/rtc.h> 22 #include <linux/slab.h> 23 #include <linux/string.h> 24 #include <linux/hwmon.h> 25 #include <linux/hwmon-sysfs.h> 26 #include <linux/clk-provider.h> 27 #include <linux/regmap.h> 28 29 /* 30 * We can't determine type by probing, but if we expect pre-Linux code 31 * to have set the chip up as a clock (turning on the oscillator and 32 * setting the date and time), Linux can ignore the non-clock features. 33 * That's a natural job for a factory or repair bench. 34 */ 35 enum ds_type { 36 ds_1307, 37 ds_1308, 38 ds_1337, 39 ds_1338, 40 ds_1339, 41 ds_1340, 42 ds_1341, 43 ds_1388, 44 ds_3231, 45 m41t0, 46 m41t00, 47 m41t11, 48 mcp794xx, 49 rx_8025, 50 rx_8130, 51 last_ds_type /* always last */ 52 /* rs5c372 too? different address... */ 53 }; 54 55 /* RTC registers don't differ much, except for the century flag */ 56 #define DS1307_REG_SECS 0x00 /* 00-59 */ 57 # define DS1307_BIT_CH 0x80 58 # define DS1340_BIT_nEOSC 0x80 59 # define MCP794XX_BIT_ST 0x80 60 #define DS1307_REG_MIN 0x01 /* 00-59 */ 61 # define M41T0_BIT_OF 0x80 62 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 63 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 64 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 65 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 66 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 67 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 68 # define MCP794XX_BIT_VBATEN 0x08 69 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 70 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 71 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 72 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 73 74 /* 75 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 76 * start at 7, and they differ a LOT. Only control and status matter for 77 * basic RTC date and time functionality; be careful using them. 78 */ 79 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 80 # define DS1307_BIT_OUT 0x80 81 # define DS1338_BIT_OSF 0x20 82 # define DS1307_BIT_SQWE 0x10 83 # define DS1307_BIT_RS1 0x02 84 # define DS1307_BIT_RS0 0x01 85 #define DS1337_REG_CONTROL 0x0e 86 # define DS1337_BIT_nEOSC 0x80 87 # define DS1339_BIT_BBSQI 0x20 88 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 89 # define DS1337_BIT_RS2 0x10 90 # define DS1337_BIT_RS1 0x08 91 # define DS1337_BIT_INTCN 0x04 92 # define DS1337_BIT_A2IE 0x02 93 # define DS1337_BIT_A1IE 0x01 94 #define DS1340_REG_CONTROL 0x07 95 # define DS1340_BIT_OUT 0x80 96 # define DS1340_BIT_FT 0x40 97 # define DS1340_BIT_CALIB_SIGN 0x20 98 # define DS1340_M_CALIBRATION 0x1f 99 #define DS1340_REG_FLAG 0x09 100 # define DS1340_BIT_OSF 0x80 101 #define DS1337_REG_STATUS 0x0f 102 # define DS1337_BIT_OSF 0x80 103 # define DS3231_BIT_EN32KHZ 0x08 104 # define DS1337_BIT_A2I 0x02 105 # define DS1337_BIT_A1I 0x01 106 #define DS1339_REG_ALARM1_SECS 0x07 107 108 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 109 110 #define RX8025_REG_CTRL1 0x0e 111 # define RX8025_BIT_2412 0x20 112 #define RX8025_REG_CTRL2 0x0f 113 # define RX8025_BIT_PON 0x10 114 # define RX8025_BIT_VDET 0x40 115 # define RX8025_BIT_XST 0x20 116 117 #define M41TXX_REG_CONTROL 0x07 118 # define M41TXX_BIT_OUT BIT(7) 119 # define M41TXX_BIT_FT BIT(6) 120 # define M41TXX_BIT_CALIB_SIGN BIT(5) 121 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 122 123 /* negative offset step is -2.034ppm */ 124 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 125 /* positive offset step is +4.068ppm */ 126 #define M41TXX_POS_OFFSET_STEP_PPB 4068 127 /* Min and max values supported with 'offset' interface by M41TXX */ 128 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 129 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 130 131 struct ds1307 { 132 enum ds_type type; 133 unsigned long flags; 134 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ 135 #define HAS_ALARM 1 /* bit 1 == irq claimed */ 136 struct device *dev; 137 struct regmap *regmap; 138 const char *name; 139 struct rtc_device *rtc; 140 #ifdef CONFIG_COMMON_CLK 141 struct clk_hw clks[2]; 142 #endif 143 }; 144 145 struct chip_desc { 146 unsigned alarm:1; 147 u16 nvram_offset; 148 u16 nvram_size; 149 u8 offset; /* register's offset */ 150 u8 century_reg; 151 u8 century_enable_bit; 152 u8 century_bit; 153 u8 bbsqi_bit; 154 irq_handler_t irq_handler; 155 const struct rtc_class_ops *rtc_ops; 156 u16 trickle_charger_reg; 157 u8 (*do_trickle_setup)(struct ds1307 *, u32, 158 bool); 159 }; 160 161 static int ds1307_get_time(struct device *dev, struct rtc_time *t); 162 static int ds1307_set_time(struct device *dev, struct rtc_time *t); 163 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t); 164 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t); 165 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled); 166 static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode); 167 static irqreturn_t rx8130_irq(int irq, void *dev_id); 168 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t); 169 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t); 170 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled); 171 static irqreturn_t mcp794xx_irq(int irq, void *dev_id); 172 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t); 173 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t); 174 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled); 175 static int m41txx_rtc_read_offset(struct device *dev, long *offset); 176 static int m41txx_rtc_set_offset(struct device *dev, long offset); 177 178 static const struct rtc_class_ops rx8130_rtc_ops = { 179 .read_time = ds1307_get_time, 180 .set_time = ds1307_set_time, 181 .read_alarm = rx8130_read_alarm, 182 .set_alarm = rx8130_set_alarm, 183 .alarm_irq_enable = rx8130_alarm_irq_enable, 184 }; 185 186 static const struct rtc_class_ops mcp794xx_rtc_ops = { 187 .read_time = ds1307_get_time, 188 .set_time = ds1307_set_time, 189 .read_alarm = mcp794xx_read_alarm, 190 .set_alarm = mcp794xx_set_alarm, 191 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 192 }; 193 194 static const struct rtc_class_ops m41txx_rtc_ops = { 195 .read_time = ds1307_get_time, 196 .set_time = ds1307_set_time, 197 .read_alarm = ds1337_read_alarm, 198 .set_alarm = ds1337_set_alarm, 199 .alarm_irq_enable = ds1307_alarm_irq_enable, 200 .read_offset = m41txx_rtc_read_offset, 201 .set_offset = m41txx_rtc_set_offset, 202 }; 203 204 static const struct chip_desc chips[last_ds_type] = { 205 [ds_1307] = { 206 .nvram_offset = 8, 207 .nvram_size = 56, 208 }, 209 [ds_1308] = { 210 .nvram_offset = 8, 211 .nvram_size = 56, 212 }, 213 [ds_1337] = { 214 .alarm = 1, 215 .century_reg = DS1307_REG_MONTH, 216 .century_bit = DS1337_BIT_CENTURY, 217 }, 218 [ds_1338] = { 219 .nvram_offset = 8, 220 .nvram_size = 56, 221 }, 222 [ds_1339] = { 223 .alarm = 1, 224 .century_reg = DS1307_REG_MONTH, 225 .century_bit = DS1337_BIT_CENTURY, 226 .bbsqi_bit = DS1339_BIT_BBSQI, 227 .trickle_charger_reg = 0x10, 228 .do_trickle_setup = &do_trickle_setup_ds1339, 229 }, 230 [ds_1340] = { 231 .century_reg = DS1307_REG_HOUR, 232 .century_enable_bit = DS1340_BIT_CENTURY_EN, 233 .century_bit = DS1340_BIT_CENTURY, 234 .do_trickle_setup = &do_trickle_setup_ds1339, 235 .trickle_charger_reg = 0x08, 236 }, 237 [ds_1341] = { 238 .century_reg = DS1307_REG_MONTH, 239 .century_bit = DS1337_BIT_CENTURY, 240 }, 241 [ds_1388] = { 242 .offset = 1, 243 .trickle_charger_reg = 0x0a, 244 }, 245 [ds_3231] = { 246 .alarm = 1, 247 .century_reg = DS1307_REG_MONTH, 248 .century_bit = DS1337_BIT_CENTURY, 249 .bbsqi_bit = DS3231_BIT_BBSQW, 250 }, 251 [rx_8130] = { 252 .alarm = 1, 253 /* this is battery backed SRAM */ 254 .nvram_offset = 0x20, 255 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 256 .offset = 0x10, 257 .irq_handler = rx8130_irq, 258 .rtc_ops = &rx8130_rtc_ops, 259 }, 260 [m41t0] = { 261 .rtc_ops = &m41txx_rtc_ops, 262 }, 263 [m41t00] = { 264 .rtc_ops = &m41txx_rtc_ops, 265 }, 266 [m41t11] = { 267 /* this is battery backed SRAM */ 268 .nvram_offset = 8, 269 .nvram_size = 56, 270 .rtc_ops = &m41txx_rtc_ops, 271 }, 272 [mcp794xx] = { 273 .alarm = 1, 274 /* this is battery backed SRAM */ 275 .nvram_offset = 0x20, 276 .nvram_size = 0x40, 277 .irq_handler = mcp794xx_irq, 278 .rtc_ops = &mcp794xx_rtc_ops, 279 }, 280 }; 281 282 static const struct i2c_device_id ds1307_id[] = { 283 { "ds1307", ds_1307 }, 284 { "ds1308", ds_1308 }, 285 { "ds1337", ds_1337 }, 286 { "ds1338", ds_1338 }, 287 { "ds1339", ds_1339 }, 288 { "ds1388", ds_1388 }, 289 { "ds1340", ds_1340 }, 290 { "ds1341", ds_1341 }, 291 { "ds3231", ds_3231 }, 292 { "m41t0", m41t0 }, 293 { "m41t00", m41t00 }, 294 { "m41t11", m41t11 }, 295 { "mcp7940x", mcp794xx }, 296 { "mcp7941x", mcp794xx }, 297 { "pt7c4338", ds_1307 }, 298 { "rx8025", rx_8025 }, 299 { "isl12057", ds_1337 }, 300 { "rx8130", rx_8130 }, 301 { } 302 }; 303 MODULE_DEVICE_TABLE(i2c, ds1307_id); 304 305 #ifdef CONFIG_OF 306 static const struct of_device_id ds1307_of_match[] = { 307 { 308 .compatible = "dallas,ds1307", 309 .data = (void *)ds_1307 310 }, 311 { 312 .compatible = "dallas,ds1308", 313 .data = (void *)ds_1308 314 }, 315 { 316 .compatible = "dallas,ds1337", 317 .data = (void *)ds_1337 318 }, 319 { 320 .compatible = "dallas,ds1338", 321 .data = (void *)ds_1338 322 }, 323 { 324 .compatible = "dallas,ds1339", 325 .data = (void *)ds_1339 326 }, 327 { 328 .compatible = "dallas,ds1388", 329 .data = (void *)ds_1388 330 }, 331 { 332 .compatible = "dallas,ds1340", 333 .data = (void *)ds_1340 334 }, 335 { 336 .compatible = "dallas,ds1341", 337 .data = (void *)ds_1341 338 }, 339 { 340 .compatible = "maxim,ds3231", 341 .data = (void *)ds_3231 342 }, 343 { 344 .compatible = "st,m41t0", 345 .data = (void *)m41t0 346 }, 347 { 348 .compatible = "st,m41t00", 349 .data = (void *)m41t00 350 }, 351 { 352 .compatible = "st,m41t11", 353 .data = (void *)m41t11 354 }, 355 { 356 .compatible = "microchip,mcp7940x", 357 .data = (void *)mcp794xx 358 }, 359 { 360 .compatible = "microchip,mcp7941x", 361 .data = (void *)mcp794xx 362 }, 363 { 364 .compatible = "pericom,pt7c4338", 365 .data = (void *)ds_1307 366 }, 367 { 368 .compatible = "epson,rx8025", 369 .data = (void *)rx_8025 370 }, 371 { 372 .compatible = "isil,isl12057", 373 .data = (void *)ds_1337 374 }, 375 { 376 .compatible = "epson,rx8130", 377 .data = (void *)rx_8130 378 }, 379 { } 380 }; 381 MODULE_DEVICE_TABLE(of, ds1307_of_match); 382 #endif 383 384 #ifdef CONFIG_ACPI 385 static const struct acpi_device_id ds1307_acpi_ids[] = { 386 { .id = "DS1307", .driver_data = ds_1307 }, 387 { .id = "DS1308", .driver_data = ds_1308 }, 388 { .id = "DS1337", .driver_data = ds_1337 }, 389 { .id = "DS1338", .driver_data = ds_1338 }, 390 { .id = "DS1339", .driver_data = ds_1339 }, 391 { .id = "DS1388", .driver_data = ds_1388 }, 392 { .id = "DS1340", .driver_data = ds_1340 }, 393 { .id = "DS1341", .driver_data = ds_1341 }, 394 { .id = "DS3231", .driver_data = ds_3231 }, 395 { .id = "M41T0", .driver_data = m41t0 }, 396 { .id = "M41T00", .driver_data = m41t00 }, 397 { .id = "M41T11", .driver_data = m41t11 }, 398 { .id = "MCP7940X", .driver_data = mcp794xx }, 399 { .id = "MCP7941X", .driver_data = mcp794xx }, 400 { .id = "PT7C4338", .driver_data = ds_1307 }, 401 { .id = "RX8025", .driver_data = rx_8025 }, 402 { .id = "ISL12057", .driver_data = ds_1337 }, 403 { .id = "RX8130", .driver_data = rx_8130 }, 404 { } 405 }; 406 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); 407 #endif 408 409 /* 410 * The ds1337 and ds1339 both have two alarms, but we only use the first 411 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 412 * signal; ds1339 chips have only one alarm signal. 413 */ 414 static irqreturn_t ds1307_irq(int irq, void *dev_id) 415 { 416 struct ds1307 *ds1307 = dev_id; 417 struct mutex *lock = &ds1307->rtc->ops_lock; 418 int stat, ret; 419 420 mutex_lock(lock); 421 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 422 if (ret) 423 goto out; 424 425 if (stat & DS1337_BIT_A1I) { 426 stat &= ~DS1337_BIT_A1I; 427 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 428 429 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 430 DS1337_BIT_A1IE, 0); 431 if (ret) 432 goto out; 433 434 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 435 } 436 437 out: 438 mutex_unlock(lock); 439 440 return IRQ_HANDLED; 441 } 442 443 /*----------------------------------------------------------------------*/ 444 445 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 446 { 447 struct ds1307 *ds1307 = dev_get_drvdata(dev); 448 int tmp, ret; 449 const struct chip_desc *chip = &chips[ds1307->type]; 450 u8 regs[7]; 451 452 /* read the RTC date and time registers all at once */ 453 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 454 sizeof(regs)); 455 if (ret) { 456 dev_err(dev, "%s error %d\n", "read", ret); 457 return ret; 458 } 459 460 dev_dbg(dev, "%s: %7ph\n", "read", regs); 461 462 /* if oscillator fail bit is set, no data can be trusted */ 463 if (ds1307->type == m41t0 && 464 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 465 dev_warn_once(dev, "oscillator failed, set time!\n"); 466 return -EINVAL; 467 } 468 469 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 470 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 471 tmp = regs[DS1307_REG_HOUR] & 0x3f; 472 t->tm_hour = bcd2bin(tmp); 473 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 474 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 475 tmp = regs[DS1307_REG_MONTH] & 0x1f; 476 t->tm_mon = bcd2bin(tmp) - 1; 477 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 478 479 if (regs[chip->century_reg] & chip->century_bit && 480 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 481 t->tm_year += 100; 482 483 dev_dbg(dev, "%s secs=%d, mins=%d, " 484 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 485 "read", t->tm_sec, t->tm_min, 486 t->tm_hour, t->tm_mday, 487 t->tm_mon, t->tm_year, t->tm_wday); 488 489 return 0; 490 } 491 492 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 493 { 494 struct ds1307 *ds1307 = dev_get_drvdata(dev); 495 const struct chip_desc *chip = &chips[ds1307->type]; 496 int result; 497 int tmp; 498 u8 regs[7]; 499 500 dev_dbg(dev, "%s secs=%d, mins=%d, " 501 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 502 "write", t->tm_sec, t->tm_min, 503 t->tm_hour, t->tm_mday, 504 t->tm_mon, t->tm_year, t->tm_wday); 505 506 if (t->tm_year < 100) 507 return -EINVAL; 508 509 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 510 if (t->tm_year > (chip->century_bit ? 299 : 199)) 511 return -EINVAL; 512 #else 513 if (t->tm_year > 199) 514 return -EINVAL; 515 #endif 516 517 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 518 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 519 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 520 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 521 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 522 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 523 524 /* assume 20YY not 19YY */ 525 tmp = t->tm_year - 100; 526 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 527 528 if (chip->century_enable_bit) 529 regs[chip->century_reg] |= chip->century_enable_bit; 530 if (t->tm_year > 199 && chip->century_bit) 531 regs[chip->century_reg] |= chip->century_bit; 532 533 if (ds1307->type == mcp794xx) { 534 /* 535 * these bits were cleared when preparing the date/time 536 * values and need to be set again before writing the 537 * regsfer out to the device. 538 */ 539 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 540 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 541 } 542 543 dev_dbg(dev, "%s: %7ph\n", "write", regs); 544 545 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 546 sizeof(regs)); 547 if (result) { 548 dev_err(dev, "%s error %d\n", "write", result); 549 return result; 550 } 551 return 0; 552 } 553 554 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 555 { 556 struct ds1307 *ds1307 = dev_get_drvdata(dev); 557 int ret; 558 u8 regs[9]; 559 560 if (!test_bit(HAS_ALARM, &ds1307->flags)) 561 return -EINVAL; 562 563 /* read all ALARM1, ALARM2, and status registers at once */ 564 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 565 regs, sizeof(regs)); 566 if (ret) { 567 dev_err(dev, "%s error %d\n", "alarm read", ret); 568 return ret; 569 } 570 571 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 572 ®s[0], ®s[4], ®s[7]); 573 574 /* 575 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 576 * and that all four fields are checked matches 577 */ 578 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 579 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 580 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 581 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 582 583 /* ... and status */ 584 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 585 t->pending = !!(regs[8] & DS1337_BIT_A1I); 586 587 dev_dbg(dev, "%s secs=%d, mins=%d, " 588 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 589 "alarm read", t->time.tm_sec, t->time.tm_min, 590 t->time.tm_hour, t->time.tm_mday, 591 t->enabled, t->pending); 592 593 return 0; 594 } 595 596 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 597 { 598 struct ds1307 *ds1307 = dev_get_drvdata(dev); 599 unsigned char regs[9]; 600 u8 control, status; 601 int ret; 602 603 if (!test_bit(HAS_ALARM, &ds1307->flags)) 604 return -EINVAL; 605 606 dev_dbg(dev, "%s secs=%d, mins=%d, " 607 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 608 "alarm set", t->time.tm_sec, t->time.tm_min, 609 t->time.tm_hour, t->time.tm_mday, 610 t->enabled, t->pending); 611 612 /* read current status of both alarms and the chip */ 613 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 614 sizeof(regs)); 615 if (ret) { 616 dev_err(dev, "%s error %d\n", "alarm write", ret); 617 return ret; 618 } 619 control = regs[7]; 620 status = regs[8]; 621 622 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 623 ®s[0], ®s[4], control, status); 624 625 /* set ALARM1, using 24 hour and day-of-month modes */ 626 regs[0] = bin2bcd(t->time.tm_sec); 627 regs[1] = bin2bcd(t->time.tm_min); 628 regs[2] = bin2bcd(t->time.tm_hour); 629 regs[3] = bin2bcd(t->time.tm_mday); 630 631 /* set ALARM2 to non-garbage */ 632 regs[4] = 0; 633 regs[5] = 0; 634 regs[6] = 0; 635 636 /* disable alarms */ 637 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 638 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 639 640 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 641 sizeof(regs)); 642 if (ret) { 643 dev_err(dev, "can't set alarm time\n"); 644 return ret; 645 } 646 647 /* optionally enable ALARM1 */ 648 if (t->enabled) { 649 dev_dbg(dev, "alarm IRQ armed\n"); 650 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 651 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 652 } 653 654 return 0; 655 } 656 657 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 658 { 659 struct ds1307 *ds1307 = dev_get_drvdata(dev); 660 661 if (!test_bit(HAS_ALARM, &ds1307->flags)) 662 return -ENOTTY; 663 664 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 665 DS1337_BIT_A1IE, 666 enabled ? DS1337_BIT_A1IE : 0); 667 } 668 669 static const struct rtc_class_ops ds13xx_rtc_ops = { 670 .read_time = ds1307_get_time, 671 .set_time = ds1307_set_time, 672 .read_alarm = ds1337_read_alarm, 673 .set_alarm = ds1337_set_alarm, 674 .alarm_irq_enable = ds1307_alarm_irq_enable, 675 }; 676 677 /*----------------------------------------------------------------------*/ 678 679 /* 680 * Alarm support for rx8130 devices. 681 */ 682 683 #define RX8130_REG_ALARM_MIN 0x07 684 #define RX8130_REG_ALARM_HOUR 0x08 685 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x09 686 #define RX8130_REG_EXTENSION 0x0c 687 #define RX8130_REG_EXTENSION_WADA BIT(3) 688 #define RX8130_REG_FLAG 0x0d 689 #define RX8130_REG_FLAG_AF BIT(3) 690 #define RX8130_REG_CONTROL0 0x0e 691 #define RX8130_REG_CONTROL0_AIE BIT(3) 692 693 static irqreturn_t rx8130_irq(int irq, void *dev_id) 694 { 695 struct ds1307 *ds1307 = dev_id; 696 struct mutex *lock = &ds1307->rtc->ops_lock; 697 u8 ctl[3]; 698 int ret; 699 700 mutex_lock(lock); 701 702 /* Read control registers. */ 703 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 704 sizeof(ctl)); 705 if (ret < 0) 706 goto out; 707 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 708 goto out; 709 ctl[1] &= ~RX8130_REG_FLAG_AF; 710 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 711 712 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 713 sizeof(ctl)); 714 if (ret < 0) 715 goto out; 716 717 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 718 719 out: 720 mutex_unlock(lock); 721 722 return IRQ_HANDLED; 723 } 724 725 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 726 { 727 struct ds1307 *ds1307 = dev_get_drvdata(dev); 728 u8 ald[3], ctl[3]; 729 int ret; 730 731 if (!test_bit(HAS_ALARM, &ds1307->flags)) 732 return -EINVAL; 733 734 /* Read alarm registers. */ 735 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 736 sizeof(ald)); 737 if (ret < 0) 738 return ret; 739 740 /* Read control registers. */ 741 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 742 sizeof(ctl)); 743 if (ret < 0) 744 return ret; 745 746 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 747 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 748 749 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 750 t->time.tm_sec = -1; 751 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 752 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 753 t->time.tm_wday = -1; 754 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 755 t->time.tm_mon = -1; 756 t->time.tm_year = -1; 757 t->time.tm_yday = -1; 758 t->time.tm_isdst = -1; 759 760 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 761 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 762 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 763 764 return 0; 765 } 766 767 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 768 { 769 struct ds1307 *ds1307 = dev_get_drvdata(dev); 770 u8 ald[3], ctl[3]; 771 int ret; 772 773 if (!test_bit(HAS_ALARM, &ds1307->flags)) 774 return -EINVAL; 775 776 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 777 "enabled=%d pending=%d\n", __func__, 778 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 779 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 780 t->enabled, t->pending); 781 782 /* Read control registers. */ 783 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 784 sizeof(ctl)); 785 if (ret < 0) 786 return ret; 787 788 ctl[0] &= ~RX8130_REG_EXTENSION_WADA; 789 ctl[1] |= RX8130_REG_FLAG_AF; 790 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 791 792 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 793 sizeof(ctl)); 794 if (ret < 0) 795 return ret; 796 797 /* Hardware alarm precision is 1 minute! */ 798 ald[0] = bin2bcd(t->time.tm_min); 799 ald[1] = bin2bcd(t->time.tm_hour); 800 ald[2] = bin2bcd(t->time.tm_mday); 801 802 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 803 sizeof(ald)); 804 if (ret < 0) 805 return ret; 806 807 if (!t->enabled) 808 return 0; 809 810 ctl[2] |= RX8130_REG_CONTROL0_AIE; 811 812 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 813 sizeof(ctl)); 814 } 815 816 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 817 { 818 struct ds1307 *ds1307 = dev_get_drvdata(dev); 819 int ret, reg; 820 821 if (!test_bit(HAS_ALARM, &ds1307->flags)) 822 return -EINVAL; 823 824 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 825 if (ret < 0) 826 return ret; 827 828 if (enabled) 829 reg |= RX8130_REG_CONTROL0_AIE; 830 else 831 reg &= ~RX8130_REG_CONTROL0_AIE; 832 833 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 834 } 835 836 /*----------------------------------------------------------------------*/ 837 838 /* 839 * Alarm support for mcp794xx devices. 840 */ 841 842 #define MCP794XX_REG_CONTROL 0x07 843 # define MCP794XX_BIT_ALM0_EN 0x10 844 # define MCP794XX_BIT_ALM1_EN 0x20 845 #define MCP794XX_REG_ALARM0_BASE 0x0a 846 #define MCP794XX_REG_ALARM0_CTRL 0x0d 847 #define MCP794XX_REG_ALARM1_BASE 0x11 848 #define MCP794XX_REG_ALARM1_CTRL 0x14 849 # define MCP794XX_BIT_ALMX_IF BIT(3) 850 # define MCP794XX_BIT_ALMX_C0 BIT(4) 851 # define MCP794XX_BIT_ALMX_C1 BIT(5) 852 # define MCP794XX_BIT_ALMX_C2 BIT(6) 853 # define MCP794XX_BIT_ALMX_POL BIT(7) 854 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 855 MCP794XX_BIT_ALMX_C1 | \ 856 MCP794XX_BIT_ALMX_C2) 857 858 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 859 { 860 struct ds1307 *ds1307 = dev_id; 861 struct mutex *lock = &ds1307->rtc->ops_lock; 862 int reg, ret; 863 864 mutex_lock(lock); 865 866 /* Check and clear alarm 0 interrupt flag. */ 867 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 868 if (ret) 869 goto out; 870 if (!(reg & MCP794XX_BIT_ALMX_IF)) 871 goto out; 872 reg &= ~MCP794XX_BIT_ALMX_IF; 873 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 874 if (ret) 875 goto out; 876 877 /* Disable alarm 0. */ 878 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 879 MCP794XX_BIT_ALM0_EN, 0); 880 if (ret) 881 goto out; 882 883 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 884 885 out: 886 mutex_unlock(lock); 887 888 return IRQ_HANDLED; 889 } 890 891 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 892 { 893 struct ds1307 *ds1307 = dev_get_drvdata(dev); 894 u8 regs[10]; 895 int ret; 896 897 if (!test_bit(HAS_ALARM, &ds1307->flags)) 898 return -EINVAL; 899 900 /* Read control and alarm 0 registers. */ 901 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 902 sizeof(regs)); 903 if (ret) 904 return ret; 905 906 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 907 908 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 909 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 910 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 911 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 912 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 913 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 914 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 915 t->time.tm_year = -1; 916 t->time.tm_yday = -1; 917 t->time.tm_isdst = -1; 918 919 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 920 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 921 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 922 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 923 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 924 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 925 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 926 927 return 0; 928 } 929 930 /* 931 * We may have a random RTC weekday, therefore calculate alarm weekday based 932 * on current weekday we read from the RTC timekeeping regs 933 */ 934 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 935 { 936 struct rtc_time tm_now; 937 int days_now, days_alarm, ret; 938 939 ret = ds1307_get_time(dev, &tm_now); 940 if (ret) 941 return ret; 942 943 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 944 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 945 946 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 947 } 948 949 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 950 { 951 struct ds1307 *ds1307 = dev_get_drvdata(dev); 952 unsigned char regs[10]; 953 int wday, ret; 954 955 if (!test_bit(HAS_ALARM, &ds1307->flags)) 956 return -EINVAL; 957 958 wday = mcp794xx_alm_weekday(dev, &t->time); 959 if (wday < 0) 960 return wday; 961 962 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 963 "enabled=%d pending=%d\n", __func__, 964 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 965 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 966 t->enabled, t->pending); 967 968 /* Read control and alarm 0 registers. */ 969 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 970 sizeof(regs)); 971 if (ret) 972 return ret; 973 974 /* Set alarm 0, using 24-hour and day-of-month modes. */ 975 regs[3] = bin2bcd(t->time.tm_sec); 976 regs[4] = bin2bcd(t->time.tm_min); 977 regs[5] = bin2bcd(t->time.tm_hour); 978 regs[6] = wday; 979 regs[7] = bin2bcd(t->time.tm_mday); 980 regs[8] = bin2bcd(t->time.tm_mon + 1); 981 982 /* Clear the alarm 0 interrupt flag. */ 983 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 984 /* Set alarm match: second, minute, hour, day, date, month. */ 985 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 986 /* Disable interrupt. We will not enable until completely programmed */ 987 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 988 989 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 990 sizeof(regs)); 991 if (ret) 992 return ret; 993 994 if (!t->enabled) 995 return 0; 996 regs[0] |= MCP794XX_BIT_ALM0_EN; 997 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 998 } 999 1000 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 1001 { 1002 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1003 1004 if (!test_bit(HAS_ALARM, &ds1307->flags)) 1005 return -EINVAL; 1006 1007 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 1008 MCP794XX_BIT_ALM0_EN, 1009 enabled ? MCP794XX_BIT_ALM0_EN : 0); 1010 } 1011 1012 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 1013 { 1014 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1015 unsigned int ctrl_reg; 1016 u8 val; 1017 1018 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1019 1020 val = ctrl_reg & M41TXX_M_CALIBRATION; 1021 1022 /* check if positive */ 1023 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 1024 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 1025 else 1026 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 1027 1028 return 0; 1029 } 1030 1031 static int m41txx_rtc_set_offset(struct device *dev, long offset) 1032 { 1033 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1034 unsigned int ctrl_reg; 1035 1036 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 1037 return -ERANGE; 1038 1039 if (offset >= 0) { 1040 ctrl_reg = DIV_ROUND_CLOSEST(offset, 1041 M41TXX_POS_OFFSET_STEP_PPB); 1042 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 1043 } else { 1044 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 1045 M41TXX_NEG_OFFSET_STEP_PPB); 1046 } 1047 1048 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 1049 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 1050 ctrl_reg); 1051 } 1052 1053 static ssize_t frequency_test_store(struct device *dev, 1054 struct device_attribute *attr, 1055 const char *buf, size_t count) 1056 { 1057 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1058 bool freq_test_en; 1059 int ret; 1060 1061 ret = kstrtobool(buf, &freq_test_en); 1062 if (ret) { 1063 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1064 return ret; 1065 } 1066 1067 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1068 freq_test_en ? M41TXX_BIT_FT : 0); 1069 1070 return count; 1071 } 1072 1073 static ssize_t frequency_test_show(struct device *dev, 1074 struct device_attribute *attr, 1075 char *buf) 1076 { 1077 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1078 unsigned int ctrl_reg; 1079 1080 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1081 1082 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : 1083 "off\n"); 1084 } 1085 1086 static DEVICE_ATTR_RW(frequency_test); 1087 1088 static struct attribute *rtc_freq_test_attrs[] = { 1089 &dev_attr_frequency_test.attr, 1090 NULL, 1091 }; 1092 1093 static const struct attribute_group rtc_freq_test_attr_group = { 1094 .attrs = rtc_freq_test_attrs, 1095 }; 1096 1097 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1098 { 1099 int err; 1100 1101 switch (ds1307->type) { 1102 case m41t0: 1103 case m41t00: 1104 case m41t11: 1105 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1106 if (err) 1107 return err; 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 return 0; 1114 } 1115 1116 /*----------------------------------------------------------------------*/ 1117 1118 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1119 size_t bytes) 1120 { 1121 struct ds1307 *ds1307 = priv; 1122 const struct chip_desc *chip = &chips[ds1307->type]; 1123 1124 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1125 val, bytes); 1126 } 1127 1128 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1129 size_t bytes) 1130 { 1131 struct ds1307 *ds1307 = priv; 1132 const struct chip_desc *chip = &chips[ds1307->type]; 1133 1134 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1135 val, bytes); 1136 } 1137 1138 /*----------------------------------------------------------------------*/ 1139 1140 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, 1141 u32 ohms, bool diode) 1142 { 1143 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 1144 DS1307_TRICKLE_CHARGER_NO_DIODE; 1145 1146 switch (ohms) { 1147 case 250: 1148 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 1149 break; 1150 case 2000: 1151 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 1152 break; 1153 case 4000: 1154 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 1155 break; 1156 default: 1157 dev_warn(ds1307->dev, 1158 "Unsupported ohm value %u in dt\n", ohms); 1159 return 0; 1160 } 1161 return setup; 1162 } 1163 1164 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1165 const struct chip_desc *chip) 1166 { 1167 u32 ohms; 1168 bool diode = true; 1169 1170 if (!chip->do_trickle_setup) 1171 return 0; 1172 1173 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1174 &ohms)) 1175 return 0; 1176 1177 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable")) 1178 diode = false; 1179 1180 return chip->do_trickle_setup(ds1307, ohms, diode); 1181 } 1182 1183 /*----------------------------------------------------------------------*/ 1184 1185 #if IS_REACHABLE(CONFIG_HWMON) 1186 1187 /* 1188 * Temperature sensor support for ds3231 devices. 1189 */ 1190 1191 #define DS3231_REG_TEMPERATURE 0x11 1192 1193 /* 1194 * A user-initiated temperature conversion is not started by this function, 1195 * so the temperature is updated once every 64 seconds. 1196 */ 1197 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1198 { 1199 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1200 u8 temp_buf[2]; 1201 s16 temp; 1202 int ret; 1203 1204 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1205 temp_buf, sizeof(temp_buf)); 1206 if (ret) 1207 return ret; 1208 /* 1209 * Temperature is represented as a 10-bit code with a resolution of 1210 * 0.25 degree celsius and encoded in two's complement format. 1211 */ 1212 temp = (temp_buf[0] << 8) | temp_buf[1]; 1213 temp >>= 6; 1214 *mC = temp * 250; 1215 1216 return 0; 1217 } 1218 1219 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1220 struct device_attribute *attr, char *buf) 1221 { 1222 int ret; 1223 s32 temp; 1224 1225 ret = ds3231_hwmon_read_temp(dev, &temp); 1226 if (ret) 1227 return ret; 1228 1229 return sprintf(buf, "%d\n", temp); 1230 } 1231 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1232 NULL, 0); 1233 1234 static struct attribute *ds3231_hwmon_attrs[] = { 1235 &sensor_dev_attr_temp1_input.dev_attr.attr, 1236 NULL, 1237 }; 1238 ATTRIBUTE_GROUPS(ds3231_hwmon); 1239 1240 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1241 { 1242 struct device *dev; 1243 1244 if (ds1307->type != ds_3231) 1245 return; 1246 1247 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1248 ds1307, 1249 ds3231_hwmon_groups); 1250 if (IS_ERR(dev)) { 1251 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1252 PTR_ERR(dev)); 1253 } 1254 } 1255 1256 #else 1257 1258 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1259 { 1260 } 1261 1262 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ 1263 1264 /*----------------------------------------------------------------------*/ 1265 1266 /* 1267 * Square-wave output support for DS3231 1268 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1269 */ 1270 #ifdef CONFIG_COMMON_CLK 1271 1272 enum { 1273 DS3231_CLK_SQW = 0, 1274 DS3231_CLK_32KHZ, 1275 }; 1276 1277 #define clk_sqw_to_ds1307(clk) \ 1278 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1279 #define clk_32khz_to_ds1307(clk) \ 1280 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1281 1282 static int ds3231_clk_sqw_rates[] = { 1283 1, 1284 1024, 1285 4096, 1286 8192, 1287 }; 1288 1289 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1290 { 1291 struct mutex *lock = &ds1307->rtc->ops_lock; 1292 int ret; 1293 1294 mutex_lock(lock); 1295 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1296 mask, value); 1297 mutex_unlock(lock); 1298 1299 return ret; 1300 } 1301 1302 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1303 unsigned long parent_rate) 1304 { 1305 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1306 int control, ret; 1307 int rate_sel = 0; 1308 1309 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1310 if (ret) 1311 return ret; 1312 if (control & DS1337_BIT_RS1) 1313 rate_sel += 1; 1314 if (control & DS1337_BIT_RS2) 1315 rate_sel += 2; 1316 1317 return ds3231_clk_sqw_rates[rate_sel]; 1318 } 1319 1320 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, 1321 unsigned long *prate) 1322 { 1323 int i; 1324 1325 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1326 if (ds3231_clk_sqw_rates[i] <= rate) 1327 return ds3231_clk_sqw_rates[i]; 1328 } 1329 1330 return 0; 1331 } 1332 1333 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1334 unsigned long parent_rate) 1335 { 1336 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1337 int control = 0; 1338 int rate_sel; 1339 1340 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1341 rate_sel++) { 1342 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1343 break; 1344 } 1345 1346 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1347 return -EINVAL; 1348 1349 if (rate_sel & 1) 1350 control |= DS1337_BIT_RS1; 1351 if (rate_sel & 2) 1352 control |= DS1337_BIT_RS2; 1353 1354 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1355 control); 1356 } 1357 1358 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1359 { 1360 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1361 1362 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1363 } 1364 1365 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1366 { 1367 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1368 1369 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1370 } 1371 1372 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1373 { 1374 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1375 int control, ret; 1376 1377 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1378 if (ret) 1379 return ret; 1380 1381 return !(control & DS1337_BIT_INTCN); 1382 } 1383 1384 static const struct clk_ops ds3231_clk_sqw_ops = { 1385 .prepare = ds3231_clk_sqw_prepare, 1386 .unprepare = ds3231_clk_sqw_unprepare, 1387 .is_prepared = ds3231_clk_sqw_is_prepared, 1388 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1389 .round_rate = ds3231_clk_sqw_round_rate, 1390 .set_rate = ds3231_clk_sqw_set_rate, 1391 }; 1392 1393 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1394 unsigned long parent_rate) 1395 { 1396 return 32768; 1397 } 1398 1399 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1400 { 1401 struct mutex *lock = &ds1307->rtc->ops_lock; 1402 int ret; 1403 1404 mutex_lock(lock); 1405 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1406 DS3231_BIT_EN32KHZ, 1407 enable ? DS3231_BIT_EN32KHZ : 0); 1408 mutex_unlock(lock); 1409 1410 return ret; 1411 } 1412 1413 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1414 { 1415 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1416 1417 return ds3231_clk_32khz_control(ds1307, true); 1418 } 1419 1420 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1421 { 1422 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1423 1424 ds3231_clk_32khz_control(ds1307, false); 1425 } 1426 1427 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1428 { 1429 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1430 int status, ret; 1431 1432 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1433 if (ret) 1434 return ret; 1435 1436 return !!(status & DS3231_BIT_EN32KHZ); 1437 } 1438 1439 static const struct clk_ops ds3231_clk_32khz_ops = { 1440 .prepare = ds3231_clk_32khz_prepare, 1441 .unprepare = ds3231_clk_32khz_unprepare, 1442 .is_prepared = ds3231_clk_32khz_is_prepared, 1443 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1444 }; 1445 1446 static struct clk_init_data ds3231_clks_init[] = { 1447 [DS3231_CLK_SQW] = { 1448 .name = "ds3231_clk_sqw", 1449 .ops = &ds3231_clk_sqw_ops, 1450 }, 1451 [DS3231_CLK_32KHZ] = { 1452 .name = "ds3231_clk_32khz", 1453 .ops = &ds3231_clk_32khz_ops, 1454 }, 1455 }; 1456 1457 static int ds3231_clks_register(struct ds1307 *ds1307) 1458 { 1459 struct device_node *node = ds1307->dev->of_node; 1460 struct clk_onecell_data *onecell; 1461 int i; 1462 1463 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1464 if (!onecell) 1465 return -ENOMEM; 1466 1467 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1468 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1469 sizeof(onecell->clks[0]), GFP_KERNEL); 1470 if (!onecell->clks) 1471 return -ENOMEM; 1472 1473 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1474 struct clk_init_data init = ds3231_clks_init[i]; 1475 1476 /* 1477 * Interrupt signal due to alarm conditions and square-wave 1478 * output share same pin, so don't initialize both. 1479 */ 1480 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags)) 1481 continue; 1482 1483 /* optional override of the clockname */ 1484 of_property_read_string_index(node, "clock-output-names", i, 1485 &init.name); 1486 ds1307->clks[i].init = &init; 1487 1488 onecell->clks[i] = devm_clk_register(ds1307->dev, 1489 &ds1307->clks[i]); 1490 if (IS_ERR(onecell->clks[i])) 1491 return PTR_ERR(onecell->clks[i]); 1492 } 1493 1494 if (!node) 1495 return 0; 1496 1497 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1498 1499 return 0; 1500 } 1501 1502 static void ds1307_clks_register(struct ds1307 *ds1307) 1503 { 1504 int ret; 1505 1506 if (ds1307->type != ds_3231) 1507 return; 1508 1509 ret = ds3231_clks_register(ds1307); 1510 if (ret) { 1511 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1512 ret); 1513 } 1514 } 1515 1516 #else 1517 1518 static void ds1307_clks_register(struct ds1307 *ds1307) 1519 { 1520 } 1521 1522 #endif /* CONFIG_COMMON_CLK */ 1523 1524 static const struct regmap_config regmap_config = { 1525 .reg_bits = 8, 1526 .val_bits = 8, 1527 }; 1528 1529 static int ds1307_probe(struct i2c_client *client, 1530 const struct i2c_device_id *id) 1531 { 1532 struct ds1307 *ds1307; 1533 int err = -ENODEV; 1534 int tmp; 1535 const struct chip_desc *chip; 1536 bool want_irq; 1537 bool ds1307_can_wakeup_device = false; 1538 unsigned char regs[8]; 1539 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1540 u8 trickle_charger_setup = 0; 1541 1542 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1543 if (!ds1307) 1544 return -ENOMEM; 1545 1546 dev_set_drvdata(&client->dev, ds1307); 1547 ds1307->dev = &client->dev; 1548 ds1307->name = client->name; 1549 1550 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1551 if (IS_ERR(ds1307->regmap)) { 1552 dev_err(ds1307->dev, "regmap allocation failed\n"); 1553 return PTR_ERR(ds1307->regmap); 1554 } 1555 1556 i2c_set_clientdata(client, ds1307); 1557 1558 if (client->dev.of_node) { 1559 ds1307->type = (enum ds_type) 1560 of_device_get_match_data(&client->dev); 1561 chip = &chips[ds1307->type]; 1562 } else if (id) { 1563 chip = &chips[id->driver_data]; 1564 ds1307->type = id->driver_data; 1565 } else { 1566 const struct acpi_device_id *acpi_id; 1567 1568 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids), 1569 ds1307->dev); 1570 if (!acpi_id) 1571 return -ENODEV; 1572 chip = &chips[acpi_id->driver_data]; 1573 ds1307->type = acpi_id->driver_data; 1574 } 1575 1576 want_irq = client->irq > 0 && chip->alarm; 1577 1578 if (!pdata) 1579 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1580 else if (pdata->trickle_charger_setup) 1581 trickle_charger_setup = pdata->trickle_charger_setup; 1582 1583 if (trickle_charger_setup && chip->trickle_charger_reg) { 1584 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 1585 dev_dbg(ds1307->dev, 1586 "writing trickle charger info 0x%x to 0x%x\n", 1587 trickle_charger_setup, chip->trickle_charger_reg); 1588 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1589 trickle_charger_setup); 1590 } 1591 1592 #ifdef CONFIG_OF 1593 /* 1594 * For devices with no IRQ directly connected to the SoC, the RTC chip 1595 * can be forced as a wakeup source by stating that explicitly in 1596 * the device's .dts file using the "wakeup-source" boolean property. 1597 * If the "wakeup-source" property is set, don't request an IRQ. 1598 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1599 * if supported by the RTC. 1600 */ 1601 if (chip->alarm && of_property_read_bool(client->dev.of_node, 1602 "wakeup-source")) 1603 ds1307_can_wakeup_device = true; 1604 #endif 1605 1606 switch (ds1307->type) { 1607 case ds_1337: 1608 case ds_1339: 1609 case ds_1341: 1610 case ds_3231: 1611 /* get registers that the "rtc" read below won't read... */ 1612 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1613 regs, 2); 1614 if (err) { 1615 dev_dbg(ds1307->dev, "read error %d\n", err); 1616 goto exit; 1617 } 1618 1619 /* oscillator off? turn it on, so clock can tick. */ 1620 if (regs[0] & DS1337_BIT_nEOSC) 1621 regs[0] &= ~DS1337_BIT_nEOSC; 1622 1623 /* 1624 * Using IRQ or defined as wakeup-source? 1625 * Disable the square wave and both alarms. 1626 * For some variants, be sure alarms can trigger when we're 1627 * running on Vbackup (BBSQI/BBSQW) 1628 */ 1629 if (want_irq || ds1307_can_wakeup_device) { 1630 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1631 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); 1632 } 1633 1634 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1635 regs[0]); 1636 1637 /* oscillator fault? clear flag, and warn */ 1638 if (regs[1] & DS1337_BIT_OSF) { 1639 regmap_write(ds1307->regmap, DS1337_REG_STATUS, 1640 regs[1] & ~DS1337_BIT_OSF); 1641 dev_warn(ds1307->dev, "SET TIME!\n"); 1642 } 1643 break; 1644 1645 case rx_8025: 1646 err = regmap_bulk_read(ds1307->regmap, 1647 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1648 if (err) { 1649 dev_dbg(ds1307->dev, "read error %d\n", err); 1650 goto exit; 1651 } 1652 1653 /* oscillator off? turn it on, so clock can tick. */ 1654 if (!(regs[1] & RX8025_BIT_XST)) { 1655 regs[1] |= RX8025_BIT_XST; 1656 regmap_write(ds1307->regmap, 1657 RX8025_REG_CTRL2 << 4 | 0x08, 1658 regs[1]); 1659 dev_warn(ds1307->dev, 1660 "oscillator stop detected - SET TIME!\n"); 1661 } 1662 1663 if (regs[1] & RX8025_BIT_PON) { 1664 regs[1] &= ~RX8025_BIT_PON; 1665 regmap_write(ds1307->regmap, 1666 RX8025_REG_CTRL2 << 4 | 0x08, 1667 regs[1]); 1668 dev_warn(ds1307->dev, "power-on detected\n"); 1669 } 1670 1671 if (regs[1] & RX8025_BIT_VDET) { 1672 regs[1] &= ~RX8025_BIT_VDET; 1673 regmap_write(ds1307->regmap, 1674 RX8025_REG_CTRL2 << 4 | 0x08, 1675 regs[1]); 1676 dev_warn(ds1307->dev, "voltage drop detected\n"); 1677 } 1678 1679 /* make sure we are running in 24hour mode */ 1680 if (!(regs[0] & RX8025_BIT_2412)) { 1681 u8 hour; 1682 1683 /* switch to 24 hour mode */ 1684 regmap_write(ds1307->regmap, 1685 RX8025_REG_CTRL1 << 4 | 0x08, 1686 regs[0] | RX8025_BIT_2412); 1687 1688 err = regmap_bulk_read(ds1307->regmap, 1689 RX8025_REG_CTRL1 << 4 | 0x08, 1690 regs, 2); 1691 if (err) { 1692 dev_dbg(ds1307->dev, "read error %d\n", err); 1693 goto exit; 1694 } 1695 1696 /* correct hour */ 1697 hour = bcd2bin(regs[DS1307_REG_HOUR]); 1698 if (hour == 12) 1699 hour = 0; 1700 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1701 hour += 12; 1702 1703 regmap_write(ds1307->regmap, 1704 DS1307_REG_HOUR << 4 | 0x08, hour); 1705 } 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 read_rtc: 1712 /* read RTC registers */ 1713 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 1714 sizeof(regs)); 1715 if (err) { 1716 dev_dbg(ds1307->dev, "read error %d\n", err); 1717 goto exit; 1718 } 1719 1720 /* 1721 * minimal sanity checking; some chips (like DS1340) don't 1722 * specify the extra bits as must-be-zero, but there are 1723 * still a few values that are clearly out-of-range. 1724 */ 1725 tmp = regs[DS1307_REG_SECS]; 1726 switch (ds1307->type) { 1727 case ds_1307: 1728 case m41t0: 1729 case m41t00: 1730 case m41t11: 1731 /* clock halted? turn it on, so clock can tick. */ 1732 if (tmp & DS1307_BIT_CH) { 1733 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1734 dev_warn(ds1307->dev, "SET TIME!\n"); 1735 goto read_rtc; 1736 } 1737 break; 1738 case ds_1308: 1739 case ds_1338: 1740 /* clock halted? turn it on, so clock can tick. */ 1741 if (tmp & DS1307_BIT_CH) 1742 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1743 1744 /* oscillator fault? clear flag, and warn */ 1745 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { 1746 regmap_write(ds1307->regmap, DS1307_REG_CONTROL, 1747 regs[DS1307_REG_CONTROL] & 1748 ~DS1338_BIT_OSF); 1749 dev_warn(ds1307->dev, "SET TIME!\n"); 1750 goto read_rtc; 1751 } 1752 break; 1753 case ds_1340: 1754 /* clock halted? turn it on, so clock can tick. */ 1755 if (tmp & DS1340_BIT_nEOSC) 1756 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); 1757 1758 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 1759 if (err) { 1760 dev_dbg(ds1307->dev, "read error %d\n", err); 1761 goto exit; 1762 } 1763 1764 /* oscillator fault? clear flag, and warn */ 1765 if (tmp & DS1340_BIT_OSF) { 1766 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0); 1767 dev_warn(ds1307->dev, "SET TIME!\n"); 1768 } 1769 break; 1770 case mcp794xx: 1771 /* make sure that the backup battery is enabled */ 1772 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 1773 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 1774 regs[DS1307_REG_WDAY] | 1775 MCP794XX_BIT_VBATEN); 1776 } 1777 1778 /* clock halted? turn it on, so clock can tick. */ 1779 if (!(tmp & MCP794XX_BIT_ST)) { 1780 regmap_write(ds1307->regmap, DS1307_REG_SECS, 1781 MCP794XX_BIT_ST); 1782 dev_warn(ds1307->dev, "SET TIME!\n"); 1783 goto read_rtc; 1784 } 1785 1786 break; 1787 default: 1788 break; 1789 } 1790 1791 tmp = regs[DS1307_REG_HOUR]; 1792 switch (ds1307->type) { 1793 case ds_1340: 1794 case m41t0: 1795 case m41t00: 1796 case m41t11: 1797 /* 1798 * NOTE: ignores century bits; fix before deploying 1799 * systems that will run through year 2100. 1800 */ 1801 break; 1802 case rx_8025: 1803 break; 1804 default: 1805 if (!(tmp & DS1307_BIT_12HR)) 1806 break; 1807 1808 /* 1809 * Be sure we're in 24 hour mode. Multi-master systems 1810 * take note... 1811 */ 1812 tmp = bcd2bin(tmp & 0x1f); 1813 if (tmp == 12) 1814 tmp = 0; 1815 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1816 tmp += 12; 1817 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 1818 bin2bcd(tmp)); 1819 } 1820 1821 if (want_irq || ds1307_can_wakeup_device) { 1822 device_set_wakeup_capable(ds1307->dev, true); 1823 set_bit(HAS_ALARM, &ds1307->flags); 1824 } 1825 1826 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 1827 if (IS_ERR(ds1307->rtc)) 1828 return PTR_ERR(ds1307->rtc); 1829 1830 if (ds1307_can_wakeup_device && !want_irq) { 1831 dev_info(ds1307->dev, 1832 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 1833 /* We cannot support UIE mode if we do not have an IRQ line */ 1834 ds1307->rtc->uie_unsupported = 1; 1835 } 1836 1837 if (want_irq) { 1838 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 1839 chip->irq_handler ?: ds1307_irq, 1840 IRQF_SHARED | IRQF_ONESHOT, 1841 ds1307->name, ds1307); 1842 if (err) { 1843 client->irq = 0; 1844 device_set_wakeup_capable(ds1307->dev, false); 1845 clear_bit(HAS_ALARM, &ds1307->flags); 1846 dev_err(ds1307->dev, "unable to request IRQ!\n"); 1847 } else { 1848 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 1849 } 1850 } 1851 1852 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 1853 err = ds1307_add_frequency_test(ds1307); 1854 if (err) 1855 return err; 1856 1857 err = rtc_register_device(ds1307->rtc); 1858 if (err) 1859 return err; 1860 1861 if (chip->nvram_size) { 1862 struct nvmem_config nvmem_cfg = { 1863 .name = "ds1307_nvram", 1864 .word_size = 1, 1865 .stride = 1, 1866 .size = chip->nvram_size, 1867 .reg_read = ds1307_nvram_read, 1868 .reg_write = ds1307_nvram_write, 1869 .priv = ds1307, 1870 }; 1871 1872 ds1307->rtc->nvram_old_abi = true; 1873 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 1874 } 1875 1876 ds1307_hwmon_register(ds1307); 1877 ds1307_clks_register(ds1307); 1878 1879 return 0; 1880 1881 exit: 1882 return err; 1883 } 1884 1885 static struct i2c_driver ds1307_driver = { 1886 .driver = { 1887 .name = "rtc-ds1307", 1888 .of_match_table = of_match_ptr(ds1307_of_match), 1889 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids), 1890 }, 1891 .probe = ds1307_probe, 1892 .id_table = ds1307_id, 1893 }; 1894 1895 module_i2c_driver(ds1307_driver); 1896 1897 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 1898 MODULE_LICENSE("GPL"); 1899