1 /* 2 * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips 3 * 4 * Copyright (C) 2008 David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/bcd.h> 14 #include <linux/slab.h> 15 #include <linux/rtc.h> 16 #include <linux/workqueue.h> 17 18 #include <linux/spi/spi.h> 19 #include <linux/spi/ds1305.h> 20 #include <linux/module.h> 21 22 23 /* 24 * Registers ... mask DS1305_WRITE into register address to write, 25 * otherwise you're reading it. All non-bitmask values are BCD. 26 */ 27 #define DS1305_WRITE 0x80 28 29 30 /* RTC date/time ... the main special cases are that we: 31 * - Need fancy "hours" encoding in 12hour mode 32 * - Don't rely on the "day-of-week" field (or tm_wday) 33 * - Are a 21st-century clock (2000 <= year < 2100) 34 */ 35 #define DS1305_RTC_LEN 7 /* bytes for RTC regs */ 36 37 #define DS1305_SEC 0x00 /* register addresses */ 38 #define DS1305_MIN 0x01 39 #define DS1305_HOUR 0x02 40 # define DS1305_HR_12 0x40 /* set == 12 hr mode */ 41 # define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */ 42 #define DS1305_WDAY 0x03 43 #define DS1305_MDAY 0x04 44 #define DS1305_MON 0x05 45 #define DS1305_YEAR 0x06 46 47 48 /* The two alarms have only sec/min/hour/wday fields (ALM_LEN). 49 * DS1305_ALM_DISABLE disables a match field (some combos are bad). 50 * 51 * NOTE that since we don't use WDAY, we limit ourselves to alarms 52 * only one day into the future (vs potentially up to a week). 53 * 54 * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we 55 * don't currently support them. We'd either need to do it only when 56 * no alarm is pending (not the standard model), or to use the second 57 * alarm (implying that this is a DS1305 not DS1306, *and* that either 58 * it's wired up a second IRQ we know, or that INTCN is set) 59 */ 60 #define DS1305_ALM_LEN 4 /* bytes for ALM regs */ 61 #define DS1305_ALM_DISABLE 0x80 62 63 #define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */ 64 #define DS1305_ALM1(r) (0x0b + (r)) 65 66 67 /* three control registers */ 68 #define DS1305_CONTROL_LEN 3 /* bytes of control regs */ 69 70 #define DS1305_CONTROL 0x0f /* register addresses */ 71 # define DS1305_nEOSC 0x80 /* low enables oscillator */ 72 # define DS1305_WP 0x40 /* write protect */ 73 # define DS1305_INTCN 0x04 /* clear == only int0 used */ 74 # define DS1306_1HZ 0x04 /* enable 1Hz output */ 75 # define DS1305_AEI1 0x02 /* enable ALM1 IRQ */ 76 # define DS1305_AEI0 0x01 /* enable ALM0 IRQ */ 77 #define DS1305_STATUS 0x10 78 /* status has just AEIx bits, mirrored as IRQFx */ 79 #define DS1305_TRICKLE 0x11 80 /* trickle bits are defined in <linux/spi/ds1305.h> */ 81 82 /* a bunch of NVRAM */ 83 #define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */ 84 85 #define DS1305_NVRAM 0x20 /* register addresses */ 86 87 88 struct ds1305 { 89 struct spi_device *spi; 90 struct rtc_device *rtc; 91 92 struct work_struct work; 93 94 unsigned long flags; 95 #define FLAG_EXITING 0 96 97 bool hr12; 98 u8 ctrl[DS1305_CONTROL_LEN]; 99 }; 100 101 102 /*----------------------------------------------------------------------*/ 103 104 /* 105 * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux 106 * software (like a bootloader) which may require it. 107 */ 108 109 static unsigned bcd2hour(u8 bcd) 110 { 111 if (bcd & DS1305_HR_12) { 112 unsigned hour = 0; 113 114 bcd &= ~DS1305_HR_12; 115 if (bcd & DS1305_HR_PM) { 116 hour = 12; 117 bcd &= ~DS1305_HR_PM; 118 } 119 hour += bcd2bin(bcd); 120 return hour - 1; 121 } 122 return bcd2bin(bcd); 123 } 124 125 static u8 hour2bcd(bool hr12, int hour) 126 { 127 if (hr12) { 128 hour++; 129 if (hour <= 12) 130 return DS1305_HR_12 | bin2bcd(hour); 131 hour -= 12; 132 return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour); 133 } 134 return bin2bcd(hour); 135 } 136 137 /*----------------------------------------------------------------------*/ 138 139 /* 140 * Interface to RTC framework 141 */ 142 143 static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled) 144 { 145 struct ds1305 *ds1305 = dev_get_drvdata(dev); 146 u8 buf[2]; 147 long err = -EINVAL; 148 149 buf[0] = DS1305_WRITE | DS1305_CONTROL; 150 buf[1] = ds1305->ctrl[0]; 151 152 if (enabled) { 153 if (ds1305->ctrl[0] & DS1305_AEI0) 154 goto done; 155 buf[1] |= DS1305_AEI0; 156 } else { 157 if (!(buf[1] & DS1305_AEI0)) 158 goto done; 159 buf[1] &= ~DS1305_AEI0; 160 } 161 err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0); 162 if (err >= 0) 163 ds1305->ctrl[0] = buf[1]; 164 done: 165 return err; 166 167 } 168 169 170 /* 171 * Get/set of date and time is pretty normal. 172 */ 173 174 static int ds1305_get_time(struct device *dev, struct rtc_time *time) 175 { 176 struct ds1305 *ds1305 = dev_get_drvdata(dev); 177 u8 addr = DS1305_SEC; 178 u8 buf[DS1305_RTC_LEN]; 179 int status; 180 181 /* Use write-then-read to get all the date/time registers 182 * since dma from stack is nonportable 183 */ 184 status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr), 185 buf, sizeof(buf)); 186 if (status < 0) 187 return status; 188 189 dev_vdbg(dev, "%s: %02x %02x %02x, %02x %02x %02x %02x\n", 190 "read", buf[0], buf[1], buf[2], buf[3], 191 buf[4], buf[5], buf[6]); 192 193 /* Decode the registers */ 194 time->tm_sec = bcd2bin(buf[DS1305_SEC]); 195 time->tm_min = bcd2bin(buf[DS1305_MIN]); 196 time->tm_hour = bcd2hour(buf[DS1305_HOUR]); 197 time->tm_wday = buf[DS1305_WDAY] - 1; 198 time->tm_mday = bcd2bin(buf[DS1305_MDAY]); 199 time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1; 200 time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100; 201 202 dev_vdbg(dev, "%s secs=%d, mins=%d, " 203 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 204 "read", time->tm_sec, time->tm_min, 205 time->tm_hour, time->tm_mday, 206 time->tm_mon, time->tm_year, time->tm_wday); 207 208 /* Time may not be set */ 209 return rtc_valid_tm(time); 210 } 211 212 static int ds1305_set_time(struct device *dev, struct rtc_time *time) 213 { 214 struct ds1305 *ds1305 = dev_get_drvdata(dev); 215 u8 buf[1 + DS1305_RTC_LEN]; 216 u8 *bp = buf; 217 218 dev_vdbg(dev, "%s secs=%d, mins=%d, " 219 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 220 "write", time->tm_sec, time->tm_min, 221 time->tm_hour, time->tm_mday, 222 time->tm_mon, time->tm_year, time->tm_wday); 223 224 /* Write registers starting at the first time/date address. */ 225 *bp++ = DS1305_WRITE | DS1305_SEC; 226 227 *bp++ = bin2bcd(time->tm_sec); 228 *bp++ = bin2bcd(time->tm_min); 229 *bp++ = hour2bcd(ds1305->hr12, time->tm_hour); 230 *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1; 231 *bp++ = bin2bcd(time->tm_mday); 232 *bp++ = bin2bcd(time->tm_mon + 1); 233 *bp++ = bin2bcd(time->tm_year - 100); 234 235 dev_dbg(dev, "%s: %02x %02x %02x, %02x %02x %02x %02x\n", 236 "write", buf[1], buf[2], buf[3], 237 buf[4], buf[5], buf[6], buf[7]); 238 239 /* use write-then-read since dma from stack is nonportable */ 240 return spi_write_then_read(ds1305->spi, buf, sizeof(buf), 241 NULL, 0); 242 } 243 244 /* 245 * Get/set of alarm is a bit funky: 246 * 247 * - First there's the inherent raciness of getting the (partitioned) 248 * status of an alarm that could trigger while we're reading parts 249 * of that status. 250 * 251 * - Second there's its limited range (we could increase it a bit by 252 * relying on WDAY), which means it will easily roll over. 253 * 254 * - Third there's the choice of two alarms and alarm signals. 255 * Here we use ALM0 and expect that nINT0 (open drain) is used; 256 * that's the only real option for DS1306 runtime alarms, and is 257 * natural on DS1305. 258 * 259 * - Fourth, there's also ALM1, and a second interrupt signal: 260 * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0; 261 * + On DS1306 ALM1 only uses INT1 (an active high pulse) 262 * and it won't work when VCC1 is active. 263 * 264 * So to be most general, we should probably set both alarms to the 265 * same value, letting ALM1 be the wakeup event source on DS1306 266 * and handling several wiring options on DS1305. 267 * 268 * - Fifth, we support the polled mode (as well as possible; why not?) 269 * even when no interrupt line is wired to an IRQ. 270 */ 271 272 /* 273 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl) 274 */ 275 static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm) 276 { 277 struct ds1305 *ds1305 = dev_get_drvdata(dev); 278 struct spi_device *spi = ds1305->spi; 279 u8 addr; 280 int status; 281 u8 buf[DS1305_ALM_LEN]; 282 283 /* Refresh control register cache BEFORE reading ALM0 registers, 284 * since reading alarm registers acks any pending IRQ. That 285 * makes returning "pending" status a bit of a lie, but that bit 286 * of EFI status is at best fragile anyway (given IRQ handlers). 287 */ 288 addr = DS1305_CONTROL; 289 status = spi_write_then_read(spi, &addr, sizeof(addr), 290 ds1305->ctrl, sizeof(ds1305->ctrl)); 291 if (status < 0) 292 return status; 293 294 alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0); 295 alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0); 296 297 /* get and check ALM0 registers */ 298 addr = DS1305_ALM0(DS1305_SEC); 299 status = spi_write_then_read(spi, &addr, sizeof(addr), 300 buf, sizeof(buf)); 301 if (status < 0) 302 return status; 303 304 dev_vdbg(dev, "%s: %02x %02x %02x %02x\n", 305 "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN], 306 buf[DS1305_HOUR], buf[DS1305_WDAY]); 307 308 if ((DS1305_ALM_DISABLE & buf[DS1305_SEC]) 309 || (DS1305_ALM_DISABLE & buf[DS1305_MIN]) 310 || (DS1305_ALM_DISABLE & buf[DS1305_HOUR])) 311 return -EIO; 312 313 /* Stuff these values into alm->time and let RTC framework code 314 * fill in the rest ... and also handle rollover to tomorrow when 315 * that's needed. 316 */ 317 alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]); 318 alm->time.tm_min = bcd2bin(buf[DS1305_MIN]); 319 alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]); 320 alm->time.tm_mday = -1; 321 alm->time.tm_mon = -1; 322 alm->time.tm_year = -1; 323 /* next three fields are unused by Linux */ 324 alm->time.tm_wday = -1; 325 alm->time.tm_mday = -1; 326 alm->time.tm_isdst = -1; 327 328 return 0; 329 } 330 331 /* 332 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl) 333 */ 334 static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 335 { 336 struct ds1305 *ds1305 = dev_get_drvdata(dev); 337 struct spi_device *spi = ds1305->spi; 338 unsigned long now, later; 339 struct rtc_time tm; 340 int status; 341 u8 buf[1 + DS1305_ALM_LEN]; 342 343 /* convert desired alarm to time_t */ 344 status = rtc_tm_to_time(&alm->time, &later); 345 if (status < 0) 346 return status; 347 348 /* Read current time as time_t */ 349 status = ds1305_get_time(dev, &tm); 350 if (status < 0) 351 return status; 352 status = rtc_tm_to_time(&tm, &now); 353 if (status < 0) 354 return status; 355 356 /* make sure alarm fires within the next 24 hours */ 357 if (later <= now) 358 return -EINVAL; 359 if ((later - now) > 24 * 60 * 60) 360 return -EDOM; 361 362 /* disable alarm if needed */ 363 if (ds1305->ctrl[0] & DS1305_AEI0) { 364 ds1305->ctrl[0] &= ~DS1305_AEI0; 365 366 buf[0] = DS1305_WRITE | DS1305_CONTROL; 367 buf[1] = ds1305->ctrl[0]; 368 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0); 369 if (status < 0) 370 return status; 371 } 372 373 /* write alarm */ 374 buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC); 375 buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec); 376 buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min); 377 buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour); 378 buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE; 379 380 dev_dbg(dev, "%s: %02x %02x %02x %02x\n", 381 "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN], 382 buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]); 383 384 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); 385 if (status < 0) 386 return status; 387 388 /* enable alarm if requested */ 389 if (alm->enabled) { 390 ds1305->ctrl[0] |= DS1305_AEI0; 391 392 buf[0] = DS1305_WRITE | DS1305_CONTROL; 393 buf[1] = ds1305->ctrl[0]; 394 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0); 395 } 396 397 return status; 398 } 399 400 #ifdef CONFIG_PROC_FS 401 402 static int ds1305_proc(struct device *dev, struct seq_file *seq) 403 { 404 struct ds1305 *ds1305 = dev_get_drvdata(dev); 405 char *diodes = "no"; 406 char *resistors = ""; 407 408 /* ctrl[2] is treated as read-only; no locking needed */ 409 if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) { 410 switch (ds1305->ctrl[2] & 0x0c) { 411 case DS1305_TRICKLE_DS2: 412 diodes = "2 diodes, "; 413 break; 414 case DS1305_TRICKLE_DS1: 415 diodes = "1 diode, "; 416 break; 417 default: 418 goto done; 419 } 420 switch (ds1305->ctrl[2] & 0x03) { 421 case DS1305_TRICKLE_2K: 422 resistors = "2k Ohm"; 423 break; 424 case DS1305_TRICKLE_4K: 425 resistors = "4k Ohm"; 426 break; 427 case DS1305_TRICKLE_8K: 428 resistors = "8k Ohm"; 429 break; 430 default: 431 diodes = "no"; 432 break; 433 } 434 } 435 436 done: 437 return seq_printf(seq, 438 "trickle_charge\t: %s%s\n", 439 diodes, resistors); 440 } 441 442 #else 443 #define ds1305_proc NULL 444 #endif 445 446 static const struct rtc_class_ops ds1305_ops = { 447 .read_time = ds1305_get_time, 448 .set_time = ds1305_set_time, 449 .read_alarm = ds1305_get_alarm, 450 .set_alarm = ds1305_set_alarm, 451 .proc = ds1305_proc, 452 .alarm_irq_enable = ds1305_alarm_irq_enable, 453 }; 454 455 static void ds1305_work(struct work_struct *work) 456 { 457 struct ds1305 *ds1305 = container_of(work, struct ds1305, work); 458 struct mutex *lock = &ds1305->rtc->ops_lock; 459 struct spi_device *spi = ds1305->spi; 460 u8 buf[3]; 461 int status; 462 463 /* lock to protect ds1305->ctrl */ 464 mutex_lock(lock); 465 466 /* Disable the IRQ, and clear its status ... for now, we "know" 467 * that if more than one alarm is active, they're in sync. 468 * Note that reading ALM data registers also clears IRQ status. 469 */ 470 ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0); 471 ds1305->ctrl[1] = 0; 472 473 buf[0] = DS1305_WRITE | DS1305_CONTROL; 474 buf[1] = ds1305->ctrl[0]; 475 buf[2] = 0; 476 477 status = spi_write_then_read(spi, buf, sizeof(buf), 478 NULL, 0); 479 if (status < 0) 480 dev_dbg(&spi->dev, "clear irq --> %d\n", status); 481 482 mutex_unlock(lock); 483 484 if (!test_bit(FLAG_EXITING, &ds1305->flags)) 485 enable_irq(spi->irq); 486 487 rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF); 488 } 489 490 /* 491 * This "real" IRQ handler hands off to a workqueue mostly to allow 492 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async 493 * I/O requests in IRQ context (to clear the IRQ status). 494 */ 495 static irqreturn_t ds1305_irq(int irq, void *p) 496 { 497 struct ds1305 *ds1305 = p; 498 499 disable_irq(irq); 500 schedule_work(&ds1305->work); 501 return IRQ_HANDLED; 502 } 503 504 /*----------------------------------------------------------------------*/ 505 506 /* 507 * Interface for NVRAM 508 */ 509 510 static void msg_init(struct spi_message *m, struct spi_transfer *x, 511 u8 *addr, size_t count, char *tx, char *rx) 512 { 513 spi_message_init(m); 514 memset(x, 0, 2 * sizeof(*x)); 515 516 x->tx_buf = addr; 517 x->len = 1; 518 spi_message_add_tail(x, m); 519 520 x++; 521 522 x->tx_buf = tx; 523 x->rx_buf = rx; 524 x->len = count; 525 spi_message_add_tail(x, m); 526 } 527 528 static ssize_t 529 ds1305_nvram_read(struct file *filp, struct kobject *kobj, 530 struct bin_attribute *attr, 531 char *buf, loff_t off, size_t count) 532 { 533 struct spi_device *spi; 534 u8 addr; 535 struct spi_message m; 536 struct spi_transfer x[2]; 537 int status; 538 539 spi = container_of(kobj, struct spi_device, dev.kobj); 540 541 if (unlikely(off >= DS1305_NVRAM_LEN)) 542 return 0; 543 if (count >= DS1305_NVRAM_LEN) 544 count = DS1305_NVRAM_LEN; 545 if ((off + count) > DS1305_NVRAM_LEN) 546 count = DS1305_NVRAM_LEN - off; 547 if (unlikely(!count)) 548 return count; 549 550 addr = DS1305_NVRAM + off; 551 msg_init(&m, x, &addr, count, NULL, buf); 552 553 status = spi_sync(spi, &m); 554 if (status < 0) 555 dev_err(&spi->dev, "nvram %s error %d\n", "read", status); 556 return (status < 0) ? status : count; 557 } 558 559 static ssize_t 560 ds1305_nvram_write(struct file *filp, struct kobject *kobj, 561 struct bin_attribute *attr, 562 char *buf, loff_t off, size_t count) 563 { 564 struct spi_device *spi; 565 u8 addr; 566 struct spi_message m; 567 struct spi_transfer x[2]; 568 int status; 569 570 spi = container_of(kobj, struct spi_device, dev.kobj); 571 572 if (unlikely(off >= DS1305_NVRAM_LEN)) 573 return -EFBIG; 574 if (count >= DS1305_NVRAM_LEN) 575 count = DS1305_NVRAM_LEN; 576 if ((off + count) > DS1305_NVRAM_LEN) 577 count = DS1305_NVRAM_LEN - off; 578 if (unlikely(!count)) 579 return count; 580 581 addr = (DS1305_WRITE | DS1305_NVRAM) + off; 582 msg_init(&m, x, &addr, count, buf, NULL); 583 584 status = spi_sync(spi, &m); 585 if (status < 0) 586 dev_err(&spi->dev, "nvram %s error %d\n", "write", status); 587 return (status < 0) ? status : count; 588 } 589 590 static struct bin_attribute nvram = { 591 .attr.name = "nvram", 592 .attr.mode = S_IRUGO | S_IWUSR, 593 .read = ds1305_nvram_read, 594 .write = ds1305_nvram_write, 595 .size = DS1305_NVRAM_LEN, 596 }; 597 598 /*----------------------------------------------------------------------*/ 599 600 /* 601 * Interface to SPI stack 602 */ 603 604 static int ds1305_probe(struct spi_device *spi) 605 { 606 struct ds1305 *ds1305; 607 int status; 608 u8 addr, value; 609 struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev); 610 bool write_ctrl = false; 611 612 /* Sanity check board setup data. This may be hooked up 613 * in 3wire mode, but we don't care. Note that unless 614 * there's an inverter in place, this needs SPI_CS_HIGH! 615 */ 616 if ((spi->bits_per_word && spi->bits_per_word != 8) 617 || (spi->max_speed_hz > 2000000) 618 || !(spi->mode & SPI_CPHA)) 619 return -EINVAL; 620 621 /* set up driver data */ 622 ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL); 623 if (!ds1305) 624 return -ENOMEM; 625 ds1305->spi = spi; 626 spi_set_drvdata(spi, ds1305); 627 628 /* read and cache control registers */ 629 addr = DS1305_CONTROL; 630 status = spi_write_then_read(spi, &addr, sizeof(addr), 631 ds1305->ctrl, sizeof(ds1305->ctrl)); 632 if (status < 0) { 633 dev_dbg(&spi->dev, "can't %s, %d\n", 634 "read", status); 635 return status; 636 } 637 638 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl); 639 640 /* Sanity check register values ... partially compensating for the 641 * fact that SPI has no device handshake. A pullup on MISO would 642 * make these tests fail; but not all systems will have one. If 643 * some register is neither 0x00 nor 0xff, a chip is likely there. 644 */ 645 if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) { 646 dev_dbg(&spi->dev, "RTC chip is not present\n"); 647 return -ENODEV; 648 } 649 if (ds1305->ctrl[2] == 0) 650 dev_dbg(&spi->dev, "chip may not be present\n"); 651 652 /* enable writes if needed ... if we were paranoid it would 653 * make sense to enable them only when absolutely necessary. 654 */ 655 if (ds1305->ctrl[0] & DS1305_WP) { 656 u8 buf[2]; 657 658 ds1305->ctrl[0] &= ~DS1305_WP; 659 660 buf[0] = DS1305_WRITE | DS1305_CONTROL; 661 buf[1] = ds1305->ctrl[0]; 662 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); 663 664 dev_dbg(&spi->dev, "clear WP --> %d\n", status); 665 if (status < 0) 666 return status; 667 } 668 669 /* on DS1305, maybe start oscillator; like most low power 670 * oscillators, it may take a second to stabilize 671 */ 672 if (ds1305->ctrl[0] & DS1305_nEOSC) { 673 ds1305->ctrl[0] &= ~DS1305_nEOSC; 674 write_ctrl = true; 675 dev_warn(&spi->dev, "SET TIME!\n"); 676 } 677 678 /* ack any pending IRQs */ 679 if (ds1305->ctrl[1]) { 680 ds1305->ctrl[1] = 0; 681 write_ctrl = true; 682 } 683 684 /* this may need one-time (re)init */ 685 if (pdata) { 686 /* maybe enable trickle charge */ 687 if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) { 688 ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC 689 | pdata->trickle; 690 write_ctrl = true; 691 } 692 693 /* on DS1306, configure 1 Hz signal */ 694 if (pdata->is_ds1306) { 695 if (pdata->en_1hz) { 696 if (!(ds1305->ctrl[0] & DS1306_1HZ)) { 697 ds1305->ctrl[0] |= DS1306_1HZ; 698 write_ctrl = true; 699 } 700 } else { 701 if (ds1305->ctrl[0] & DS1306_1HZ) { 702 ds1305->ctrl[0] &= ~DS1306_1HZ; 703 write_ctrl = true; 704 } 705 } 706 } 707 } 708 709 if (write_ctrl) { 710 u8 buf[4]; 711 712 buf[0] = DS1305_WRITE | DS1305_CONTROL; 713 buf[1] = ds1305->ctrl[0]; 714 buf[2] = ds1305->ctrl[1]; 715 buf[3] = ds1305->ctrl[2]; 716 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); 717 if (status < 0) { 718 dev_dbg(&spi->dev, "can't %s, %d\n", 719 "write", status); 720 return status; 721 } 722 723 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl); 724 } 725 726 /* see if non-Linux software set up AM/PM mode */ 727 addr = DS1305_HOUR; 728 status = spi_write_then_read(spi, &addr, sizeof(addr), 729 &value, sizeof(value)); 730 if (status < 0) { 731 dev_dbg(&spi->dev, "read HOUR --> %d\n", status); 732 return status; 733 } 734 735 ds1305->hr12 = (DS1305_HR_12 & value) != 0; 736 if (ds1305->hr12) 737 dev_dbg(&spi->dev, "AM/PM\n"); 738 739 /* register RTC ... from here on, ds1305->ctrl needs locking */ 740 ds1305->rtc = devm_rtc_device_register(&spi->dev, "ds1305", 741 &ds1305_ops, THIS_MODULE); 742 if (IS_ERR(ds1305->rtc)) { 743 status = PTR_ERR(ds1305->rtc); 744 dev_dbg(&spi->dev, "register rtc --> %d\n", status); 745 return status; 746 } 747 748 /* Maybe set up alarm IRQ; be ready to handle it triggering right 749 * away. NOTE that we don't share this. The signal is active low, 750 * and we can't ack it before a SPI message delay. We temporarily 751 * disable the IRQ until it's acked, which lets us work with more 752 * IRQ trigger modes (not all IRQ controllers can do falling edge). 753 */ 754 if (spi->irq) { 755 INIT_WORK(&ds1305->work, ds1305_work); 756 status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq, 757 0, dev_name(&ds1305->rtc->dev), ds1305); 758 if (status < 0) { 759 dev_dbg(&spi->dev, "request_irq %d --> %d\n", 760 spi->irq, status); 761 return status; 762 } 763 764 device_set_wakeup_capable(&spi->dev, 1); 765 } 766 767 /* export NVRAM */ 768 status = sysfs_create_bin_file(&spi->dev.kobj, &nvram); 769 if (status < 0) { 770 dev_dbg(&spi->dev, "register nvram --> %d\n", status); 771 return status; 772 } 773 774 return 0; 775 } 776 777 static int ds1305_remove(struct spi_device *spi) 778 { 779 struct ds1305 *ds1305 = spi_get_drvdata(spi); 780 781 sysfs_remove_bin_file(&spi->dev.kobj, &nvram); 782 783 /* carefully shut down irq and workqueue, if present */ 784 if (spi->irq) { 785 set_bit(FLAG_EXITING, &ds1305->flags); 786 devm_free_irq(&spi->dev, spi->irq, ds1305); 787 cancel_work_sync(&ds1305->work); 788 } 789 790 spi_set_drvdata(spi, NULL); 791 return 0; 792 } 793 794 static struct spi_driver ds1305_driver = { 795 .driver.name = "rtc-ds1305", 796 .driver.owner = THIS_MODULE, 797 .probe = ds1305_probe, 798 .remove = ds1305_remove, 799 /* REVISIT add suspend/resume */ 800 }; 801 802 module_spi_driver(ds1305_driver); 803 804 MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips"); 805 MODULE_LICENSE("GPL"); 806 MODULE_ALIAS("spi:rtc-ds1305"); 807