1 /* 2 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver. 3 * 4 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 /* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz 12 * crystal. Counter 0, which keeps counting during sleep/powerdown, is 13 * used to count seconds since the beginning of the unix epoch. 14 * 15 * The counters must be configured and enabled by bootloader/board code; 16 * no checks as to whether they really get a proper 32.768kHz clock are 17 * made as this would take far too long. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/rtc.h> 23 #include <linux/init.h> 24 #include <linux/platform_device.h> 25 #include <linux/io.h> 26 #include <asm/mach-au1x00/au1000.h> 27 28 /* 32kHz clock enabled and detected */ 29 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) 30 31 static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm) 32 { 33 unsigned long t; 34 35 t = alchemy_rdsys(AU1000_SYS_TOYREAD); 36 37 rtc_time_to_tm(t, tm); 38 39 return rtc_valid_tm(tm); 40 } 41 42 static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm) 43 { 44 unsigned long t; 45 46 rtc_tm_to_time(tm, &t); 47 48 alchemy_wrsys(t, AU1000_SYS_TOYWRITE); 49 50 /* wait for the pending register write to succeed. This can 51 * take up to 6 seconds... 52 */ 53 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S) 54 msleep(1); 55 56 return 0; 57 } 58 59 static const struct rtc_class_ops au1xtoy_rtc_ops = { 60 .read_time = au1xtoy_rtc_read_time, 61 .set_time = au1xtoy_rtc_set_time, 62 }; 63 64 static int au1xtoy_rtc_probe(struct platform_device *pdev) 65 { 66 struct rtc_device *rtcdev; 67 unsigned long t; 68 int ret; 69 70 t = alchemy_rdsys(AU1000_SYS_CNTRCTRL); 71 if (!(t & CNTR_OK)) { 72 dev_err(&pdev->dev, "counters not working; aborting.\n"); 73 ret = -ENODEV; 74 goto out_err; 75 } 76 77 ret = -ETIMEDOUT; 78 79 /* set counter0 tickrate to 1Hz if necessary */ 80 if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) { 81 /* wait until hardware gives access to TRIM register */ 82 t = 0x00100000; 83 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t) 84 msleep(1); 85 86 if (!t) { 87 /* timed out waiting for register access; assume 88 * counters are unusable. 89 */ 90 dev_err(&pdev->dev, "timeout waiting for access\n"); 91 goto out_err; 92 } 93 94 /* set 1Hz TOY tick rate */ 95 alchemy_wrsys(32767, AU1000_SYS_TOYTRIM); 96 } 97 98 /* wait until the hardware allows writes to the counter reg */ 99 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S) 100 msleep(1); 101 102 rtcdev = devm_rtc_device_register(&pdev->dev, "rtc-au1xxx", 103 &au1xtoy_rtc_ops, THIS_MODULE); 104 if (IS_ERR(rtcdev)) { 105 ret = PTR_ERR(rtcdev); 106 goto out_err; 107 } 108 109 platform_set_drvdata(pdev, rtcdev); 110 111 return 0; 112 113 out_err: 114 return ret; 115 } 116 117 static struct platform_driver au1xrtc_driver = { 118 .driver = { 119 .name = "rtc-au1xxx", 120 }, 121 }; 122 123 module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe); 124 125 MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver"); 126 MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>"); 127 MODULE_LICENSE("GPL"); 128 MODULE_ALIAS("platform:rtc-au1xxx"); 129