1 /* 2 * "RTT as Real Time Clock" driver for AT91SAM9 SoC family 3 * 4 * (C) 2007 Michel Benoit 5 * 6 * Based on rtc-at91rm9200.c by Rick Bronson 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/interrupt.h> 16 #include <linux/ioctl.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/rtc.h> 25 #include <linux/slab.h> 26 #include <linux/suspend.h> 27 #include <linux/time.h> 28 29 /* 30 * This driver uses two configurable hardware resources that live in the 31 * AT91SAM9 backup power domain (intended to be powered at all times) 32 * to implement the Real Time Clock interfaces 33 * 34 * - A "Real-time Timer" (RTT) counts up in seconds from a base time. 35 * We can't assign the counter value (CRTV) ... but we can reset it. 36 * 37 * - One of the "General Purpose Backup Registers" (GPBRs) holds the 38 * base time, normally an offset from the beginning of the POSIX 39 * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the 40 * local timezone's offset. 41 * 42 * The RTC's value is the RTT counter plus that offset. The RTC's alarm 43 * is likewise a base (ALMV) plus that offset. 44 * 45 * Not all RTTs will be used as RTCs; some systems have multiple RTTs to 46 * choose from, or a "real" RTC module. All systems have multiple GPBR 47 * registers available, likewise usable for more than "RTC" support. 48 */ 49 50 #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ 51 #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ 52 #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ 53 #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ 54 #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ 55 56 #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ 57 #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ 58 59 #define AT91_RTT_VR 0x08 /* Real-time Value Register */ 60 #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ 61 62 #define AT91_RTT_SR 0x0c /* Real-time Status Register */ 63 #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ 64 #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ 65 66 /* 67 * We store ALARM_DISABLED in ALMV to record that no alarm is set. 68 * It's also the reset value for that field. 69 */ 70 #define ALARM_DISABLED ((u32)~0) 71 72 73 struct sam9_rtc { 74 void __iomem *rtt; 75 struct rtc_device *rtcdev; 76 u32 imr; 77 struct regmap *gpbr; 78 unsigned int gpbr_offset; 79 int irq; 80 struct clk *sclk; 81 bool suspended; 82 unsigned long events; 83 spinlock_t lock; 84 }; 85 86 #define rtt_readl(rtc, field) \ 87 readl((rtc)->rtt + AT91_RTT_ ## field) 88 #define rtt_writel(rtc, field, val) \ 89 writel((val), (rtc)->rtt + AT91_RTT_ ## field) 90 91 static inline unsigned int gpbr_readl(struct sam9_rtc *rtc) 92 { 93 unsigned int val; 94 95 regmap_read(rtc->gpbr, rtc->gpbr_offset, &val); 96 97 return val; 98 } 99 100 static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val) 101 { 102 regmap_write(rtc->gpbr, rtc->gpbr_offset, val); 103 } 104 105 /* 106 * Read current time and date in RTC 107 */ 108 static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) 109 { 110 struct sam9_rtc *rtc = dev_get_drvdata(dev); 111 u32 secs, secs2; 112 u32 offset; 113 114 /* read current time offset */ 115 offset = gpbr_readl(rtc); 116 if (offset == 0) 117 return -EILSEQ; 118 119 /* reread the counter to help sync the two clock domains */ 120 secs = rtt_readl(rtc, VR); 121 secs2 = rtt_readl(rtc, VR); 122 if (secs != secs2) 123 secs = rtt_readl(rtc, VR); 124 125 rtc_time_to_tm(offset + secs, tm); 126 127 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime", 128 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, 129 tm->tm_hour, tm->tm_min, tm->tm_sec); 130 131 return 0; 132 } 133 134 /* 135 * Set current time and date in RTC 136 */ 137 static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) 138 { 139 struct sam9_rtc *rtc = dev_get_drvdata(dev); 140 int err; 141 u32 offset, alarm, mr; 142 unsigned long secs; 143 144 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime", 145 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, 146 tm->tm_hour, tm->tm_min, tm->tm_sec); 147 148 err = rtc_tm_to_time(tm, &secs); 149 if (err != 0) 150 return err; 151 152 mr = rtt_readl(rtc, MR); 153 154 /* disable interrupts */ 155 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 156 157 /* read current time offset */ 158 offset = gpbr_readl(rtc); 159 160 /* store the new base time in a battery backup register */ 161 secs += 1; 162 gpbr_writel(rtc, secs); 163 164 /* adjust the alarm time for the new base */ 165 alarm = rtt_readl(rtc, AR); 166 if (alarm != ALARM_DISABLED) { 167 if (offset > secs) { 168 /* time jumped backwards, increase time until alarm */ 169 alarm += (offset - secs); 170 } else if ((alarm + offset) > secs) { 171 /* time jumped forwards, decrease time until alarm */ 172 alarm -= (secs - offset); 173 } else { 174 /* time jumped past the alarm, disable alarm */ 175 alarm = ALARM_DISABLED; 176 mr &= ~AT91_RTT_ALMIEN; 177 } 178 rtt_writel(rtc, AR, alarm); 179 } 180 181 /* reset the timer, and re-enable interrupts */ 182 rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST); 183 184 return 0; 185 } 186 187 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) 188 { 189 struct sam9_rtc *rtc = dev_get_drvdata(dev); 190 struct rtc_time *tm = &alrm->time; 191 u32 alarm = rtt_readl(rtc, AR); 192 u32 offset; 193 194 offset = gpbr_readl(rtc); 195 if (offset == 0) 196 return -EILSEQ; 197 198 memset(alrm, 0, sizeof(*alrm)); 199 if (alarm != ALARM_DISABLED && offset != 0) { 200 rtc_time_to_tm(offset + alarm, tm); 201 202 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm", 203 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, 204 tm->tm_hour, tm->tm_min, tm->tm_sec); 205 206 if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN) 207 alrm->enabled = 1; 208 } 209 210 return 0; 211 } 212 213 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) 214 { 215 struct sam9_rtc *rtc = dev_get_drvdata(dev); 216 struct rtc_time *tm = &alrm->time; 217 unsigned long secs; 218 u32 offset; 219 u32 mr; 220 int err; 221 222 err = rtc_tm_to_time(tm, &secs); 223 if (err != 0) 224 return err; 225 226 offset = gpbr_readl(rtc); 227 if (offset == 0) { 228 /* time is not set */ 229 return -EILSEQ; 230 } 231 mr = rtt_readl(rtc, MR); 232 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); 233 234 /* alarm in the past? finish and leave disabled */ 235 if (secs <= offset) { 236 rtt_writel(rtc, AR, ALARM_DISABLED); 237 return 0; 238 } 239 240 /* else set alarm and maybe enable it */ 241 rtt_writel(rtc, AR, secs - offset); 242 if (alrm->enabled) 243 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); 244 245 dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm", 246 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, 247 tm->tm_min, tm->tm_sec); 248 249 return 0; 250 } 251 252 static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 253 { 254 struct sam9_rtc *rtc = dev_get_drvdata(dev); 255 u32 mr = rtt_readl(rtc, MR); 256 257 dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr); 258 if (enabled) 259 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); 260 else 261 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); 262 return 0; 263 } 264 265 /* 266 * Provide additional RTC information in /proc/driver/rtc 267 */ 268 static int at91_rtc_proc(struct device *dev, struct seq_file *seq) 269 { 270 struct sam9_rtc *rtc = dev_get_drvdata(dev); 271 u32 mr = rtt_readl(rtc, MR); 272 273 seq_printf(seq, "update_IRQ\t: %s\n", 274 (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no"); 275 return 0; 276 } 277 278 static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc) 279 { 280 u32 sr, mr; 281 282 /* Shared interrupt may be for another device. Note: reading 283 * SR clears it, so we must only read it in this irq handler! 284 */ 285 mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 286 sr = rtt_readl(rtc, SR) & (mr >> 16); 287 if (!sr) 288 return IRQ_NONE; 289 290 /* alarm status */ 291 if (sr & AT91_RTT_ALMS) 292 rtc->events |= (RTC_AF | RTC_IRQF); 293 294 /* timer update/increment */ 295 if (sr & AT91_RTT_RTTINC) 296 rtc->events |= (RTC_UF | RTC_IRQF); 297 298 return IRQ_HANDLED; 299 } 300 301 static void at91_rtc_flush_events(struct sam9_rtc *rtc) 302 { 303 if (!rtc->events) 304 return; 305 306 rtc_update_irq(rtc->rtcdev, 1, rtc->events); 307 rtc->events = 0; 308 309 pr_debug("%s: num=%ld, events=0x%02lx\n", __func__, 310 rtc->events >> 8, rtc->events & 0x000000FF); 311 } 312 313 /* 314 * IRQ handler for the RTC 315 */ 316 static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc) 317 { 318 struct sam9_rtc *rtc = _rtc; 319 int ret; 320 321 spin_lock(&rtc->lock); 322 323 ret = at91_rtc_cache_events(rtc); 324 325 /* We're called in suspended state */ 326 if (rtc->suspended) { 327 /* Mask irqs coming from this peripheral */ 328 rtt_writel(rtc, MR, 329 rtt_readl(rtc, MR) & 330 ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 331 /* Trigger a system wakeup */ 332 pm_system_wakeup(); 333 } else { 334 at91_rtc_flush_events(rtc); 335 } 336 337 spin_unlock(&rtc->lock); 338 339 return ret; 340 } 341 342 static const struct rtc_class_ops at91_rtc_ops = { 343 .read_time = at91_rtc_readtime, 344 .set_time = at91_rtc_settime, 345 .read_alarm = at91_rtc_readalarm, 346 .set_alarm = at91_rtc_setalarm, 347 .proc = at91_rtc_proc, 348 .alarm_irq_enable = at91_rtc_alarm_irq_enable, 349 }; 350 351 static const struct regmap_config gpbr_regmap_config = { 352 .name = "gpbr", 353 .reg_bits = 32, 354 .val_bits = 32, 355 .reg_stride = 4, 356 }; 357 358 /* 359 * Initialize and install RTC driver 360 */ 361 static int at91_rtc_probe(struct platform_device *pdev) 362 { 363 struct resource *r; 364 struct sam9_rtc *rtc; 365 int ret, irq; 366 u32 mr; 367 unsigned int sclk_rate; 368 369 irq = platform_get_irq(pdev, 0); 370 if (irq < 0) { 371 dev_err(&pdev->dev, "failed to get interrupt resource\n"); 372 return irq; 373 } 374 375 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 376 if (!rtc) 377 return -ENOMEM; 378 379 spin_lock_init(&rtc->lock); 380 rtc->irq = irq; 381 382 /* platform setup code should have handled this; sigh */ 383 if (!device_can_wakeup(&pdev->dev)) 384 device_init_wakeup(&pdev->dev, 1); 385 386 platform_set_drvdata(pdev, rtc); 387 388 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 389 rtc->rtt = devm_ioremap_resource(&pdev->dev, r); 390 if (IS_ERR(rtc->rtt)) 391 return PTR_ERR(rtc->rtt); 392 393 if (!pdev->dev.of_node) { 394 /* 395 * TODO: Remove this code chunk when removing non DT board 396 * support. Remember to remove the gpbr_regmap_config 397 * variable too. 398 */ 399 void __iomem *gpbr; 400 401 r = platform_get_resource(pdev, IORESOURCE_MEM, 1); 402 gpbr = devm_ioremap_resource(&pdev->dev, r); 403 if (IS_ERR(gpbr)) 404 return PTR_ERR(gpbr); 405 406 rtc->gpbr = regmap_init_mmio(NULL, gpbr, 407 &gpbr_regmap_config); 408 } else { 409 struct of_phandle_args args; 410 411 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 412 "atmel,rtt-rtc-time-reg", 1, 0, 413 &args); 414 if (ret) 415 return ret; 416 417 rtc->gpbr = syscon_node_to_regmap(args.np); 418 rtc->gpbr_offset = args.args[0]; 419 } 420 421 if (IS_ERR(rtc->gpbr)) { 422 dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n"); 423 return -ENOMEM; 424 } 425 426 rtc->sclk = devm_clk_get(&pdev->dev, NULL); 427 if (IS_ERR(rtc->sclk)) 428 return PTR_ERR(rtc->sclk); 429 430 ret = clk_prepare_enable(rtc->sclk); 431 if (ret) { 432 dev_err(&pdev->dev, "Could not enable slow clock\n"); 433 return ret; 434 } 435 436 sclk_rate = clk_get_rate(rtc->sclk); 437 if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) { 438 dev_err(&pdev->dev, "Invalid slow clock rate\n"); 439 ret = -EINVAL; 440 goto err_clk; 441 } 442 443 mr = rtt_readl(rtc, MR); 444 445 /* unless RTT is counting at 1 Hz, re-initialize it */ 446 if ((mr & AT91_RTT_RTPRES) != sclk_rate) { 447 mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES); 448 gpbr_writel(rtc, 0); 449 } 450 451 /* disable all interrupts (same as on shutdown path) */ 452 mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 453 rtt_writel(rtc, MR, mr); 454 455 rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name, 456 &at91_rtc_ops, THIS_MODULE); 457 if (IS_ERR(rtc->rtcdev)) { 458 ret = PTR_ERR(rtc->rtcdev); 459 goto err_clk; 460 } 461 462 /* register irq handler after we know what name we'll use */ 463 ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt, 464 IRQF_SHARED | IRQF_COND_SUSPEND, 465 dev_name(&rtc->rtcdev->dev), rtc); 466 if (ret) { 467 dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq); 468 goto err_clk; 469 } 470 471 /* NOTE: sam9260 rev A silicon has a ROM bug which resets the 472 * RTT on at least some reboots. If you have that chip, you must 473 * initialize the time from some external source like a GPS, wall 474 * clock, discrete RTC, etc 475 */ 476 477 if (gpbr_readl(rtc) == 0) 478 dev_warn(&pdev->dev, "%s: SET TIME!\n", 479 dev_name(&rtc->rtcdev->dev)); 480 481 return 0; 482 483 err_clk: 484 clk_disable_unprepare(rtc->sclk); 485 486 return ret; 487 } 488 489 /* 490 * Disable and remove the RTC driver 491 */ 492 static int at91_rtc_remove(struct platform_device *pdev) 493 { 494 struct sam9_rtc *rtc = platform_get_drvdata(pdev); 495 u32 mr = rtt_readl(rtc, MR); 496 497 /* disable all interrupts */ 498 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 499 500 clk_disable_unprepare(rtc->sclk); 501 502 return 0; 503 } 504 505 static void at91_rtc_shutdown(struct platform_device *pdev) 506 { 507 struct sam9_rtc *rtc = platform_get_drvdata(pdev); 508 u32 mr = rtt_readl(rtc, MR); 509 510 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 511 rtt_writel(rtc, MR, mr & ~rtc->imr); 512 } 513 514 #ifdef CONFIG_PM_SLEEP 515 516 /* AT91SAM9 RTC Power management control */ 517 518 static int at91_rtc_suspend(struct device *dev) 519 { 520 struct sam9_rtc *rtc = dev_get_drvdata(dev); 521 u32 mr = rtt_readl(rtc, MR); 522 523 /* 524 * This IRQ is shared with DBGU and other hardware which isn't 525 * necessarily a wakeup event source. 526 */ 527 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 528 if (rtc->imr) { 529 if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) { 530 unsigned long flags; 531 532 enable_irq_wake(rtc->irq); 533 spin_lock_irqsave(&rtc->lock, flags); 534 rtc->suspended = true; 535 spin_unlock_irqrestore(&rtc->lock, flags); 536 /* don't let RTTINC cause wakeups */ 537 if (mr & AT91_RTT_RTTINCIEN) 538 rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN); 539 } else 540 rtt_writel(rtc, MR, mr & ~rtc->imr); 541 } 542 543 return 0; 544 } 545 546 static int at91_rtc_resume(struct device *dev) 547 { 548 struct sam9_rtc *rtc = dev_get_drvdata(dev); 549 u32 mr; 550 551 if (rtc->imr) { 552 unsigned long flags; 553 554 if (device_may_wakeup(dev)) 555 disable_irq_wake(rtc->irq); 556 mr = rtt_readl(rtc, MR); 557 rtt_writel(rtc, MR, mr | rtc->imr); 558 559 spin_lock_irqsave(&rtc->lock, flags); 560 rtc->suspended = false; 561 at91_rtc_cache_events(rtc); 562 at91_rtc_flush_events(rtc); 563 spin_unlock_irqrestore(&rtc->lock, flags); 564 } 565 566 return 0; 567 } 568 #endif 569 570 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); 571 572 #ifdef CONFIG_OF 573 static const struct of_device_id at91_rtc_dt_ids[] = { 574 { .compatible = "atmel,at91sam9260-rtt" }, 575 { /* sentinel */ } 576 }; 577 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); 578 #endif 579 580 static struct platform_driver at91_rtc_driver = { 581 .probe = at91_rtc_probe, 582 .remove = at91_rtc_remove, 583 .shutdown = at91_rtc_shutdown, 584 .driver = { 585 .name = "rtc-at91sam9", 586 .pm = &at91_rtc_pm_ops, 587 .of_match_table = of_match_ptr(at91_rtc_dt_ids), 588 }, 589 }; 590 591 module_platform_driver(at91_rtc_driver); 592 593 MODULE_AUTHOR("Michel Benoit"); 594 MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x"); 595 MODULE_LICENSE("GPL"); 596