1 /* 2 * RTC driver for the Armada 38x Marvell SoCs 3 * 4 * Copyright (C) 2015 Marvell 5 * 6 * Gregory Clement <gregory.clement@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of the 11 * License, or (at your option) any later version. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/rtc.h> 22 23 #define RTC_STATUS 0x0 24 #define RTC_STATUS_ALARM1 BIT(0) 25 #define RTC_STATUS_ALARM2 BIT(1) 26 #define RTC_IRQ1_CONF 0x4 27 #define RTC_IRQ2_CONF 0x8 28 #define RTC_IRQ_AL_EN BIT(0) 29 #define RTC_IRQ_FREQ_EN BIT(1) 30 #define RTC_IRQ_FREQ_1HZ BIT(2) 31 #define RTC_CCR 0x18 32 #define RTC_CCR_MODE BIT(15) 33 #define RTC_CONF_TEST 0x1C 34 #define RTC_NOMINAL_TIMING BIT(13) 35 36 #define RTC_TIME 0xC 37 #define RTC_ALARM1 0x10 38 #define RTC_ALARM2 0x14 39 40 /* Armada38x SoC registers */ 41 #define RTC_38X_BRIDGE_TIMING_CTL 0x0 42 #define RTC_38X_PERIOD_OFFS 0 43 #define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS) 44 #define RTC_38X_READ_DELAY_OFFS 26 45 #define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS) 46 47 /* Armada 7K/8K registers */ 48 #define RTC_8K_BRIDGE_TIMING_CTL0 0x0 49 #define RTC_8K_WRCLK_PERIOD_OFFS 0 50 #define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS) 51 #define RTC_8K_WRCLK_SETUP_OFFS 16 52 #define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS) 53 #define RTC_8K_BRIDGE_TIMING_CTL1 0x4 54 #define RTC_8K_READ_DELAY_OFFS 0 55 #define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS) 56 57 #define RTC_8K_ISR 0x10 58 #define RTC_8K_IMR 0x14 59 #define RTC_8K_ALARM2 BIT(0) 60 61 #define SOC_RTC_INTERRUPT 0x8 62 #define SOC_RTC_ALARM1 BIT(0) 63 #define SOC_RTC_ALARM2 BIT(1) 64 #define SOC_RTC_ALARM1_MASK BIT(2) 65 #define SOC_RTC_ALARM2_MASK BIT(3) 66 67 #define SAMPLE_NR 100 68 69 struct value_to_freq { 70 u32 value; 71 u8 freq; 72 }; 73 74 struct armada38x_rtc { 75 struct rtc_device *rtc_dev; 76 void __iomem *regs; 77 void __iomem *regs_soc; 78 spinlock_t lock; 79 int irq; 80 bool initialized; 81 struct value_to_freq *val_to_freq; 82 struct armada38x_rtc_data *data; 83 }; 84 85 #define ALARM1 0 86 #define ALARM2 1 87 88 #define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32)) 89 90 struct armada38x_rtc_data { 91 /* Initialize the RTC-MBUS bridge timing */ 92 void (*update_mbus_timing)(struct armada38x_rtc *rtc); 93 u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg); 94 void (*clear_isr)(struct armada38x_rtc *rtc); 95 void (*unmask_interrupt)(struct armada38x_rtc *rtc); 96 u32 alarm; 97 }; 98 99 /* 100 * According to the datasheet, the OS should wait 5us after every 101 * register write to the RTC hard macro so that the required update 102 * can occur without holding off the system bus 103 * According to errata RES-3124064, Write to any RTC register 104 * may fail. As a workaround, before writing to RTC 105 * register, issue a dummy write of 0x0 twice to RTC Status 106 * register. 107 */ 108 109 static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) 110 { 111 writel(0, rtc->regs + RTC_STATUS); 112 writel(0, rtc->regs + RTC_STATUS); 113 writel(val, rtc->regs + offset); 114 udelay(5); 115 } 116 117 /* Update RTC-MBUS bridge timing parameters */ 118 static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc) 119 { 120 u32 reg; 121 122 reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); 123 reg &= ~RTC_38X_PERIOD_MASK; 124 reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */ 125 reg &= ~RTC_38X_READ_DELAY_MASK; 126 reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */ 127 writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); 128 } 129 130 static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc) 131 { 132 u32 reg; 133 134 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); 135 reg &= ~RTC_8K_WRCLK_PERIOD_MASK; 136 reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS; 137 reg &= ~RTC_8K_WRCLK_SETUP_MASK; 138 reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS; 139 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); 140 141 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); 142 reg &= ~RTC_8K_READ_DELAY_MASK; 143 reg |= 0x3F << RTC_8K_READ_DELAY_OFFS; 144 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); 145 } 146 147 static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg) 148 { 149 return readl(rtc->regs + rtc_reg); 150 } 151 152 static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg) 153 { 154 int i, index_max = 0, max = 0; 155 156 for (i = 0; i < SAMPLE_NR; i++) { 157 rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg); 158 rtc->val_to_freq[i].freq = 0; 159 } 160 161 for (i = 0; i < SAMPLE_NR; i++) { 162 int j = 0; 163 u32 value = rtc->val_to_freq[i].value; 164 165 while (rtc->val_to_freq[j].freq) { 166 if (rtc->val_to_freq[j].value == value) { 167 rtc->val_to_freq[j].freq++; 168 break; 169 } 170 j++; 171 } 172 173 if (!rtc->val_to_freq[j].freq) { 174 rtc->val_to_freq[j].value = value; 175 rtc->val_to_freq[j].freq = 1; 176 } 177 178 if (rtc->val_to_freq[j].freq > max) { 179 index_max = j; 180 max = rtc->val_to_freq[j].freq; 181 } 182 183 /* 184 * If a value already has half of the sample this is the most 185 * frequent one and we can stop the research right now 186 */ 187 if (max > SAMPLE_NR / 2) 188 break; 189 } 190 191 return rtc->val_to_freq[index_max].value; 192 } 193 194 static void armada38x_clear_isr(struct armada38x_rtc *rtc) 195 { 196 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); 197 198 writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT); 199 } 200 201 static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc) 202 { 203 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); 204 205 writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT); 206 } 207 208 static void armada8k_clear_isr(struct armada38x_rtc *rtc) 209 { 210 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR); 211 } 212 213 static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc) 214 { 215 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR); 216 } 217 218 static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm) 219 { 220 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 221 unsigned long time, flags; 222 223 spin_lock_irqsave(&rtc->lock, flags); 224 time = rtc->data->read_rtc_reg(rtc, RTC_TIME); 225 spin_unlock_irqrestore(&rtc->lock, flags); 226 227 rtc_time64_to_tm(time, tm); 228 229 return 0; 230 } 231 232 static void armada38x_rtc_reset(struct armada38x_rtc *rtc) 233 { 234 u32 reg; 235 236 reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST); 237 /* If bits [7:0] are non-zero, assume RTC was uninitialized */ 238 if (reg & 0xff) { 239 rtc_delayed_write(0, rtc, RTC_CONF_TEST); 240 msleep(500); /* Oscillator startup time */ 241 rtc_delayed_write(0, rtc, RTC_TIME); 242 rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc, 243 RTC_STATUS); 244 rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR); 245 } 246 rtc->initialized = true; 247 } 248 249 static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm) 250 { 251 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 252 unsigned long time, flags; 253 254 time = rtc_tm_to_time64(tm); 255 256 if (!rtc->initialized) 257 armada38x_rtc_reset(rtc); 258 259 spin_lock_irqsave(&rtc->lock, flags); 260 rtc_delayed_write(time, rtc, RTC_TIME); 261 spin_unlock_irqrestore(&rtc->lock, flags); 262 263 return 0; 264 } 265 266 static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 267 { 268 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 269 unsigned long time, flags; 270 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); 271 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 272 u32 val; 273 274 spin_lock_irqsave(&rtc->lock, flags); 275 276 time = rtc->data->read_rtc_reg(rtc, reg); 277 val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN; 278 279 spin_unlock_irqrestore(&rtc->lock, flags); 280 281 alrm->enabled = val ? 1 : 0; 282 rtc_time64_to_tm(time, &alrm->time); 283 284 return 0; 285 } 286 287 static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 288 { 289 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 290 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); 291 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 292 unsigned long time, flags; 293 294 time = rtc_tm_to_time64(&alrm->time); 295 296 spin_lock_irqsave(&rtc->lock, flags); 297 298 rtc_delayed_write(time, rtc, reg); 299 300 if (alrm->enabled) { 301 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq); 302 rtc->data->unmask_interrupt(rtc); 303 } 304 305 spin_unlock_irqrestore(&rtc->lock, flags); 306 307 return 0; 308 } 309 310 static int armada38x_rtc_alarm_irq_enable(struct device *dev, 311 unsigned int enabled) 312 { 313 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 314 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 315 unsigned long flags; 316 317 spin_lock_irqsave(&rtc->lock, flags); 318 319 if (enabled) 320 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq); 321 else 322 rtc_delayed_write(0, rtc, reg_irq); 323 324 spin_unlock_irqrestore(&rtc->lock, flags); 325 326 return 0; 327 } 328 329 static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data) 330 { 331 struct armada38x_rtc *rtc = data; 332 u32 val; 333 int event = RTC_IRQF | RTC_AF; 334 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 335 336 dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq); 337 338 spin_lock(&rtc->lock); 339 340 rtc->data->clear_isr(rtc); 341 val = rtc->data->read_rtc_reg(rtc, reg_irq); 342 /* disable all the interrupts for alarm*/ 343 rtc_delayed_write(0, rtc, reg_irq); 344 /* Ack the event */ 345 rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS); 346 347 spin_unlock(&rtc->lock); 348 349 if (val & RTC_IRQ_FREQ_EN) { 350 if (val & RTC_IRQ_FREQ_1HZ) 351 event |= RTC_UF; 352 else 353 event |= RTC_PF; 354 } 355 356 rtc_update_irq(rtc->rtc_dev, 1, event); 357 358 return IRQ_HANDLED; 359 } 360 361 /* 362 * The information given in the Armada 388 functional spec is complex. 363 * They give two different formulas for calculating the offset value, 364 * but when considering "Offset" as an 8-bit signed integer, they both 365 * reduce down to (we shall rename "Offset" as "val" here): 366 * 367 * val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768 368 * 369 * Converting to time, f = 1/t: 370 * val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768 371 * 372 * => t_measured / t_ideal = val * resolution + 1 373 * 374 * "offset" in the RTC interface is defined as: 375 * t = t0 * (1 + offset * 1e-9) 376 * where t is the desired period, t0 is the measured period with a zero 377 * offset, which is t_measured above. With t0 = t_measured and t = t_ideal, 378 * offset = (t_ideal / t_measured - 1) / 1e-9 379 * 380 * => t_ideal / t_measured = offset * 1e-9 + 1 381 * 382 * so: 383 * 384 * offset * 1e-9 + 1 = 1 / (val * resolution + 1) 385 * 386 * We want "resolution" to be an integer, so resolution = R * 1e-9, giving 387 * offset = 1e18 / (val * R + 1e9) - 1e9 388 * val = (1e18 / (offset + 1e9) - 1e9) / R 389 * with a common transformation: 390 * f(x) = 1e18 / (x + 1e9) - 1e9 391 * offset = f(val * R) 392 * val = f(offset) / R 393 * 394 * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb). 395 */ 396 static long armada38x_ppb_convert(long ppb) 397 { 398 long div = ppb + 1000000000L; 399 400 return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L; 401 } 402 403 static int armada38x_rtc_read_offset(struct device *dev, long *offset) 404 { 405 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 406 unsigned long ccr, flags; 407 long ppb_cor; 408 409 spin_lock_irqsave(&rtc->lock, flags); 410 ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR); 411 spin_unlock_irqrestore(&rtc->lock, flags); 412 413 ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr; 414 /* ppb_cor + 1000000000L can never be zero */ 415 *offset = armada38x_ppb_convert(ppb_cor); 416 417 return 0; 418 } 419 420 static int armada38x_rtc_set_offset(struct device *dev, long offset) 421 { 422 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 423 unsigned long ccr = 0; 424 long ppb_cor, off; 425 426 /* 427 * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we 428 * need to clamp the input. This equates to -484270 .. 488558. 429 * Not only is this to stop out of range "off" but also to 430 * avoid the division by zero in armada38x_ppb_convert(). 431 */ 432 offset = clamp(offset, -484270L, 488558L); 433 434 ppb_cor = armada38x_ppb_convert(offset); 435 436 /* 437 * Use low update mode where possible, which gives a better 438 * resolution of correction. 439 */ 440 off = DIV_ROUND_CLOSEST(ppb_cor, 954); 441 if (off > 127 || off < -128) { 442 ccr = RTC_CCR_MODE; 443 off = DIV_ROUND_CLOSEST(ppb_cor, 3815); 444 } 445 446 /* 447 * Armada 388 requires a bit pattern in bits 14..8 depending on 448 * the sign bit: { 0, ~S, S, S, S, S, S } 449 */ 450 ccr |= (off & 0x3fff) ^ 0x2000; 451 rtc_delayed_write(ccr, rtc, RTC_CCR); 452 453 return 0; 454 } 455 456 static const struct rtc_class_ops armada38x_rtc_ops = { 457 .read_time = armada38x_rtc_read_time, 458 .set_time = armada38x_rtc_set_time, 459 .read_alarm = armada38x_rtc_read_alarm, 460 .set_alarm = armada38x_rtc_set_alarm, 461 .alarm_irq_enable = armada38x_rtc_alarm_irq_enable, 462 .read_offset = armada38x_rtc_read_offset, 463 .set_offset = armada38x_rtc_set_offset, 464 }; 465 466 static const struct rtc_class_ops armada38x_rtc_ops_noirq = { 467 .read_time = armada38x_rtc_read_time, 468 .set_time = armada38x_rtc_set_time, 469 .read_alarm = armada38x_rtc_read_alarm, 470 .read_offset = armada38x_rtc_read_offset, 471 .set_offset = armada38x_rtc_set_offset, 472 }; 473 474 static const struct armada38x_rtc_data armada38x_data = { 475 .update_mbus_timing = rtc_update_38x_mbus_timing_params, 476 .read_rtc_reg = read_rtc_register_38x_wa, 477 .clear_isr = armada38x_clear_isr, 478 .unmask_interrupt = armada38x_unmask_interrupt, 479 .alarm = ALARM1, 480 }; 481 482 static const struct armada38x_rtc_data armada8k_data = { 483 .update_mbus_timing = rtc_update_8k_mbus_timing_params, 484 .read_rtc_reg = read_rtc_register, 485 .clear_isr = armada8k_clear_isr, 486 .unmask_interrupt = armada8k_unmask_interrupt, 487 .alarm = ALARM2, 488 }; 489 490 #ifdef CONFIG_OF 491 static const struct of_device_id armada38x_rtc_of_match_table[] = { 492 { 493 .compatible = "marvell,armada-380-rtc", 494 .data = &armada38x_data, 495 }, 496 { 497 .compatible = "marvell,armada-8k-rtc", 498 .data = &armada8k_data, 499 }, 500 {} 501 }; 502 MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table); 503 #endif 504 505 static __init int armada38x_rtc_probe(struct platform_device *pdev) 506 { 507 struct resource *res; 508 struct armada38x_rtc *rtc; 509 const struct of_device_id *match; 510 int ret; 511 512 match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev); 513 if (!match) 514 return -ENODEV; 515 516 rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc), 517 GFP_KERNEL); 518 if (!rtc) 519 return -ENOMEM; 520 521 rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR, 522 sizeof(struct value_to_freq), GFP_KERNEL); 523 if (!rtc->val_to_freq) 524 return -ENOMEM; 525 526 spin_lock_init(&rtc->lock); 527 528 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc"); 529 rtc->regs = devm_ioremap_resource(&pdev->dev, res); 530 if (IS_ERR(rtc->regs)) 531 return PTR_ERR(rtc->regs); 532 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc"); 533 rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res); 534 if (IS_ERR(rtc->regs_soc)) 535 return PTR_ERR(rtc->regs_soc); 536 537 rtc->irq = platform_get_irq(pdev, 0); 538 539 if (rtc->irq < 0) { 540 dev_err(&pdev->dev, "no irq\n"); 541 return rtc->irq; 542 } 543 544 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 545 if (IS_ERR(rtc->rtc_dev)) 546 return PTR_ERR(rtc->rtc_dev); 547 548 if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq, 549 0, pdev->name, rtc) < 0) { 550 dev_warn(&pdev->dev, "Interrupt not available.\n"); 551 rtc->irq = -1; 552 } 553 platform_set_drvdata(pdev, rtc); 554 555 if (rtc->irq != -1) { 556 device_init_wakeup(&pdev->dev, 1); 557 rtc->rtc_dev->ops = &armada38x_rtc_ops; 558 } else { 559 /* 560 * If there is no interrupt available then we can't 561 * use the alarm 562 */ 563 rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq; 564 } 565 rtc->data = (struct armada38x_rtc_data *)match->data; 566 567 /* Update RTC-MBUS bridge timing parameters */ 568 rtc->data->update_mbus_timing(rtc); 569 570 rtc->rtc_dev->range_max = U32_MAX; 571 572 ret = rtc_register_device(rtc->rtc_dev); 573 if (ret) 574 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); 575 576 return ret; 577 } 578 579 #ifdef CONFIG_PM_SLEEP 580 static int armada38x_rtc_suspend(struct device *dev) 581 { 582 if (device_may_wakeup(dev)) { 583 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 584 585 return enable_irq_wake(rtc->irq); 586 } 587 588 return 0; 589 } 590 591 static int armada38x_rtc_resume(struct device *dev) 592 { 593 if (device_may_wakeup(dev)) { 594 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 595 596 /* Update RTC-MBUS bridge timing parameters */ 597 rtc->data->update_mbus_timing(rtc); 598 599 return disable_irq_wake(rtc->irq); 600 } 601 602 return 0; 603 } 604 #endif 605 606 static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops, 607 armada38x_rtc_suspend, armada38x_rtc_resume); 608 609 static struct platform_driver armada38x_rtc_driver = { 610 .driver = { 611 .name = "armada38x-rtc", 612 .pm = &armada38x_rtc_pm_ops, 613 .of_match_table = of_match_ptr(armada38x_rtc_of_match_table), 614 }, 615 }; 616 617 module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe); 618 619 MODULE_DESCRIPTION("Marvell Armada 38x RTC driver"); 620 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>"); 621 MODULE_LICENSE("GPL"); 622