1 /* 2 * RTC Driver for X-Powers AC100 3 * 4 * Copyright (c) 2016 Chen-Yu Tsai 5 * 6 * Chen-Yu Tsai <wens@csie.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 */ 17 18 #include <linux/bcd.h> 19 #include <linux/clk-provider.h> 20 #include <linux/device.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/mfd/ac100.h> 24 #include <linux/module.h> 25 #include <linux/mutex.h> 26 #include <linux/of.h> 27 #include <linux/platform_device.h> 28 #include <linux/regmap.h> 29 #include <linux/rtc.h> 30 #include <linux/types.h> 31 32 /* Control register */ 33 #define AC100_RTC_CTRL_24HOUR BIT(0) 34 35 /* Clock output register bits */ 36 #define AC100_CLKOUT_PRE_DIV_SHIFT 5 37 #define AC100_CLKOUT_PRE_DIV_WIDTH 3 38 #define AC100_CLKOUT_MUX_SHIFT 4 39 #define AC100_CLKOUT_MUX_WIDTH 1 40 #define AC100_CLKOUT_DIV_SHIFT 1 41 #define AC100_CLKOUT_DIV_WIDTH 3 42 #define AC100_CLKOUT_EN BIT(0) 43 44 /* RTC */ 45 #define AC100_RTC_SEC_MASK GENMASK(6, 0) 46 #define AC100_RTC_MIN_MASK GENMASK(6, 0) 47 #define AC100_RTC_HOU_MASK GENMASK(5, 0) 48 #define AC100_RTC_WEE_MASK GENMASK(2, 0) 49 #define AC100_RTC_DAY_MASK GENMASK(5, 0) 50 #define AC100_RTC_MON_MASK GENMASK(4, 0) 51 #define AC100_RTC_YEA_MASK GENMASK(7, 0) 52 #define AC100_RTC_YEA_LEAP BIT(15) 53 #define AC100_RTC_UPD_TRIGGER BIT(15) 54 55 /* Alarm (wall clock) */ 56 #define AC100_ALM_INT_ENABLE BIT(0) 57 58 #define AC100_ALM_SEC_MASK GENMASK(6, 0) 59 #define AC100_ALM_MIN_MASK GENMASK(6, 0) 60 #define AC100_ALM_HOU_MASK GENMASK(5, 0) 61 #define AC100_ALM_WEE_MASK GENMASK(2, 0) 62 #define AC100_ALM_DAY_MASK GENMASK(5, 0) 63 #define AC100_ALM_MON_MASK GENMASK(4, 0) 64 #define AC100_ALM_YEA_MASK GENMASK(7, 0) 65 #define AC100_ALM_ENABLE_FLAG BIT(15) 66 #define AC100_ALM_UPD_TRIGGER BIT(15) 67 68 /* 69 * The year parameter passed to the driver is usually an offset relative to 70 * the year 1900. This macro is used to convert this offset to another one 71 * relative to the minimum year allowed by the hardware. 72 * 73 * The year range is 1970 - 2069. This range is selected to match Allwinner's 74 * driver. 75 */ 76 #define AC100_YEAR_MIN 1970 77 #define AC100_YEAR_MAX 2069 78 #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900) 79 80 struct ac100_clkout { 81 struct clk_hw hw; 82 struct regmap *regmap; 83 u8 offset; 84 }; 85 86 #define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw) 87 88 #define AC100_RTC_32K_NAME "ac100-rtc-32k" 89 #define AC100_RTC_32K_RATE 32768 90 #define AC100_CLKOUT_NUM 3 91 92 static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = { 93 "ac100-cko1-rtc", 94 "ac100-cko2-rtc", 95 "ac100-cko3-rtc", 96 }; 97 98 struct ac100_rtc_dev { 99 struct rtc_device *rtc; 100 struct device *dev; 101 struct regmap *regmap; 102 int irq; 103 unsigned long alarm; 104 105 struct clk_hw *rtc_32k_clk; 106 struct ac100_clkout clks[AC100_CLKOUT_NUM]; 107 struct clk_hw_onecell_data *clk_data; 108 }; 109 110 /** 111 * Clock controls for 3 clock output pins 112 */ 113 114 static const struct clk_div_table ac100_clkout_prediv[] = { 115 { .val = 0, .div = 1 }, 116 { .val = 1, .div = 2 }, 117 { .val = 2, .div = 4 }, 118 { .val = 3, .div = 8 }, 119 { .val = 4, .div = 16 }, 120 { .val = 5, .div = 32 }, 121 { .val = 6, .div = 64 }, 122 { .val = 7, .div = 122 }, 123 { }, 124 }; 125 126 /* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */ 127 static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw, 128 unsigned long prate) 129 { 130 struct ac100_clkout *clk = to_ac100_clkout(hw); 131 unsigned int reg, div; 132 133 regmap_read(clk->regmap, clk->offset, ®); 134 135 /* Handle pre-divider first */ 136 if (prate != AC100_RTC_32K_RATE) { 137 div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & 138 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1); 139 prate = divider_recalc_rate(hw, prate, div, 140 ac100_clkout_prediv, 0, 141 AC100_CLKOUT_PRE_DIV_WIDTH); 142 } 143 144 div = (reg >> AC100_CLKOUT_DIV_SHIFT) & 145 (BIT(AC100_CLKOUT_DIV_WIDTH) - 1); 146 return divider_recalc_rate(hw, prate, div, NULL, 147 CLK_DIVIDER_POWER_OF_TWO, 148 AC100_CLKOUT_DIV_WIDTH); 149 } 150 151 static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate, 152 unsigned long prate) 153 { 154 unsigned long best_rate = 0, tmp_rate, tmp_prate; 155 int i; 156 157 if (prate == AC100_RTC_32K_RATE) 158 return divider_round_rate(hw, rate, &prate, NULL, 159 AC100_CLKOUT_DIV_WIDTH, 160 CLK_DIVIDER_POWER_OF_TWO); 161 162 for (i = 0; ac100_clkout_prediv[i].div; i++) { 163 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); 164 tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL, 165 AC100_CLKOUT_DIV_WIDTH, 166 CLK_DIVIDER_POWER_OF_TWO); 167 168 if (tmp_rate > rate) 169 continue; 170 if (rate - tmp_rate < best_rate - tmp_rate) 171 best_rate = tmp_rate; 172 } 173 174 return best_rate; 175 } 176 177 static int ac100_clkout_determine_rate(struct clk_hw *hw, 178 struct clk_rate_request *req) 179 { 180 struct clk_hw *best_parent; 181 unsigned long best = 0; 182 int i, num_parents = clk_hw_get_num_parents(hw); 183 184 for (i = 0; i < num_parents; i++) { 185 struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); 186 unsigned long tmp, prate = clk_hw_get_rate(parent); 187 188 tmp = ac100_clkout_round_rate(hw, req->rate, prate); 189 190 if (tmp > req->rate) 191 continue; 192 if (req->rate - tmp < req->rate - best) { 193 best = tmp; 194 best_parent = parent; 195 } 196 } 197 198 if (!best) 199 return -EINVAL; 200 201 req->best_parent_hw = best_parent; 202 req->best_parent_rate = best; 203 req->rate = best; 204 205 return 0; 206 } 207 208 static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate, 209 unsigned long prate) 210 { 211 struct ac100_clkout *clk = to_ac100_clkout(hw); 212 int div = 0, pre_div = 0; 213 214 do { 215 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, 216 prate, NULL, AC100_CLKOUT_DIV_WIDTH, 217 CLK_DIVIDER_POWER_OF_TWO); 218 if (div >= 0) 219 break; 220 } while (prate != AC100_RTC_32K_RATE && 221 ac100_clkout_prediv[++pre_div].div); 222 223 if (div < 0) 224 return div; 225 226 pre_div = ac100_clkout_prediv[pre_div].val; 227 228 regmap_update_bits(clk->regmap, clk->offset, 229 ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT | 230 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT, 231 (div - 1) << AC100_CLKOUT_DIV_SHIFT | 232 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT); 233 234 return 0; 235 } 236 237 static int ac100_clkout_prepare(struct clk_hw *hw) 238 { 239 struct ac100_clkout *clk = to_ac100_clkout(hw); 240 241 return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 242 AC100_CLKOUT_EN); 243 } 244 245 static void ac100_clkout_unprepare(struct clk_hw *hw) 246 { 247 struct ac100_clkout *clk = to_ac100_clkout(hw); 248 249 regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0); 250 } 251 252 static int ac100_clkout_is_prepared(struct clk_hw *hw) 253 { 254 struct ac100_clkout *clk = to_ac100_clkout(hw); 255 unsigned int reg; 256 257 regmap_read(clk->regmap, clk->offset, ®); 258 259 return reg & AC100_CLKOUT_EN; 260 } 261 262 static u8 ac100_clkout_get_parent(struct clk_hw *hw) 263 { 264 struct ac100_clkout *clk = to_ac100_clkout(hw); 265 unsigned int reg; 266 267 regmap_read(clk->regmap, clk->offset, ®); 268 269 return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1; 270 } 271 272 static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index) 273 { 274 struct ac100_clkout *clk = to_ac100_clkout(hw); 275 276 return regmap_update_bits(clk->regmap, clk->offset, 277 BIT(AC100_CLKOUT_MUX_SHIFT), 278 index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0); 279 } 280 281 static const struct clk_ops ac100_clkout_ops = { 282 .prepare = ac100_clkout_prepare, 283 .unprepare = ac100_clkout_unprepare, 284 .is_prepared = ac100_clkout_is_prepared, 285 .recalc_rate = ac100_clkout_recalc_rate, 286 .determine_rate = ac100_clkout_determine_rate, 287 .get_parent = ac100_clkout_get_parent, 288 .set_parent = ac100_clkout_set_parent, 289 .set_rate = ac100_clkout_set_rate, 290 }; 291 292 static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip) 293 { 294 struct device_node *np = chip->dev->of_node; 295 const char *parents[2] = {AC100_RTC_32K_NAME}; 296 int i, ret; 297 298 chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + 299 sizeof(*chip->clk_data->hws) * 300 AC100_CLKOUT_NUM, 301 GFP_KERNEL); 302 if (!chip->clk_data) 303 return -ENOMEM; 304 305 chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev, 306 AC100_RTC_32K_NAME, 307 NULL, 0, 308 AC100_RTC_32K_RATE); 309 if (IS_ERR(chip->rtc_32k_clk)) { 310 ret = PTR_ERR(chip->rtc_32k_clk); 311 dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n", 312 ret); 313 return ret; 314 } 315 316 parents[1] = of_clk_get_parent_name(np, 0); 317 if (!parents[1]) { 318 dev_err(chip->dev, "Failed to get ADDA 4M clock\n"); 319 return -EINVAL; 320 } 321 322 for (i = 0; i < AC100_CLKOUT_NUM; i++) { 323 struct ac100_clkout *clk = &chip->clks[i]; 324 struct clk_init_data init = { 325 .name = ac100_clkout_names[i], 326 .ops = &ac100_clkout_ops, 327 .parent_names = parents, 328 .num_parents = ARRAY_SIZE(parents), 329 .flags = 0, 330 }; 331 332 of_property_read_string_index(np, "clock-output-names", 333 i, &init.name); 334 clk->regmap = chip->regmap; 335 clk->offset = AC100_CLKOUT_CTRL1 + i; 336 clk->hw.init = &init; 337 338 ret = devm_clk_hw_register(chip->dev, &clk->hw); 339 if (ret) { 340 dev_err(chip->dev, "Failed to register clk '%s': %d\n", 341 init.name, ret); 342 goto err_unregister_rtc_32k; 343 } 344 345 chip->clk_data->hws[i] = &clk->hw; 346 } 347 348 chip->clk_data->num = i; 349 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data); 350 if (ret) 351 goto err_unregister_rtc_32k; 352 353 return 0; 354 355 err_unregister_rtc_32k: 356 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk); 357 358 return ret; 359 } 360 361 static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip) 362 { 363 of_clk_del_provider(chip->dev->of_node); 364 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk); 365 } 366 367 /** 368 * RTC related bits 369 */ 370 static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm) 371 { 372 struct ac100_rtc_dev *chip = dev_get_drvdata(dev); 373 struct regmap *regmap = chip->regmap; 374 u16 reg[7]; 375 int ret; 376 377 ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7); 378 if (ret) 379 return ret; 380 381 rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK); 382 rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK); 383 rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK); 384 rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK); 385 rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK); 386 rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1; 387 rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) + 388 AC100_YEAR_OFF; 389 390 return rtc_valid_tm(rtc_tm); 391 } 392 393 static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm) 394 { 395 struct ac100_rtc_dev *chip = dev_get_drvdata(dev); 396 struct regmap *regmap = chip->regmap; 397 int year; 398 u16 reg[8]; 399 400 /* our RTC has a limited year range... */ 401 year = rtc_tm->tm_year - AC100_YEAR_OFF; 402 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) { 403 dev_err(dev, "rtc only supports year in range %d - %d\n", 404 AC100_YEAR_MIN, AC100_YEAR_MAX); 405 return -EINVAL; 406 } 407 408 /* convert to BCD */ 409 reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK; 410 reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK; 411 reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK; 412 reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK; 413 reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK; 414 reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK; 415 reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK; 416 /* trigger write */ 417 reg[7] = AC100_RTC_UPD_TRIGGER; 418 419 /* Is it a leap year? */ 420 if (is_leap_year(year + AC100_YEAR_OFF + 1900)) 421 reg[6] |= AC100_RTC_YEA_LEAP; 422 423 return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8); 424 } 425 426 static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en) 427 { 428 struct ac100_rtc_dev *chip = dev_get_drvdata(dev); 429 struct regmap *regmap = chip->regmap; 430 unsigned int val; 431 432 val = en ? AC100_ALM_INT_ENABLE : 0; 433 434 return regmap_write(regmap, AC100_ALM_INT_ENA, val); 435 } 436 437 static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm) 438 { 439 struct ac100_rtc_dev *chip = dev_get_drvdata(dev); 440 struct regmap *regmap = chip->regmap; 441 struct rtc_time *alrm_tm = &alrm->time; 442 u16 reg[7]; 443 unsigned int val; 444 int ret; 445 446 ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val); 447 if (ret) 448 return ret; 449 450 alrm->enabled = !!(val & AC100_ALM_INT_ENABLE); 451 452 ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7); 453 if (ret) 454 return ret; 455 456 alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK); 457 alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK); 458 alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK); 459 alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK); 460 alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK); 461 alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1; 462 alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) + 463 AC100_YEAR_OFF; 464 465 return 0; 466 } 467 468 static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 469 { 470 struct ac100_rtc_dev *chip = dev_get_drvdata(dev); 471 struct regmap *regmap = chip->regmap; 472 struct rtc_time *alrm_tm = &alrm->time; 473 u16 reg[8]; 474 int year; 475 int ret; 476 477 /* our alarm has a limited year range... */ 478 year = alrm_tm->tm_year - AC100_YEAR_OFF; 479 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) { 480 dev_err(dev, "alarm only supports year in range %d - %d\n", 481 AC100_YEAR_MIN, AC100_YEAR_MAX); 482 return -EINVAL; 483 } 484 485 /* convert to BCD */ 486 reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) | 487 AC100_ALM_ENABLE_FLAG; 488 reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) | 489 AC100_ALM_ENABLE_FLAG; 490 reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) | 491 AC100_ALM_ENABLE_FLAG; 492 /* Do not enable weekday alarm */ 493 reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK; 494 reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) | 495 AC100_ALM_ENABLE_FLAG; 496 reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) | 497 AC100_ALM_ENABLE_FLAG; 498 reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) | 499 AC100_ALM_ENABLE_FLAG; 500 /* trigger write */ 501 reg[7] = AC100_ALM_UPD_TRIGGER; 502 503 ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8); 504 if (ret) 505 return ret; 506 507 return ac100_rtc_alarm_irq_enable(dev, alrm->enabled); 508 } 509 510 static irqreturn_t ac100_rtc_irq(int irq, void *data) 511 { 512 struct ac100_rtc_dev *chip = data; 513 struct regmap *regmap = chip->regmap; 514 unsigned int val = 0; 515 int ret; 516 517 mutex_lock(&chip->rtc->ops_lock); 518 519 /* read status */ 520 ret = regmap_read(regmap, AC100_ALM_INT_STA, &val); 521 if (ret) 522 goto out; 523 524 if (val & AC100_ALM_INT_ENABLE) { 525 /* signal rtc framework */ 526 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 527 528 /* clear status */ 529 ret = regmap_write(regmap, AC100_ALM_INT_STA, val); 530 if (ret) 531 goto out; 532 533 /* disable interrupt */ 534 ret = ac100_rtc_alarm_irq_enable(chip->dev, 0); 535 if (ret) 536 goto out; 537 } 538 539 out: 540 mutex_unlock(&chip->rtc->ops_lock); 541 return IRQ_HANDLED; 542 } 543 544 static const struct rtc_class_ops ac100_rtc_ops = { 545 .read_time = ac100_rtc_get_time, 546 .set_time = ac100_rtc_set_time, 547 .read_alarm = ac100_rtc_get_alarm, 548 .set_alarm = ac100_rtc_set_alarm, 549 .alarm_irq_enable = ac100_rtc_alarm_irq_enable, 550 }; 551 552 static int ac100_rtc_probe(struct platform_device *pdev) 553 { 554 struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent); 555 struct ac100_rtc_dev *chip; 556 int ret; 557 558 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 559 if (!chip) 560 return -ENOMEM; 561 562 platform_set_drvdata(pdev, chip); 563 chip->dev = &pdev->dev; 564 chip->regmap = ac100->regmap; 565 566 chip->irq = platform_get_irq(pdev, 0); 567 if (chip->irq < 0) { 568 dev_err(&pdev->dev, "No IRQ resource\n"); 569 return chip->irq; 570 } 571 572 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 573 if (IS_ERR(chip->rtc)) 574 return PTR_ERR(chip->rtc); 575 576 chip->rtc->ops = &ac100_rtc_ops; 577 578 ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL, 579 ac100_rtc_irq, 580 IRQF_SHARED | IRQF_ONESHOT, 581 dev_name(&pdev->dev), chip); 582 if (ret) { 583 dev_err(&pdev->dev, "Could not request IRQ\n"); 584 return ret; 585 } 586 587 /* always use 24 hour mode */ 588 regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR, 589 AC100_RTC_CTRL_24HOUR); 590 591 /* disable counter alarm interrupt */ 592 regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0); 593 594 /* clear counter alarm pending interrupts */ 595 regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE); 596 597 ret = ac100_rtc_register_clks(chip); 598 if (ret) 599 return ret; 600 601 ret = rtc_register_device(chip->rtc); 602 if (ret) { 603 dev_err(&pdev->dev, "unable to register device\n"); 604 return ret; 605 } 606 607 dev_info(&pdev->dev, "RTC enabled\n"); 608 609 return 0; 610 } 611 612 static int ac100_rtc_remove(struct platform_device *pdev) 613 { 614 struct ac100_rtc_dev *chip = platform_get_drvdata(pdev); 615 616 ac100_rtc_unregister_clks(chip); 617 618 return 0; 619 } 620 621 static const struct of_device_id ac100_rtc_match[] = { 622 { .compatible = "x-powers,ac100-rtc" }, 623 { }, 624 }; 625 MODULE_DEVICE_TABLE(of, ac100_rtc_match); 626 627 static struct platform_driver ac100_rtc_driver = { 628 .probe = ac100_rtc_probe, 629 .remove = ac100_rtc_remove, 630 .driver = { 631 .name = "ac100-rtc", 632 .of_match_table = of_match_ptr(ac100_rtc_match), 633 }, 634 }; 635 module_platform_driver(ac100_rtc_driver); 636 637 MODULE_DESCRIPTION("X-Powers AC100 RTC driver"); 638 MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>"); 639 MODULE_LICENSE("GPL v2"); 640