1 /* 2 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3 3 * I2C RTC / Alarm chip 4 * 5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> 6 * 7 * Detailed datasheet of the chip is available here: 8 * 9 * http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf 10 * 11 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c). 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 #include <linux/module.h> 25 #include <linux/mutex.h> 26 #include <linux/rtc.h> 27 #include <linux/i2c.h> 28 #include <linux/bcd.h> 29 #include <linux/of.h> 30 #include <linux/regmap.h> 31 #include <linux/interrupt.h> 32 33 #define DRV_NAME "rtc-ab-b5ze-s3" 34 35 /* Control section */ 36 #define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */ 37 #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */ 38 #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */ 39 #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */ 40 #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */ 41 #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */ 42 #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */ 43 #define ABB5ZES3_REG_CTRL1_CAP BIT(7) 44 45 #define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */ 46 #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */ 47 #define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */ 48 #define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */ 49 #define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */ 50 #define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */ 51 #define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */ 52 #define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */ 53 #define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */ 54 55 #define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */ 56 #define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */ 57 #define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */ 58 #define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */ 59 #define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */ 60 #define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */ 61 #define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */ 62 #define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */ 63 64 #define ABB5ZES3_CTRL_SEC_LEN 3 65 66 /* RTC section */ 67 #define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */ 68 #define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */ 69 #define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */ 70 #define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */ 71 #define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */ 72 #define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */ 73 #define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */ 74 #define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */ 75 #define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */ 76 77 #define ABB5ZES3_RTC_SEC_LEN 7 78 79 /* Alarm section (enable bits are all active low) */ 80 #define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */ 81 #define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */ 82 #define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */ 83 #define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */ 84 #define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */ 85 #define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */ 86 #define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */ 87 #define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */ 88 89 #define ABB5ZES3_ALRM_SEC_LEN 4 90 91 /* Frequency offset section */ 92 #define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */ 93 #define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */ 94 95 /* CLOCKOUT section */ 96 #define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */ 97 #define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */ 98 #define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */ 99 #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */ 100 #define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */ 101 #define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */ 102 #define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */ 103 #define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */ 104 #define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */ 105 106 /* Timer A Section */ 107 #define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */ 108 #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */ 109 #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */ 110 #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */ 111 #define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */ 112 113 #define ABB5ZES3_TIMA_SEC_LEN 2 114 115 /* Timer B Section */ 116 #define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */ 117 #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6) 118 #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5) 119 #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4) 120 #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2) 121 #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1) 122 #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0) 123 #define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */ 124 #define ABB5ZES3_TIMB_SEC_LEN 2 125 126 #define ABB5ZES3_MEM_MAP_LEN 0x14 127 128 struct abb5zes3_rtc_data { 129 struct rtc_device *rtc; 130 struct regmap *regmap; 131 struct mutex lock; 132 133 int irq; 134 135 bool battery_low; 136 bool timer_alarm; /* current alarm is via timer A */ 137 }; 138 139 /* 140 * Try and match register bits w/ fixed null values to see whether we 141 * are dealing with an ABB5ZES3. Note: this function is called early 142 * during init and hence does need mutex protection. 143 */ 144 static int abb5zes3_i2c_validate_chip(struct regmap *regmap) 145 { 146 u8 regs[ABB5ZES3_MEM_MAP_LEN]; 147 static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00, 148 0x80, 0xc0, 0xc0, 0xf8, 149 0xe0, 0x00, 0x00, 0x40, 150 0x40, 0x78, 0x00, 0x00, 151 0xf8, 0x00, 0x88, 0x00 }; 152 int ret, i; 153 154 ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN); 155 if (ret) 156 return ret; 157 158 for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) { 159 if (regs[i] & mask[i]) /* check if bits are cleared */ 160 return -ENODEV; 161 } 162 163 return 0; 164 } 165 166 /* Clear alarm status bit. */ 167 static int _abb5zes3_rtc_clear_alarm(struct device *dev) 168 { 169 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 170 int ret; 171 172 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2, 173 ABB5ZES3_REG_CTRL2_AF, 0); 174 if (ret) 175 dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret); 176 177 return ret; 178 } 179 180 /* Enable or disable alarm (i.e. alarm interrupt generation) */ 181 static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable) 182 { 183 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 184 int ret; 185 186 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1, 187 ABB5ZES3_REG_CTRL1_AIE, 188 enable ? ABB5ZES3_REG_CTRL1_AIE : 0); 189 if (ret) 190 dev_err(dev, "%s: writing alarm INT failed (%d)\n", 191 __func__, ret); 192 193 return ret; 194 } 195 196 /* Enable or disable timer (watchdog timer A interrupt generation) */ 197 static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable) 198 { 199 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 200 int ret; 201 202 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2, 203 ABB5ZES3_REG_CTRL2_WTAIE, 204 enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0); 205 if (ret) 206 dev_err(dev, "%s: writing timer INT failed (%d)\n", 207 __func__, ret); 208 209 return ret; 210 } 211 212 /* 213 * Note: we only read, so regmap inner lock protection is sufficient, i.e. 214 * we do not need driver's main lock protection. 215 */ 216 static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm) 217 { 218 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 219 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN]; 220 int ret = 0; 221 222 /* 223 * As we need to read CTRL1 register anyway to access 24/12h 224 * mode bit, we do a single bulk read of both control and RTC 225 * sections (they are consecutive). This also ease indexing 226 * of register values after bulk read. 227 */ 228 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs, 229 sizeof(regs)); 230 if (ret) { 231 dev_err(dev, "%s: reading RTC time failed (%d)\n", 232 __func__, ret); 233 goto err; 234 } 235 236 /* If clock integrity is not guaranteed, do not return a time value */ 237 if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC) { 238 ret = -ENODATA; 239 goto err; 240 } 241 242 tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F); 243 tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]); 244 245 if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */ 246 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f); 247 if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */ 248 tm->tm_hour += 12; 249 } else { /* 24hr mode */ 250 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]); 251 } 252 253 tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]); 254 tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]); 255 tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */ 256 tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100; 257 258 err: 259 return ret; 260 } 261 262 static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm) 263 { 264 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 265 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN]; 266 int ret; 267 268 /* 269 * Year register is 8-bit wide and bcd-coded, i.e records values 270 * between 0 and 99. tm_year is an offset from 1900 and we are 271 * interested in the 2000-2099 range, so any value less than 100 272 * is invalid. 273 */ 274 if (tm->tm_year < 100) 275 return -EINVAL; 276 277 regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */ 278 regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min); 279 regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */ 280 regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday); 281 regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday); 282 regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1); 283 regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100); 284 285 mutex_lock(&data->lock); 286 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC, 287 regs + ABB5ZES3_REG_RTC_SC, 288 ABB5ZES3_RTC_SEC_LEN); 289 mutex_unlock(&data->lock); 290 291 292 return ret; 293 } 294 295 /* 296 * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on 297 * given number of seconds. 298 */ 299 static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a) 300 { 301 *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */ 302 *timer_a = secs; 303 } 304 305 /* 306 * Return current number of seconds in Timer A. As we only use 307 * timer A with a 1Hz freq, this is what we expect to have. 308 */ 309 static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a) 310 { 311 if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */ 312 return -EINVAL; 313 314 *secs = timer_a; 315 316 return 0; 317 } 318 319 /* 320 * Read alarm currently configured via a watchdog timer using timer A. This 321 * is done by reading current RTC time and adding remaining timer time. 322 */ 323 static int _abb5zes3_rtc_read_timer(struct device *dev, 324 struct rtc_wkalrm *alarm) 325 { 326 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 327 struct rtc_time rtc_tm, *alarm_tm = &alarm->time; 328 u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1]; 329 unsigned long rtc_secs; 330 unsigned int reg; 331 u8 timer_secs; 332 int ret; 333 334 /* 335 * Instead of doing two separate calls, because they are consecutive, 336 * we grab both clockout register and Timer A section. The latter is 337 * used to decide if timer A is enabled (as a watchdog timer). 338 */ 339 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs, 340 ABB5ZES3_TIMA_SEC_LEN + 1); 341 if (ret) { 342 dev_err(dev, "%s: reading Timer A section failed (%d)\n", 343 __func__, ret); 344 goto err; 345 } 346 347 /* get current time ... */ 348 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm); 349 if (ret) 350 goto err; 351 352 /* ... convert to seconds ... */ 353 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs); 354 if (ret) 355 goto err; 356 357 /* ... add remaining timer A time ... */ 358 ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]); 359 if (ret) 360 goto err; 361 362 /* ... and convert back. */ 363 rtc_time_to_tm(rtc_secs + timer_secs, alarm_tm); 364 365 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, ®); 366 if (ret) { 367 dev_err(dev, "%s: reading ctrl reg failed (%d)\n", 368 __func__, ret); 369 goto err; 370 } 371 372 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE); 373 374 err: 375 return ret; 376 } 377 378 /* Read alarm currently configured via a RTC alarm registers. */ 379 static int _abb5zes3_rtc_read_alarm(struct device *dev, 380 struct rtc_wkalrm *alarm) 381 { 382 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 383 struct rtc_time rtc_tm, *alarm_tm = &alarm->time; 384 unsigned long rtc_secs, alarm_secs; 385 u8 regs[ABB5ZES3_ALRM_SEC_LEN]; 386 unsigned int reg; 387 int ret; 388 389 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs, 390 ABB5ZES3_ALRM_SEC_LEN); 391 if (ret) { 392 dev_err(dev, "%s: reading alarm section failed (%d)\n", 393 __func__, ret); 394 goto err; 395 } 396 397 alarm_tm->tm_sec = 0; 398 alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f); 399 alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f); 400 alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f); 401 alarm_tm->tm_wday = -1; 402 403 /* 404 * The alarm section does not store year/month. We use the ones in rtc 405 * section as a basis and increment month and then year if needed to get 406 * alarm after current time. 407 */ 408 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm); 409 if (ret) 410 goto err; 411 412 alarm_tm->tm_year = rtc_tm.tm_year; 413 alarm_tm->tm_mon = rtc_tm.tm_mon; 414 415 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs); 416 if (ret) 417 goto err; 418 419 ret = rtc_tm_to_time(alarm_tm, &alarm_secs); 420 if (ret) 421 goto err; 422 423 if (alarm_secs < rtc_secs) { 424 if (alarm_tm->tm_mon == 11) { 425 alarm_tm->tm_mon = 0; 426 alarm_tm->tm_year += 1; 427 } else { 428 alarm_tm->tm_mon += 1; 429 } 430 } 431 432 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, ®); 433 if (ret) { 434 dev_err(dev, "%s: reading ctrl reg failed (%d)\n", 435 __func__, ret); 436 goto err; 437 } 438 439 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE); 440 441 err: 442 return ret; 443 } 444 445 /* 446 * As the Alarm mechanism supported by the chip is only accurate to the 447 * minute, we use the watchdog timer mechanism provided by timer A 448 * (up to 256 seconds w/ a second accuracy) for low alarm values (below 449 * 4 minutes). Otherwise, we use the common alarm mechanism provided 450 * by the chip. In order for that to work, we keep track of currently 451 * configured timer type via 'timer_alarm' flag in our private data 452 * structure. 453 */ 454 static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 455 { 456 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 457 int ret; 458 459 mutex_lock(&data->lock); 460 if (data->timer_alarm) 461 ret = _abb5zes3_rtc_read_timer(dev, alarm); 462 else 463 ret = _abb5zes3_rtc_read_alarm(dev, alarm); 464 mutex_unlock(&data->lock); 465 466 return ret; 467 } 468 469 /* 470 * Set alarm using chip alarm mechanism. It is only accurate to the 471 * minute (not the second). The function expects alarm interrupt to 472 * be disabled. 473 */ 474 static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 475 { 476 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 477 struct rtc_time *alarm_tm = &alarm->time; 478 unsigned long rtc_secs, alarm_secs; 479 u8 regs[ABB5ZES3_ALRM_SEC_LEN]; 480 struct rtc_time rtc_tm; 481 int ret, enable = 1; 482 483 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm); 484 if (ret) 485 goto err; 486 487 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs); 488 if (ret) 489 goto err; 490 491 ret = rtc_tm_to_time(alarm_tm, &alarm_secs); 492 if (ret) 493 goto err; 494 495 /* If alarm time is before current time, disable the alarm */ 496 if (!alarm->enabled || alarm_secs <= rtc_secs) { 497 enable = 0; 498 } else { 499 /* 500 * Chip only support alarms up to one month in the future. Let's 501 * return an error if we get something after that limit. 502 * Comparison is done by incrementing rtc_tm month field by one 503 * and checking alarm value is still below. 504 */ 505 if (rtc_tm.tm_mon == 11) { /* handle year wrapping */ 506 rtc_tm.tm_mon = 0; 507 rtc_tm.tm_year += 1; 508 } else { 509 rtc_tm.tm_mon += 1; 510 } 511 512 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs); 513 if (ret) 514 goto err; 515 516 if (alarm_secs > rtc_secs) { 517 dev_err(dev, "%s: alarm maximum is one month in the " 518 "future (%d)\n", __func__, ret); 519 ret = -EINVAL; 520 goto err; 521 } 522 } 523 524 /* 525 * Program all alarm registers but DW one. For each register, setting 526 * MSB to 0 enables associated alarm. 527 */ 528 regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f; 529 regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f; 530 regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f; 531 regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */ 532 533 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs, 534 ABB5ZES3_ALRM_SEC_LEN); 535 if (ret < 0) { 536 dev_err(dev, "%s: writing ALARM section failed (%d)\n", 537 __func__, ret); 538 goto err; 539 } 540 541 /* Record currently configured alarm is not a timer */ 542 data->timer_alarm = 0; 543 544 /* Enable or disable alarm interrupt generation */ 545 ret = _abb5zes3_rtc_update_alarm(dev, enable); 546 547 err: 548 return ret; 549 } 550 551 /* 552 * Set alarm using timer watchdog (via timer A) mechanism. The function expects 553 * timer A interrupt to be disabled. 554 */ 555 static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm, 556 u8 secs) 557 { 558 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 559 u8 regs[ABB5ZES3_TIMA_SEC_LEN]; 560 u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1; 561 int ret = 0; 562 563 /* Program given number of seconds to Timer A registers */ 564 sec_to_timer_a(secs, ®s[0], ®s[1]); 565 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs, 566 ABB5ZES3_TIMA_SEC_LEN); 567 if (ret < 0) { 568 dev_err(dev, "%s: writing timer section failed\n", __func__); 569 goto err; 570 } 571 572 /* Configure Timer A as a watchdog timer */ 573 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK, 574 mask, ABB5ZES3_REG_TIM_CLK_TAC1); 575 if (ret) 576 dev_err(dev, "%s: failed to update timer\n", __func__); 577 578 /* Record currently configured alarm is a timer */ 579 data->timer_alarm = 1; 580 581 /* Enable or disable timer interrupt generation */ 582 ret = _abb5zes3_rtc_update_timer(dev, alarm->enabled); 583 584 err: 585 return ret; 586 } 587 588 /* 589 * The chip has an alarm which is only accurate to the minute. In order to 590 * handle alarms below that limit, we use the watchdog timer function of 591 * timer A. More precisely, the timer method is used for alarms below 240 592 * seconds. 593 */ 594 static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 595 { 596 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 597 struct rtc_time *alarm_tm = &alarm->time; 598 unsigned long rtc_secs, alarm_secs; 599 struct rtc_time rtc_tm; 600 int ret; 601 602 mutex_lock(&data->lock); 603 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm); 604 if (ret) 605 goto err; 606 607 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs); 608 if (ret) 609 goto err; 610 611 ret = rtc_tm_to_time(alarm_tm, &alarm_secs); 612 if (ret) 613 goto err; 614 615 /* Let's first disable both the alarm and the timer interrupts */ 616 ret = _abb5zes3_rtc_update_alarm(dev, false); 617 if (ret < 0) { 618 dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__, 619 ret); 620 goto err; 621 } 622 ret = _abb5zes3_rtc_update_timer(dev, false); 623 if (ret < 0) { 624 dev_err(dev, "%s: unable to disable timer (%d)\n", __func__, 625 ret); 626 goto err; 627 } 628 629 data->timer_alarm = 0; 630 631 /* 632 * Let's now configure the alarm; if we are expected to ring in 633 * more than 240s, then we setup an alarm. Otherwise, a timer. 634 */ 635 if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240)) 636 ret = _abb5zes3_rtc_set_timer(dev, alarm, 637 alarm_secs - rtc_secs); 638 else 639 ret = _abb5zes3_rtc_set_alarm(dev, alarm); 640 641 err: 642 mutex_unlock(&data->lock); 643 644 if (ret) 645 dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__, 646 ret); 647 648 return ret; 649 } 650 651 /* Enable or disable battery low irq generation */ 652 static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap, 653 bool enable) 654 { 655 return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, 656 ABB5ZES3_REG_CTRL3_BLIE, 657 enable ? ABB5ZES3_REG_CTRL3_BLIE : 0); 658 } 659 660 /* 661 * Check current RTC status and enable/disable what needs to be. Return 0 if 662 * everything went ok and a negative value upon error. Note: this function 663 * is called early during init and hence does need mutex protection. 664 */ 665 static int abb5zes3_rtc_check_setup(struct device *dev) 666 { 667 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev); 668 struct regmap *regmap = data->regmap; 669 unsigned int reg; 670 int ret; 671 u8 mask; 672 673 /* 674 * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It 675 * is disabled here to prevent polluting the interrupt line and 676 * uselessly triggering the IRQ handler we install for alarm and battery 677 * low events. Note: this is done before clearing int. status below 678 * in this function. 679 * We also disable all timers and set timer interrupt to permanent (not 680 * pulsed). 681 */ 682 mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 | 683 ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 | 684 ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 | 685 ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM); 686 ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask, 687 ABB5ZES3_REG_TIM_CLK_COF0 | ABB5ZES3_REG_TIM_CLK_COF1 | 688 ABB5ZES3_REG_TIM_CLK_COF2); 689 if (ret < 0) { 690 dev_err(dev, "%s: unable to initialize clkout register (%d)\n", 691 __func__, ret); 692 return ret; 693 } 694 695 /* 696 * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled 697 * individually by clearing/setting MSB of each associated register. So, 698 * we set all alarm enable bits to disable current alarm setting. 699 */ 700 mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE | 701 ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE); 702 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask); 703 if (ret < 0) { 704 dev_err(dev, "%s: unable to disable alarm setting (%d)\n", 705 __func__, ret); 706 return ret; 707 } 708 709 /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */ 710 mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE | 711 ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM | 712 ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP); 713 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0); 714 if (ret < 0) { 715 dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n", 716 __func__, ret); 717 return ret; 718 } 719 720 /* 721 * Set Control 2 register (timer int. disabled, alarm status cleared). 722 * WTAF is read-only and cleared automatically by reading the register. 723 */ 724 mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE | 725 ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF | 726 ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF | 727 ABB5ZES3_REG_CTRL2_CTAF); 728 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0); 729 if (ret < 0) { 730 dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n", 731 __func__, ret); 732 return ret; 733 } 734 735 /* 736 * Enable battery low detection function and battery switchover function 737 * (standard mode). Disable associated interrupts. Clear battery 738 * switchover flag but not battery low flag. The latter is checked 739 * later below. 740 */ 741 mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 | 742 ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE | 743 ABB5ZES3_REG_CTRL3_BSIE| ABB5ZES3_REG_CTRL3_BSF); 744 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0); 745 if (ret < 0) { 746 dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n", 747 __func__, ret); 748 return ret; 749 } 750 751 /* Check oscillator integrity flag */ 752 ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, ®); 753 if (ret < 0) { 754 dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n", 755 __func__, ret); 756 return ret; 757 } 758 759 if (reg & ABB5ZES3_REG_RTC_SC_OSC) { 760 dev_err(dev, "clock integrity not guaranteed. Osc. has stopped " 761 "or has been interrupted.\n"); 762 dev_err(dev, "change battery (if not already done) and " 763 "then set time to reset osc. failure flag.\n"); 764 } 765 766 /* 767 * Check battery low flag at startup: this allows reporting battery 768 * is low at startup when IRQ line is not connected. Note: we record 769 * current status to avoid reenabling this interrupt later in probe 770 * function if battery is low. 771 */ 772 ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, ®); 773 if (ret < 0) { 774 dev_err(dev, "%s: unable to read battery low flag (%d)\n", 775 __func__, ret); 776 return ret; 777 } 778 779 data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF; 780 if (data->battery_low) { 781 dev_err(dev, "RTC battery is low; please, consider " 782 "changing it!\n"); 783 784 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false); 785 if (ret) 786 dev_err(dev, "%s: disabling battery low interrupt " 787 "generation failed (%d)\n", __func__, ret); 788 } 789 790 return ret; 791 } 792 793 static int abb5zes3_rtc_alarm_irq_enable(struct device *dev, 794 unsigned int enable) 795 { 796 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev); 797 int ret = 0; 798 799 if (rtc_data->irq) { 800 mutex_lock(&rtc_data->lock); 801 if (rtc_data->timer_alarm) 802 ret = _abb5zes3_rtc_update_timer(dev, enable); 803 else 804 ret = _abb5zes3_rtc_update_alarm(dev, enable); 805 mutex_unlock(&rtc_data->lock); 806 } 807 808 return ret; 809 } 810 811 static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data) 812 { 813 struct i2c_client *client = data; 814 struct device *dev = &client->dev; 815 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev); 816 struct rtc_device *rtc = rtc_data->rtc; 817 u8 regs[ABB5ZES3_CTRL_SEC_LEN]; 818 int ret, handled = IRQ_NONE; 819 820 ret = regmap_bulk_read(rtc_data->regmap, 0, regs, 821 ABB5ZES3_CTRL_SEC_LEN); 822 if (ret) { 823 dev_err(dev, "%s: unable to read control section (%d)!\n", 824 __func__, ret); 825 return handled; 826 } 827 828 /* 829 * Check battery low detection flag and disable battery low interrupt 830 * generation if flag is set (interrupt can only be cleared when 831 * battery is replaced). 832 */ 833 if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) { 834 dev_err(dev, "RTC battery is low; please change it!\n"); 835 836 _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false); 837 838 handled = IRQ_HANDLED; 839 } 840 841 /* Check alarm flag */ 842 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) { 843 dev_dbg(dev, "RTC alarm!\n"); 844 845 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF); 846 847 /* Acknowledge and disable the alarm */ 848 _abb5zes3_rtc_clear_alarm(dev); 849 _abb5zes3_rtc_update_alarm(dev, 0); 850 851 handled = IRQ_HANDLED; 852 } 853 854 /* Check watchdog Timer A flag */ 855 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) { 856 dev_dbg(dev, "RTC timer!\n"); 857 858 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF); 859 860 /* 861 * Acknowledge and disable the alarm. Note: WTAF 862 * flag had been cleared when reading CTRL2 863 */ 864 _abb5zes3_rtc_update_timer(dev, 0); 865 866 rtc_data->timer_alarm = 0; 867 868 handled = IRQ_HANDLED; 869 } 870 871 return handled; 872 } 873 874 static const struct rtc_class_ops rtc_ops = { 875 .read_time = _abb5zes3_rtc_read_time, 876 .set_time = abb5zes3_rtc_set_time, 877 .read_alarm = abb5zes3_rtc_read_alarm, 878 .set_alarm = abb5zes3_rtc_set_alarm, 879 .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable, 880 }; 881 882 static const struct regmap_config abb5zes3_rtc_regmap_config = { 883 .reg_bits = 8, 884 .val_bits = 8, 885 }; 886 887 static int abb5zes3_probe(struct i2c_client *client, 888 const struct i2c_device_id *id) 889 { 890 struct abb5zes3_rtc_data *data = NULL; 891 struct device *dev = &client->dev; 892 struct regmap *regmap; 893 int ret; 894 895 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | 896 I2C_FUNC_SMBUS_BYTE_DATA | 897 I2C_FUNC_SMBUS_I2C_BLOCK)) { 898 ret = -ENODEV; 899 goto err; 900 } 901 902 regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config); 903 if (IS_ERR(regmap)) { 904 ret = PTR_ERR(regmap); 905 dev_err(dev, "%s: regmap allocation failed: %d\n", 906 __func__, ret); 907 goto err; 908 } 909 910 ret = abb5zes3_i2c_validate_chip(regmap); 911 if (ret) 912 goto err; 913 914 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 915 if (!data) { 916 ret = -ENOMEM; 917 goto err; 918 } 919 920 mutex_init(&data->lock); 921 data->regmap = regmap; 922 dev_set_drvdata(dev, data); 923 924 ret = abb5zes3_rtc_check_setup(dev); 925 if (ret) 926 goto err; 927 928 if (client->irq > 0) { 929 ret = devm_request_threaded_irq(dev, client->irq, NULL, 930 _abb5zes3_rtc_interrupt, 931 IRQF_SHARED|IRQF_ONESHOT, 932 DRV_NAME, client); 933 if (!ret) { 934 device_init_wakeup(dev, true); 935 data->irq = client->irq; 936 dev_dbg(dev, "%s: irq %d used by RTC\n", __func__, 937 client->irq); 938 } else { 939 dev_err(dev, "%s: irq %d unavailable (%d)\n", 940 __func__, client->irq, ret); 941 goto err; 942 } 943 } 944 945 data->rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops, 946 THIS_MODULE); 947 ret = PTR_ERR_OR_ZERO(data->rtc); 948 if (ret) { 949 dev_err(dev, "%s: unable to register RTC device (%d)\n", 950 __func__, ret); 951 goto err; 952 } 953 954 /* Enable battery low detection interrupt if battery not already low */ 955 if (!data->battery_low && data->irq) { 956 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true); 957 if (ret) { 958 dev_err(dev, "%s: enabling battery low interrupt " 959 "generation failed (%d)\n", __func__, ret); 960 goto err; 961 } 962 } 963 964 err: 965 if (ret && data && data->irq) 966 device_init_wakeup(dev, false); 967 return ret; 968 } 969 970 static int abb5zes3_remove(struct i2c_client *client) 971 { 972 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(&client->dev); 973 974 if (rtc_data->irq > 0) 975 device_init_wakeup(&client->dev, false); 976 977 return 0; 978 } 979 980 #ifdef CONFIG_PM_SLEEP 981 static int abb5zes3_rtc_suspend(struct device *dev) 982 { 983 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev); 984 985 if (device_may_wakeup(dev)) 986 return enable_irq_wake(rtc_data->irq); 987 988 return 0; 989 } 990 991 static int abb5zes3_rtc_resume(struct device *dev) 992 { 993 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev); 994 995 if (device_may_wakeup(dev)) 996 return disable_irq_wake(rtc_data->irq); 997 998 return 0; 999 } 1000 #endif 1001 1002 static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend, 1003 abb5zes3_rtc_resume); 1004 1005 #ifdef CONFIG_OF 1006 static const struct of_device_id abb5zes3_dt_match[] = { 1007 { .compatible = "abracon,abb5zes3" }, 1008 { }, 1009 }; 1010 MODULE_DEVICE_TABLE(of, abb5zes3_dt_match); 1011 #endif 1012 1013 static const struct i2c_device_id abb5zes3_id[] = { 1014 { "abb5zes3", 0 }, 1015 { } 1016 }; 1017 MODULE_DEVICE_TABLE(i2c, abb5zes3_id); 1018 1019 static struct i2c_driver abb5zes3_driver = { 1020 .driver = { 1021 .name = DRV_NAME, 1022 .pm = &abb5zes3_rtc_pm_ops, 1023 .of_match_table = of_match_ptr(abb5zes3_dt_match), 1024 }, 1025 .probe = abb5zes3_probe, 1026 .remove = abb5zes3_remove, 1027 .id_table = abb5zes3_id, 1028 }; 1029 module_i2c_driver(abb5zes3_driver); 1030 1031 MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>"); 1032 MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver"); 1033 MODULE_LICENSE("GPL"); 1034