1 /* 2 * Copyright (c) 2015, National Instruments Corp. 3 * 4 * Xilinx Zynq Reset controller driver 5 * 6 * Author: Moritz Fischer <moritz.fischer@ettus.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/init.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/reset-controller.h> 25 #include <linux/regmap.h> 26 #include <linux/types.h> 27 28 struct zynq_reset_data { 29 struct regmap *slcr; 30 struct reset_controller_dev rcdev; 31 u32 offset; 32 }; 33 34 #define to_zynq_reset_data(p) \ 35 container_of((p), struct zynq_reset_data, rcdev) 36 37 static int zynq_reset_assert(struct reset_controller_dev *rcdev, 38 unsigned long id) 39 { 40 struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); 41 42 int bank = id / BITS_PER_LONG; 43 int offset = id % BITS_PER_LONG; 44 45 pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__, 46 bank, offset); 47 48 return regmap_update_bits(priv->slcr, 49 priv->offset + (bank * 4), 50 BIT(offset), 51 BIT(offset)); 52 } 53 54 static int zynq_reset_deassert(struct reset_controller_dev *rcdev, 55 unsigned long id) 56 { 57 struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); 58 59 int bank = id / BITS_PER_LONG; 60 int offset = id % BITS_PER_LONG; 61 62 pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__, 63 bank, offset); 64 65 return regmap_update_bits(priv->slcr, 66 priv->offset + (bank * 4), 67 BIT(offset), 68 ~BIT(offset)); 69 } 70 71 static int zynq_reset_status(struct reset_controller_dev *rcdev, 72 unsigned long id) 73 { 74 struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); 75 76 int bank = id / BITS_PER_LONG; 77 int offset = id % BITS_PER_LONG; 78 int ret; 79 u32 reg; 80 81 pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__, 82 bank, offset); 83 84 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®); 85 if (ret) 86 return ret; 87 88 return !!(reg & BIT(offset)); 89 } 90 91 static const struct reset_control_ops zynq_reset_ops = { 92 .assert = zynq_reset_assert, 93 .deassert = zynq_reset_deassert, 94 .status = zynq_reset_status, 95 }; 96 97 static int zynq_reset_probe(struct platform_device *pdev) 98 { 99 struct resource *res; 100 struct zynq_reset_data *priv; 101 102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 103 if (!priv) 104 return -ENOMEM; 105 platform_set_drvdata(pdev, priv); 106 107 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 108 "syscon"); 109 if (IS_ERR(priv->slcr)) { 110 dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); 111 return PTR_ERR(priv->slcr); 112 } 113 114 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 115 if (!res) { 116 dev_err(&pdev->dev, "missing IO resource\n"); 117 return -ENODEV; 118 } 119 120 priv->offset = res->start; 121 122 priv->rcdev.owner = THIS_MODULE; 123 priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG; 124 priv->rcdev.ops = &zynq_reset_ops; 125 priv->rcdev.of_node = pdev->dev.of_node; 126 127 return devm_reset_controller_register(&pdev->dev, &priv->rcdev); 128 } 129 130 static const struct of_device_id zynq_reset_dt_ids[] = { 131 { .compatible = "xlnx,zynq-reset", }, 132 { /* sentinel */ }, 133 }; 134 135 static struct platform_driver zynq_reset_driver = { 136 .probe = zynq_reset_probe, 137 .driver = { 138 .name = KBUILD_MODNAME, 139 .of_match_table = zynq_reset_dt_ids, 140 }, 141 }; 142 builtin_platform_driver(zynq_reset_driver); 143