1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of_device.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
11 
12 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
13 
14 #define RPMH_SDM845_PDC_SYNC_RESET	0x100
15 #define RPMH_SC7280_PDC_SYNC_RESET	0x1000
16 
17 struct qcom_pdc_reset_map {
18 	u8 bit;
19 };
20 
21 struct qcom_pdc_reset_desc {
22 	const struct qcom_pdc_reset_map *resets;
23 	size_t num_resets;
24 	unsigned int offset;
25 };
26 
27 struct qcom_pdc_reset_data {
28 	struct reset_controller_dev rcdev;
29 	struct regmap *regmap;
30 	const struct qcom_pdc_reset_desc *desc;
31 };
32 
33 static const struct regmap_config pdc_regmap_config = {
34 	.name		= "pdc-reset",
35 	.reg_bits	= 32,
36 	.reg_stride	= 4,
37 	.val_bits	= 32,
38 	.max_register	= 0x20000,
39 	.fast_io	= true,
40 };
41 
42 static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
43 	[PDC_APPS_SYNC_RESET] = {0},
44 	[PDC_SP_SYNC_RESET] = {1},
45 	[PDC_AUDIO_SYNC_RESET] = {2},
46 	[PDC_SENSORS_SYNC_RESET] = {3},
47 	[PDC_AOP_SYNC_RESET] = {4},
48 	[PDC_DEBUG_SYNC_RESET] = {5},
49 	[PDC_GPU_SYNC_RESET] = {6},
50 	[PDC_DISPLAY_SYNC_RESET] = {7},
51 	[PDC_COMPUTE_SYNC_RESET] = {8},
52 	[PDC_MODEM_SYNC_RESET] = {9},
53 };
54 
55 static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
56 	.resets = sdm845_pdc_resets,
57 	.num_resets = ARRAY_SIZE(sdm845_pdc_resets),
58 	.offset = RPMH_SDM845_PDC_SYNC_RESET,
59 };
60 
61 static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
62 	[PDC_APPS_SYNC_RESET] = {0},
63 	[PDC_SP_SYNC_RESET] = {1},
64 	[PDC_AUDIO_SYNC_RESET] = {2},
65 	[PDC_SENSORS_SYNC_RESET] = {3},
66 	[PDC_AOP_SYNC_RESET] = {4},
67 	[PDC_DEBUG_SYNC_RESET] = {5},
68 	[PDC_GPU_SYNC_RESET] = {6},
69 	[PDC_DISPLAY_SYNC_RESET] = {7},
70 	[PDC_COMPUTE_SYNC_RESET] = {8},
71 	[PDC_MODEM_SYNC_RESET] = {9},
72 	[PDC_WLAN_RF_SYNC_RESET] = {10},
73 	[PDC_WPSS_SYNC_RESET] = {11},
74 };
75 
76 static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
77 	.resets = sc7280_pdc_resets,
78 	.num_resets = ARRAY_SIZE(sc7280_pdc_resets),
79 	.offset = RPMH_SC7280_PDC_SYNC_RESET,
80 };
81 
82 static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
83 				struct reset_controller_dev *rcdev)
84 {
85 	return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
86 }
87 
88 static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
89 					unsigned long idx)
90 {
91 	struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
92 	u32 mask = BIT(data->desc->resets[idx].bit);
93 
94 	return regmap_update_bits(data->regmap, data->desc->offset, mask, mask);
95 }
96 
97 static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
98 					unsigned long idx)
99 {
100 	struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
101 	u32 mask = BIT(data->desc->resets[idx].bit);
102 
103 	return regmap_update_bits(data->regmap, data->desc->offset, mask, 0);
104 }
105 
106 static const struct reset_control_ops qcom_pdc_reset_ops = {
107 	.assert = qcom_pdc_control_assert,
108 	.deassert = qcom_pdc_control_deassert,
109 };
110 
111 static int qcom_pdc_reset_probe(struct platform_device *pdev)
112 {
113 	const struct qcom_pdc_reset_desc *desc;
114 	struct qcom_pdc_reset_data *data;
115 	struct device *dev = &pdev->dev;
116 	void __iomem *base;
117 	struct resource *res;
118 
119 	desc = device_get_match_data(&pdev->dev);
120 	if (!desc)
121 		return -EINVAL;
122 
123 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
124 	if (!data)
125 		return -ENOMEM;
126 
127 	data->desc = desc;
128 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
129 	base = devm_ioremap_resource(dev, res);
130 	if (IS_ERR(base))
131 		return PTR_ERR(base);
132 
133 	data->regmap = devm_regmap_init_mmio(dev, base, &pdc_regmap_config);
134 	if (IS_ERR(data->regmap)) {
135 		dev_err(dev, "Unable to initialize regmap\n");
136 		return PTR_ERR(data->regmap);
137 	}
138 
139 	data->rcdev.owner = THIS_MODULE;
140 	data->rcdev.ops = &qcom_pdc_reset_ops;
141 	data->rcdev.nr_resets = desc->num_resets;
142 	data->rcdev.of_node = dev->of_node;
143 
144 	return devm_reset_controller_register(dev, &data->rcdev);
145 }
146 
147 static const struct of_device_id qcom_pdc_reset_of_match[] = {
148 	{ .compatible = "qcom,sc7280-pdc-global", .data = &sc7280_pdc_reset_desc },
149 	{ .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_reset_desc },
150 	{}
151 };
152 MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
153 
154 static struct platform_driver qcom_pdc_reset_driver = {
155 	.probe = qcom_pdc_reset_probe,
156 	.driver = {
157 		.name = "qcom_pdc_reset",
158 		.of_match_table = qcom_pdc_reset_of_match,
159 	},
160 };
161 module_platform_driver(qcom_pdc_reset_driver);
162 
163 MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
164 MODULE_LICENSE("GPL v2");
165