1*e4bb55d6SJacky Huang // SPDX-License-Identifier: GPL-2.0-only
2*e4bb55d6SJacky Huang /*
3*e4bb55d6SJacky Huang * Copyright (C) 2023 Nuvoton Technology Corp.
4*e4bb55d6SJacky Huang * Author: Chi-Fang Li <cfli0@nuvoton.com>
5*e4bb55d6SJacky Huang */
6*e4bb55d6SJacky Huang
7*e4bb55d6SJacky Huang #include <linux/bits.h>
8*e4bb55d6SJacky Huang #include <linux/container_of.h>
9*e4bb55d6SJacky Huang #include <linux/device.h>
10*e4bb55d6SJacky Huang #include <linux/err.h>
11*e4bb55d6SJacky Huang #include <linux/io.h>
12*e4bb55d6SJacky Huang #include <linux/kernel.h>
13*e4bb55d6SJacky Huang #include <linux/of.h>
14*e4bb55d6SJacky Huang #include <linux/platform_device.h>
15*e4bb55d6SJacky Huang #include <linux/reboot.h>
16*e4bb55d6SJacky Huang #include <linux/reset-controller.h>
17*e4bb55d6SJacky Huang #include <linux/spinlock.h>
18*e4bb55d6SJacky Huang #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
19*e4bb55d6SJacky Huang
20*e4bb55d6SJacky Huang struct ma35d1_reset_data {
21*e4bb55d6SJacky Huang struct reset_controller_dev rcdev;
22*e4bb55d6SJacky Huang struct notifier_block restart_handler;
23*e4bb55d6SJacky Huang void __iomem *base;
24*e4bb55d6SJacky Huang /* protect registers against concurrent read-modify-write */
25*e4bb55d6SJacky Huang spinlock_t lock;
26*e4bb55d6SJacky Huang };
27*e4bb55d6SJacky Huang
28*e4bb55d6SJacky Huang static const struct {
29*e4bb55d6SJacky Huang u32 reg_ofs;
30*e4bb55d6SJacky Huang u32 bit;
31*e4bb55d6SJacky Huang } ma35d1_reset_map[] = {
32*e4bb55d6SJacky Huang [MA35D1_RESET_CHIP] = {0x20, 0},
33*e4bb55d6SJacky Huang [MA35D1_RESET_CA35CR0] = {0x20, 1},
34*e4bb55d6SJacky Huang [MA35D1_RESET_CA35CR1] = {0x20, 2},
35*e4bb55d6SJacky Huang [MA35D1_RESET_CM4] = {0x20, 3},
36*e4bb55d6SJacky Huang [MA35D1_RESET_PDMA0] = {0x20, 4},
37*e4bb55d6SJacky Huang [MA35D1_RESET_PDMA1] = {0x20, 5},
38*e4bb55d6SJacky Huang [MA35D1_RESET_PDMA2] = {0x20, 6},
39*e4bb55d6SJacky Huang [MA35D1_RESET_PDMA3] = {0x20, 7},
40*e4bb55d6SJacky Huang [MA35D1_RESET_DISP] = {0x20, 9},
41*e4bb55d6SJacky Huang [MA35D1_RESET_VCAP0] = {0x20, 10},
42*e4bb55d6SJacky Huang [MA35D1_RESET_VCAP1] = {0x20, 11},
43*e4bb55d6SJacky Huang [MA35D1_RESET_GFX] = {0x20, 12},
44*e4bb55d6SJacky Huang [MA35D1_RESET_VDEC] = {0x20, 13},
45*e4bb55d6SJacky Huang [MA35D1_RESET_WHC0] = {0x20, 14},
46*e4bb55d6SJacky Huang [MA35D1_RESET_WHC1] = {0x20, 15},
47*e4bb55d6SJacky Huang [MA35D1_RESET_GMAC0] = {0x20, 16},
48*e4bb55d6SJacky Huang [MA35D1_RESET_GMAC1] = {0x20, 17},
49*e4bb55d6SJacky Huang [MA35D1_RESET_HWSEM] = {0x20, 18},
50*e4bb55d6SJacky Huang [MA35D1_RESET_EBI] = {0x20, 19},
51*e4bb55d6SJacky Huang [MA35D1_RESET_HSUSBH0] = {0x20, 20},
52*e4bb55d6SJacky Huang [MA35D1_RESET_HSUSBH1] = {0x20, 21},
53*e4bb55d6SJacky Huang [MA35D1_RESET_HSUSBD] = {0x20, 22},
54*e4bb55d6SJacky Huang [MA35D1_RESET_USBHL] = {0x20, 23},
55*e4bb55d6SJacky Huang [MA35D1_RESET_SDH0] = {0x20, 24},
56*e4bb55d6SJacky Huang [MA35D1_RESET_SDH1] = {0x20, 25},
57*e4bb55d6SJacky Huang [MA35D1_RESET_NAND] = {0x20, 26},
58*e4bb55d6SJacky Huang [MA35D1_RESET_GPIO] = {0x20, 27},
59*e4bb55d6SJacky Huang [MA35D1_RESET_MCTLP] = {0x20, 28},
60*e4bb55d6SJacky Huang [MA35D1_RESET_MCTLC] = {0x20, 29},
61*e4bb55d6SJacky Huang [MA35D1_RESET_DDRPUB] = {0x20, 30},
62*e4bb55d6SJacky Huang [MA35D1_RESET_TMR0] = {0x24, 2},
63*e4bb55d6SJacky Huang [MA35D1_RESET_TMR1] = {0x24, 3},
64*e4bb55d6SJacky Huang [MA35D1_RESET_TMR2] = {0x24, 4},
65*e4bb55d6SJacky Huang [MA35D1_RESET_TMR3] = {0x24, 5},
66*e4bb55d6SJacky Huang [MA35D1_RESET_I2C0] = {0x24, 8},
67*e4bb55d6SJacky Huang [MA35D1_RESET_I2C1] = {0x24, 9},
68*e4bb55d6SJacky Huang [MA35D1_RESET_I2C2] = {0x24, 10},
69*e4bb55d6SJacky Huang [MA35D1_RESET_I2C3] = {0x24, 11},
70*e4bb55d6SJacky Huang [MA35D1_RESET_QSPI0] = {0x24, 12},
71*e4bb55d6SJacky Huang [MA35D1_RESET_SPI0] = {0x24, 13},
72*e4bb55d6SJacky Huang [MA35D1_RESET_SPI1] = {0x24, 14},
73*e4bb55d6SJacky Huang [MA35D1_RESET_SPI2] = {0x24, 15},
74*e4bb55d6SJacky Huang [MA35D1_RESET_UART0] = {0x24, 16},
75*e4bb55d6SJacky Huang [MA35D1_RESET_UART1] = {0x24, 17},
76*e4bb55d6SJacky Huang [MA35D1_RESET_UART2] = {0x24, 18},
77*e4bb55d6SJacky Huang [MA35D1_RESET_UART3] = {0x24, 19},
78*e4bb55d6SJacky Huang [MA35D1_RESET_UART4] = {0x24, 20},
79*e4bb55d6SJacky Huang [MA35D1_RESET_UART5] = {0x24, 21},
80*e4bb55d6SJacky Huang [MA35D1_RESET_UART6] = {0x24, 22},
81*e4bb55d6SJacky Huang [MA35D1_RESET_UART7] = {0x24, 23},
82*e4bb55d6SJacky Huang [MA35D1_RESET_CANFD0] = {0x24, 24},
83*e4bb55d6SJacky Huang [MA35D1_RESET_CANFD1] = {0x24, 25},
84*e4bb55d6SJacky Huang [MA35D1_RESET_EADC0] = {0x24, 28},
85*e4bb55d6SJacky Huang [MA35D1_RESET_I2S0] = {0x24, 29},
86*e4bb55d6SJacky Huang [MA35D1_RESET_SC0] = {0x28, 0},
87*e4bb55d6SJacky Huang [MA35D1_RESET_SC1] = {0x28, 1},
88*e4bb55d6SJacky Huang [MA35D1_RESET_QSPI1] = {0x28, 4},
89*e4bb55d6SJacky Huang [MA35D1_RESET_SPI3] = {0x28, 6},
90*e4bb55d6SJacky Huang [MA35D1_RESET_EPWM0] = {0x28, 16},
91*e4bb55d6SJacky Huang [MA35D1_RESET_EPWM1] = {0x28, 17},
92*e4bb55d6SJacky Huang [MA35D1_RESET_QEI0] = {0x28, 22},
93*e4bb55d6SJacky Huang [MA35D1_RESET_QEI1] = {0x28, 23},
94*e4bb55d6SJacky Huang [MA35D1_RESET_ECAP0] = {0x28, 26},
95*e4bb55d6SJacky Huang [MA35D1_RESET_ECAP1] = {0x28, 27},
96*e4bb55d6SJacky Huang [MA35D1_RESET_CANFD2] = {0x28, 28},
97*e4bb55d6SJacky Huang [MA35D1_RESET_ADC0] = {0x28, 31},
98*e4bb55d6SJacky Huang [MA35D1_RESET_TMR4] = {0x2C, 0},
99*e4bb55d6SJacky Huang [MA35D1_RESET_TMR5] = {0x2C, 1},
100*e4bb55d6SJacky Huang [MA35D1_RESET_TMR6] = {0x2C, 2},
101*e4bb55d6SJacky Huang [MA35D1_RESET_TMR7] = {0x2C, 3},
102*e4bb55d6SJacky Huang [MA35D1_RESET_TMR8] = {0x2C, 4},
103*e4bb55d6SJacky Huang [MA35D1_RESET_TMR9] = {0x2C, 5},
104*e4bb55d6SJacky Huang [MA35D1_RESET_TMR10] = {0x2C, 6},
105*e4bb55d6SJacky Huang [MA35D1_RESET_TMR11] = {0x2C, 7},
106*e4bb55d6SJacky Huang [MA35D1_RESET_UART8] = {0x2C, 8},
107*e4bb55d6SJacky Huang [MA35D1_RESET_UART9] = {0x2C, 9},
108*e4bb55d6SJacky Huang [MA35D1_RESET_UART10] = {0x2C, 10},
109*e4bb55d6SJacky Huang [MA35D1_RESET_UART11] = {0x2C, 11},
110*e4bb55d6SJacky Huang [MA35D1_RESET_UART12] = {0x2C, 12},
111*e4bb55d6SJacky Huang [MA35D1_RESET_UART13] = {0x2C, 13},
112*e4bb55d6SJacky Huang [MA35D1_RESET_UART14] = {0x2C, 14},
113*e4bb55d6SJacky Huang [MA35D1_RESET_UART15] = {0x2C, 15},
114*e4bb55d6SJacky Huang [MA35D1_RESET_UART16] = {0x2C, 16},
115*e4bb55d6SJacky Huang [MA35D1_RESET_I2S1] = {0x2C, 17},
116*e4bb55d6SJacky Huang [MA35D1_RESET_I2C4] = {0x2C, 18},
117*e4bb55d6SJacky Huang [MA35D1_RESET_I2C5] = {0x2C, 19},
118*e4bb55d6SJacky Huang [MA35D1_RESET_EPWM2] = {0x2C, 20},
119*e4bb55d6SJacky Huang [MA35D1_RESET_ECAP2] = {0x2C, 21},
120*e4bb55d6SJacky Huang [MA35D1_RESET_QEI2] = {0x2C, 22},
121*e4bb55d6SJacky Huang [MA35D1_RESET_CANFD3] = {0x2C, 23},
122*e4bb55d6SJacky Huang [MA35D1_RESET_KPI] = {0x2C, 24},
123*e4bb55d6SJacky Huang [MA35D1_RESET_GIC] = {0x2C, 28},
124*e4bb55d6SJacky Huang [MA35D1_RESET_SSMCC] = {0x2C, 30},
125*e4bb55d6SJacky Huang [MA35D1_RESET_SSPCC] = {0x2C, 31}
126*e4bb55d6SJacky Huang };
127*e4bb55d6SJacky Huang
ma35d1_restart_handler(struct notifier_block * this,unsigned long mode,void * cmd)128*e4bb55d6SJacky Huang static int ma35d1_restart_handler(struct notifier_block *this, unsigned long mode, void *cmd)
129*e4bb55d6SJacky Huang {
130*e4bb55d6SJacky Huang struct ma35d1_reset_data *data =
131*e4bb55d6SJacky Huang container_of(this, struct ma35d1_reset_data, restart_handler);
132*e4bb55d6SJacky Huang u32 id = MA35D1_RESET_CHIP;
133*e4bb55d6SJacky Huang
134*e4bb55d6SJacky Huang writel_relaxed(BIT(ma35d1_reset_map[id].bit),
135*e4bb55d6SJacky Huang data->base + ma35d1_reset_map[id].reg_ofs);
136*e4bb55d6SJacky Huang return 0;
137*e4bb55d6SJacky Huang }
138*e4bb55d6SJacky Huang
ma35d1_reset_update(struct reset_controller_dev * rcdev,unsigned long id,bool assert)139*e4bb55d6SJacky Huang static int ma35d1_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert)
140*e4bb55d6SJacky Huang {
141*e4bb55d6SJacky Huang struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev);
142*e4bb55d6SJacky Huang unsigned long flags;
143*e4bb55d6SJacky Huang u32 reg;
144*e4bb55d6SJacky Huang
145*e4bb55d6SJacky Huang if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map)))
146*e4bb55d6SJacky Huang return -EINVAL;
147*e4bb55d6SJacky Huang
148*e4bb55d6SJacky Huang spin_lock_irqsave(&data->lock, flags);
149*e4bb55d6SJacky Huang reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs);
150*e4bb55d6SJacky Huang if (assert)
151*e4bb55d6SJacky Huang reg |= BIT(ma35d1_reset_map[id].bit);
152*e4bb55d6SJacky Huang else
153*e4bb55d6SJacky Huang reg &= ~(BIT(ma35d1_reset_map[id].bit));
154*e4bb55d6SJacky Huang writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs);
155*e4bb55d6SJacky Huang spin_unlock_irqrestore(&data->lock, flags);
156*e4bb55d6SJacky Huang
157*e4bb55d6SJacky Huang return 0;
158*e4bb55d6SJacky Huang }
159*e4bb55d6SJacky Huang
ma35d1_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)160*e4bb55d6SJacky Huang static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
161*e4bb55d6SJacky Huang {
162*e4bb55d6SJacky Huang return ma35d1_reset_update(rcdev, id, true);
163*e4bb55d6SJacky Huang }
164*e4bb55d6SJacky Huang
ma35d1_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)165*e4bb55d6SJacky Huang static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
166*e4bb55d6SJacky Huang {
167*e4bb55d6SJacky Huang return ma35d1_reset_update(rcdev, id, false);
168*e4bb55d6SJacky Huang }
169*e4bb55d6SJacky Huang
ma35d1_reset_status(struct reset_controller_dev * rcdev,unsigned long id)170*e4bb55d6SJacky Huang static int ma35d1_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
171*e4bb55d6SJacky Huang {
172*e4bb55d6SJacky Huang struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev);
173*e4bb55d6SJacky Huang u32 reg;
174*e4bb55d6SJacky Huang
175*e4bb55d6SJacky Huang if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map)))
176*e4bb55d6SJacky Huang return -EINVAL;
177*e4bb55d6SJacky Huang
178*e4bb55d6SJacky Huang reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs);
179*e4bb55d6SJacky Huang return !!(reg & BIT(ma35d1_reset_map[id].bit));
180*e4bb55d6SJacky Huang }
181*e4bb55d6SJacky Huang
182*e4bb55d6SJacky Huang static const struct reset_control_ops ma35d1_reset_ops = {
183*e4bb55d6SJacky Huang .assert = ma35d1_reset_assert,
184*e4bb55d6SJacky Huang .deassert = ma35d1_reset_deassert,
185*e4bb55d6SJacky Huang .status = ma35d1_reset_status,
186*e4bb55d6SJacky Huang };
187*e4bb55d6SJacky Huang
188*e4bb55d6SJacky Huang static const struct of_device_id ma35d1_reset_dt_ids[] = {
189*e4bb55d6SJacky Huang { .compatible = "nuvoton,ma35d1-reset" },
190*e4bb55d6SJacky Huang { },
191*e4bb55d6SJacky Huang };
192*e4bb55d6SJacky Huang
ma35d1_reset_probe(struct platform_device * pdev)193*e4bb55d6SJacky Huang static int ma35d1_reset_probe(struct platform_device *pdev)
194*e4bb55d6SJacky Huang {
195*e4bb55d6SJacky Huang struct ma35d1_reset_data *reset_data;
196*e4bb55d6SJacky Huang struct device *dev = &pdev->dev;
197*e4bb55d6SJacky Huang int err;
198*e4bb55d6SJacky Huang
199*e4bb55d6SJacky Huang if (!pdev->dev.of_node) {
200*e4bb55d6SJacky Huang dev_err(&pdev->dev, "Device tree node not found\n");
201*e4bb55d6SJacky Huang return -EINVAL;
202*e4bb55d6SJacky Huang }
203*e4bb55d6SJacky Huang
204*e4bb55d6SJacky Huang reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL);
205*e4bb55d6SJacky Huang if (!reset_data)
206*e4bb55d6SJacky Huang return -ENOMEM;
207*e4bb55d6SJacky Huang
208*e4bb55d6SJacky Huang reset_data->base = devm_platform_ioremap_resource(pdev, 0);
209*e4bb55d6SJacky Huang if (IS_ERR(reset_data->base))
210*e4bb55d6SJacky Huang return PTR_ERR(reset_data->base);
211*e4bb55d6SJacky Huang
212*e4bb55d6SJacky Huang reset_data->rcdev.owner = THIS_MODULE;
213*e4bb55d6SJacky Huang reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT;
214*e4bb55d6SJacky Huang reset_data->rcdev.ops = &ma35d1_reset_ops;
215*e4bb55d6SJacky Huang reset_data->rcdev.of_node = dev->of_node;
216*e4bb55d6SJacky Huang reset_data->restart_handler.notifier_call = ma35d1_restart_handler;
217*e4bb55d6SJacky Huang reset_data->restart_handler.priority = 192;
218*e4bb55d6SJacky Huang spin_lock_init(&reset_data->lock);
219*e4bb55d6SJacky Huang
220*e4bb55d6SJacky Huang err = register_restart_handler(&reset_data->restart_handler);
221*e4bb55d6SJacky Huang if (err)
222*e4bb55d6SJacky Huang dev_warn(&pdev->dev, "failed to register restart handler\n");
223*e4bb55d6SJacky Huang
224*e4bb55d6SJacky Huang return devm_reset_controller_register(dev, &reset_data->rcdev);
225*e4bb55d6SJacky Huang }
226*e4bb55d6SJacky Huang
227*e4bb55d6SJacky Huang static struct platform_driver ma35d1_reset_driver = {
228*e4bb55d6SJacky Huang .probe = ma35d1_reset_probe,
229*e4bb55d6SJacky Huang .driver = {
230*e4bb55d6SJacky Huang .name = "ma35d1-reset",
231*e4bb55d6SJacky Huang .of_match_table = ma35d1_reset_dt_ids,
232*e4bb55d6SJacky Huang },
233*e4bb55d6SJacky Huang };
234*e4bb55d6SJacky Huang
235*e4bb55d6SJacky Huang builtin_platform_driver(ma35d1_reset_driver);
236