1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017, Impinj, Inc. 4 * 5 * i.MX7 System Reset Controller (SRC) driver 6 * 7 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 8 */ 9 10 #include <linux/mfd/syscon.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset-controller.h> 15 #include <linux/regmap.h> 16 #include <dt-bindings/reset/imx7-reset.h> 17 #include <dt-bindings/reset/imx8mq-reset.h> 18 19 struct imx7_src_signal { 20 unsigned int offset, bit; 21 }; 22 23 struct imx7_src_variant { 24 const struct imx7_src_signal *signals; 25 unsigned int signals_num; 26 struct reset_control_ops ops; 27 }; 28 29 struct imx7_src { 30 struct reset_controller_dev rcdev; 31 struct regmap *regmap; 32 const struct imx7_src_signal *signals; 33 }; 34 35 enum imx7_src_registers { 36 SRC_A7RCR0 = 0x0004, 37 SRC_M4RCR = 0x000c, 38 SRC_ERCR = 0x0014, 39 SRC_HSICPHY_RCR = 0x001c, 40 SRC_USBOPHY1_RCR = 0x0020, 41 SRC_USBOPHY2_RCR = 0x0024, 42 SRC_MIPIPHY_RCR = 0x0028, 43 SRC_PCIEPHY_RCR = 0x002c, 44 SRC_DDRC_RCR = 0x1000, 45 }; 46 47 static int imx7_reset_update(struct imx7_src *imx7src, 48 unsigned long id, unsigned int value) 49 { 50 const struct imx7_src_signal *signal = &imx7src->signals[id]; 51 52 return regmap_update_bits(imx7src->regmap, 53 signal->offset, signal->bit, value); 54 } 55 56 static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { 57 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, 58 [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, 59 [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, 60 [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, 61 [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, 62 [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, 63 [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, 64 [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, 65 [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, 66 [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, 67 [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, 68 [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, 69 [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, 70 [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, 71 [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, 72 [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, 73 [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, 74 [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, 75 [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, 76 [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, 77 [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, 78 [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, 79 [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, 80 [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, 81 [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, 82 [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, 83 }; 84 85 static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev) 86 { 87 return container_of(rcdev, struct imx7_src, rcdev); 88 } 89 90 static int imx7_reset_set(struct reset_controller_dev *rcdev, 91 unsigned long id, bool assert) 92 { 93 struct imx7_src *imx7src = to_imx7_src(rcdev); 94 const unsigned int bit = imx7src->signals[id].bit; 95 unsigned int value = assert ? bit : 0; 96 97 switch (id) { 98 case IMX7_RESET_PCIEPHY: 99 /* 100 * wait for more than 10us to release phy g_rst and 101 * btnrst 102 */ 103 if (!assert) 104 udelay(10); 105 break; 106 107 case IMX7_RESET_PCIE_CTRL_APPS_EN: 108 value = assert ? 0 : bit; 109 break; 110 } 111 112 return imx7_reset_update(imx7src, id, value); 113 } 114 115 static int imx7_reset_assert(struct reset_controller_dev *rcdev, 116 unsigned long id) 117 { 118 return imx7_reset_set(rcdev, id, true); 119 } 120 121 static int imx7_reset_deassert(struct reset_controller_dev *rcdev, 122 unsigned long id) 123 { 124 return imx7_reset_set(rcdev, id, false); 125 } 126 127 static const struct imx7_src_variant variant_imx7 = { 128 .signals = imx7_src_signals, 129 .signals_num = ARRAY_SIZE(imx7_src_signals), 130 .ops = { 131 .assert = imx7_reset_assert, 132 .deassert = imx7_reset_deassert, 133 }, 134 }; 135 136 enum imx8mq_src_registers { 137 SRC_A53RCR0 = 0x0004, 138 SRC_HDMI_RCR = 0x0030, 139 SRC_DISP_RCR = 0x0034, 140 SRC_GPU_RCR = 0x0040, 141 SRC_VPU_RCR = 0x0044, 142 SRC_PCIE2_RCR = 0x0048, 143 SRC_MIPIPHY1_RCR = 0x004c, 144 SRC_MIPIPHY2_RCR = 0x0050, 145 SRC_DDRC2_RCR = 0x1004, 146 }; 147 148 static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { 149 [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, 150 [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, 151 [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, 152 [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, 153 [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, 154 [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, 155 [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, 156 [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, 157 [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, 158 [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, 159 [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, 160 [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, 161 [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, 162 [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, 163 [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, 164 [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, 165 [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, 166 [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, 167 [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, 168 [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, 169 [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, 170 [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, 171 [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, 172 [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, 173 [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, 174 [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, 175 [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, 176 BIT(2) | BIT(1) }, 177 [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, 178 [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, 179 [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, 180 [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, 181 [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) }, 182 [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, 183 [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, 184 [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR, 185 BIT(2) | BIT(1) }, 186 [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) }, 187 [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) }, 188 [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) }, 189 [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) }, 190 [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) }, 191 [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) }, 192 [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) }, 193 [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) }, 194 [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) }, 195 [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) }, 196 [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) }, 197 [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) }, 198 [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) }, 199 [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) }, 200 [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, 201 }; 202 203 static int imx8mq_reset_set(struct reset_controller_dev *rcdev, 204 unsigned long id, bool assert) 205 { 206 struct imx7_src *imx7src = to_imx7_src(rcdev); 207 const unsigned int bit = imx7src->signals[id].bit; 208 unsigned int value = assert ? bit : 0; 209 210 switch (id) { 211 case IMX8MQ_RESET_PCIEPHY: 212 case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */ 213 /* 214 * wait for more than 10us to release phy g_rst and 215 * btnrst 216 */ 217 if (!assert) 218 udelay(10); 219 break; 220 221 case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: 222 case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ 223 case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */ 224 case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */ 225 case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */ 226 case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ 227 case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ 228 value = assert ? 0 : bit; 229 break; 230 } 231 232 return imx7_reset_update(imx7src, id, value); 233 } 234 235 static int imx8mq_reset_assert(struct reset_controller_dev *rcdev, 236 unsigned long id) 237 { 238 return imx8mq_reset_set(rcdev, id, true); 239 } 240 241 static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev, 242 unsigned long id) 243 { 244 return imx8mq_reset_set(rcdev, id, false); 245 } 246 247 static const struct imx7_src_variant variant_imx8mq = { 248 .signals = imx8mq_src_signals, 249 .signals_num = ARRAY_SIZE(imx8mq_src_signals), 250 .ops = { 251 .assert = imx8mq_reset_assert, 252 .deassert = imx8mq_reset_deassert, 253 }, 254 }; 255 256 static int imx7_reset_probe(struct platform_device *pdev) 257 { 258 struct imx7_src *imx7src; 259 struct device *dev = &pdev->dev; 260 struct regmap_config config = { .name = "src" }; 261 const struct imx7_src_variant *variant = of_device_get_match_data(dev); 262 263 imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL); 264 if (!imx7src) 265 return -ENOMEM; 266 267 imx7src->signals = variant->signals; 268 imx7src->regmap = syscon_node_to_regmap(dev->of_node); 269 if (IS_ERR(imx7src->regmap)) { 270 dev_err(dev, "Unable to get imx7-src regmap"); 271 return PTR_ERR(imx7src->regmap); 272 } 273 regmap_attach_dev(dev, imx7src->regmap, &config); 274 275 imx7src->rcdev.owner = THIS_MODULE; 276 imx7src->rcdev.nr_resets = variant->signals_num; 277 imx7src->rcdev.ops = &variant->ops; 278 imx7src->rcdev.of_node = dev->of_node; 279 280 return devm_reset_controller_register(dev, &imx7src->rcdev); 281 } 282 283 static const struct of_device_id imx7_reset_dt_ids[] = { 284 { .compatible = "fsl,imx7d-src", .data = &variant_imx7 }, 285 { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq }, 286 { /* sentinel */ }, 287 }; 288 289 static struct platform_driver imx7_reset_driver = { 290 .probe = imx7_reset_probe, 291 .driver = { 292 .name = KBUILD_MODNAME, 293 .of_match_table = imx7_reset_dt_ids, 294 }, 295 }; 296 builtin_platform_driver(imx7_reset_driver); 297