1config ARCH_HAS_RESET_CONTROLLER 2 bool 3 4menuconfig RESET_CONTROLLER 5 bool "Reset Controller Support" 6 default y if ARCH_HAS_RESET_CONTROLLER 7 help 8 Generic Reset Controller support. 9 10 This framework is designed to abstract reset handling of devices 11 via GPIOs or SoC-internal reset controller modules. 12 13 If unsure, say no. 14 15if RESET_CONTROLLER 16 17config RESET_A10SR 18 tristate "Altera Arria10 System Resource Reset" 19 depends on MFD_ALTERA_A10SR 20 help 21 This option enables support for the external reset functions for 22 peripheral PHYs on the Altera Arria10 System Resource Chip. 23 24config RESET_ATH79 25 bool "AR71xx Reset Driver" if COMPILE_TEST 26 default ATH79 27 help 28 This enables the ATH79 reset controller driver that supports the 29 AR71xx SoC reset controller. 30 31config RESET_AXS10X 32 bool "AXS10x Reset Driver" if COMPILE_TEST 33 default ARC_PLAT_AXS10X 34 help 35 This enables the reset controller driver for AXS10x. 36 37config RESET_BERLIN 38 bool "Berlin Reset Driver" if COMPILE_TEST 39 default ARCH_BERLIN 40 help 41 This enables the reset controller driver for Marvell Berlin SoCs. 42 43config RESET_BRCMSTB 44 tristate "Broadcom STB reset controller" 45 depends on ARCH_BRCMSTB || COMPILE_TEST 46 default ARCH_BRCMSTB 47 help 48 This enables the reset controller driver for Broadcom STB SoCs using 49 a SUN_TOP_CTRL_SW_INIT style controller. 50 51config RESET_HSDK 52 bool "Synopsys HSDK Reset Driver" 53 depends on HAS_IOMEM 54 depends on ARC_SOC_HSDK || COMPILE_TEST 55 help 56 This enables the reset controller driver for HSDK board. 57 58config RESET_IMX7 59 bool "i.MX7/8 Reset Driver" if COMPILE_TEST 60 depends on HAS_IOMEM 61 default SOC_IMX7D || (ARM64 && ARCH_MXC) 62 select MFD_SYSCON 63 help 64 This enables the reset controller driver for i.MX7 SoCs. 65 66config RESET_LANTIQ 67 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 68 default SOC_TYPE_XWAY 69 help 70 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 71 72config RESET_LPC18XX 73 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 74 default ARCH_LPC18XX 75 help 76 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 77 78config RESET_MESON 79 bool "Meson Reset Driver" if COMPILE_TEST 80 default ARCH_MESON 81 help 82 This enables the reset driver for Amlogic Meson SoCs. 83 84config RESET_MESON_AUDIO_ARB 85 tristate "Meson Audio Memory Arbiter Reset Driver" 86 depends on ARCH_MESON || COMPILE_TEST 87 help 88 This enables the reset driver for Audio Memory Arbiter of 89 Amlogic's A113 based SoCs 90 91config RESET_OXNAS 92 bool 93 94config RESET_PISTACHIO 95 bool "Pistachio Reset Driver" if COMPILE_TEST 96 default MACH_PISTACHIO 97 help 98 This enables the reset driver for ImgTec Pistachio SoCs. 99 100config RESET_QCOM_AOSS 101 bool "Qcom AOSS Reset Driver" 102 depends on ARCH_QCOM || COMPILE_TEST 103 help 104 This enables the AOSS (always on subsystem) reset driver 105 for Qualcomm SDM845 SoCs. Say Y if you want to control 106 reset signals provided by AOSS for Modem, Venus, ADSP, 107 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 108 109config RESET_QCOM_PDC 110 tristate "Qualcomm PDC Reset Driver" 111 depends on ARCH_QCOM || COMPILE_TEST 112 help 113 This enables the PDC (Power Domain Controller) reset driver 114 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 115 to control reset signals provided by PDC for Modem, Compute, 116 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 117 118config RESET_SIMPLE 119 bool "Simple Reset Controller Driver" if COMPILE_TEST 120 default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED 121 help 122 This enables a simple reset controller driver for reset lines that 123 that can be asserted and deasserted by toggling bits in a contiguous, 124 exclusive register space. 125 126 Currently this driver supports: 127 - Altera SoCFPGAs 128 - ASPEED BMC SoCs 129 - RCC reset controller in STM32 MCUs 130 - Allwinner SoCs 131 - ZTE's zx2967 family 132 133config RESET_STM32MP157 134 bool "STM32MP157 Reset Driver" if COMPILE_TEST 135 default MACH_STM32MP157 136 help 137 This enables the RCC reset controller driver for STM32 MPUs. 138 139config RESET_SOCFPGA 140 bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA 141 default ARCH_SOCFPGA 142 select RESET_SIMPLE 143 help 144 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 145 driver gets initialized early during platform init calls. 146 147config RESET_SUNXI 148 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 149 default ARCH_SUNXI 150 select RESET_SIMPLE 151 help 152 This enables the reset driver for Allwinner SoCs. 153 154config RESET_TI_SCI 155 tristate "TI System Control Interface (TI-SCI) reset driver" 156 depends on TI_SCI_PROTOCOL 157 help 158 This enables the reset driver support over TI System Control Interface 159 available on some new TI's SoCs. If you wish to use reset resources 160 managed by the TI System Controller, say Y here. Otherwise, say N. 161 162config RESET_TI_SYSCON 163 tristate "TI SYSCON Reset Driver" 164 depends on HAS_IOMEM 165 select MFD_SYSCON 166 help 167 This enables the reset driver support for TI devices with 168 memory-mapped reset registers as part of a syscon device node. If 169 you wish to use the reset framework for such memory-mapped devices, 170 say Y here. Otherwise, say N. 171 172config RESET_UNIPHIER 173 tristate "Reset controller driver for UniPhier SoCs" 174 depends on ARCH_UNIPHIER || COMPILE_TEST 175 depends on OF && MFD_SYSCON 176 default ARCH_UNIPHIER 177 help 178 Support for reset controllers on UniPhier SoCs. 179 Say Y if you want to control reset signals provided by System Control 180 block, Media I/O block, Peripheral Block. 181 182config RESET_UNIPHIER_GLUE 183 tristate "Reset driver in glue layer for UniPhier SoCs" 184 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 185 default ARCH_UNIPHIER 186 select RESET_SIMPLE 187 help 188 Support for peripheral core reset included in its own glue layer 189 on UniPhier SoCs. Say Y if you want to control reset signals 190 provided by the glue layer. 191 192config RESET_ZYNQ 193 bool "ZYNQ Reset Driver" if COMPILE_TEST 194 default ARCH_ZYNQ 195 help 196 This enables the reset controller driver for Xilinx Zynq SoCs. 197 198source "drivers/reset/sti/Kconfig" 199source "drivers/reset/hisilicon/Kconfig" 200source "drivers/reset/tegra/Kconfig" 201 202endif 203