1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 bool "Berlin Reset Driver" if COMPILE_TEST 47 default ARCH_BERLIN 48 help 49 This enables the reset controller driver for Marvell Berlin SoCs. 50 51config RESET_BRCMSTB 52 tristate "Broadcom STB reset controller" 53 depends on ARCH_BRCMSTB || COMPILE_TEST 54 default ARCH_BRCMSTB 55 help 56 This enables the reset controller driver for Broadcom STB SoCs using 57 a SUN_TOP_CTRL_SW_INIT style controller. 58 59config RESET_BRCMSTB_RESCAL 60 bool "Broadcom STB RESCAL reset controller" 61 depends on HAS_IOMEM 62 default ARCH_BRCMSTB || COMPILE_TEST 63 help 64 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 65 BCM7216. 66 67config RESET_HSDK 68 bool "Synopsys HSDK Reset Driver" 69 depends on HAS_IOMEM 70 depends on ARC_SOC_HSDK || COMPILE_TEST 71 help 72 This enables the reset controller driver for HSDK board. 73 74config RESET_IMX7 75 tristate "i.MX7/8 Reset Driver" 76 depends on HAS_IOMEM 77 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 78 default y if SOC_IMX7D 79 select MFD_SYSCON 80 help 81 This enables the reset controller driver for i.MX7 SoCs. 82 83config RESET_INTEL_GW 84 bool "Intel Reset Controller Driver" 85 depends on OF && HAS_IOMEM 86 select REGMAP_MMIO 87 help 88 This enables the reset controller driver for Intel Gateway SoCs. 89 Say Y to control the reset signals provided by reset controller. 90 Otherwise, say N. 91 92config RESET_LANTIQ 93 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 94 default SOC_TYPE_XWAY 95 help 96 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 97 98config RESET_LPC18XX 99 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 100 default ARCH_LPC18XX 101 help 102 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 103 104config RESET_MESON 105 bool "Meson Reset Driver" if COMPILE_TEST 106 default ARCH_MESON 107 help 108 This enables the reset driver for Amlogic Meson SoCs. 109 110config RESET_MESON_AUDIO_ARB 111 tristate "Meson Audio Memory Arbiter Reset Driver" 112 depends on ARCH_MESON || COMPILE_TEST 113 help 114 This enables the reset driver for Audio Memory Arbiter of 115 Amlogic's A113 based SoCs 116 117config RESET_NPCM 118 bool "NPCM BMC Reset Driver" if COMPILE_TEST 119 default ARCH_NPCM 120 help 121 This enables the reset controller driver for Nuvoton NPCM 122 BMC SoCs. 123 124config RESET_OXNAS 125 bool 126 127config RESET_PISTACHIO 128 bool "Pistachio Reset Driver" if COMPILE_TEST 129 default MACH_PISTACHIO 130 help 131 This enables the reset driver for ImgTec Pistachio SoCs. 132 133config RESET_QCOM_AOSS 134 tristate "Qcom AOSS Reset Driver" 135 depends on ARCH_QCOM || COMPILE_TEST 136 help 137 This enables the AOSS (always on subsystem) reset driver 138 for Qualcomm SDM845 SoCs. Say Y if you want to control 139 reset signals provided by AOSS for Modem, Venus, ADSP, 140 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 141 142config RESET_QCOM_PDC 143 tristate "Qualcomm PDC Reset Driver" 144 depends on ARCH_QCOM || COMPILE_TEST 145 help 146 This enables the PDC (Power Domain Controller) reset driver 147 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 148 to control reset signals provided by PDC for Modem, Compute, 149 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 150 151config RESET_RASPBERRYPI 152 tristate "Raspberry Pi 4 Firmware Reset Driver" 153 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 154 default USB_XHCI_PCI 155 help 156 Raspberry Pi 4's co-processor controls some of the board's HW 157 initialization process, but it's up to Linux to trigger it when 158 relevant. This driver provides a reset controller capable of 159 interfacing with RPi4's co-processor and model these firmware 160 initialization routines as reset lines. 161 162config RESET_SCMI 163 tristate "Reset driver controlled via ARM SCMI interface" 164 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 165 default ARM_SCMI_PROTOCOL 166 help 167 This driver provides support for reset signal/domains that are 168 controlled by firmware that implements the SCMI interface. 169 170 This driver uses SCMI Message Protocol to interact with the 171 firmware controlling all the reset signals. 172 173config RESET_SIMPLE 174 bool "Simple Reset Controller Driver" if COMPILE_TEST 175 default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC 176 help 177 This enables a simple reset controller driver for reset lines that 178 that can be asserted and deasserted by toggling bits in a contiguous, 179 exclusive register space. 180 181 Currently this driver supports: 182 - Altera SoCFPGAs 183 - ASPEED BMC SoCs 184 - Bitmain BM1880 SoC 185 - Realtek SoCs 186 - RCC reset controller in STM32 MCUs 187 - Allwinner SoCs 188 - ZTE's zx2967 family 189 190config RESET_STM32MP157 191 bool "STM32MP157 Reset Driver" if COMPILE_TEST 192 default MACH_STM32MP157 193 help 194 This enables the RCC reset controller driver for STM32 MPUs. 195 196config RESET_SOCFPGA 197 bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA 198 default ARCH_SOCFPGA 199 select RESET_SIMPLE 200 help 201 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 202 driver gets initialized early during platform init calls. 203 204config RESET_SUNXI 205 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 206 default ARCH_SUNXI 207 select RESET_SIMPLE 208 help 209 This enables the reset driver for Allwinner SoCs. 210 211config RESET_TI_SCI 212 tristate "TI System Control Interface (TI-SCI) reset driver" 213 depends on TI_SCI_PROTOCOL 214 help 215 This enables the reset driver support over TI System Control Interface 216 available on some new TI's SoCs. If you wish to use reset resources 217 managed by the TI System Controller, say Y here. Otherwise, say N. 218 219config RESET_TI_SYSCON 220 tristate "TI SYSCON Reset Driver" 221 depends on HAS_IOMEM 222 select MFD_SYSCON 223 help 224 This enables the reset driver support for TI devices with 225 memory-mapped reset registers as part of a syscon device node. If 226 you wish to use the reset framework for such memory-mapped devices, 227 say Y here. Otherwise, say N. 228 229config RESET_UNIPHIER 230 tristate "Reset controller driver for UniPhier SoCs" 231 depends on ARCH_UNIPHIER || COMPILE_TEST 232 depends on OF && MFD_SYSCON 233 default ARCH_UNIPHIER 234 help 235 Support for reset controllers on UniPhier SoCs. 236 Say Y if you want to control reset signals provided by System Control 237 block, Media I/O block, Peripheral Block. 238 239config RESET_UNIPHIER_GLUE 240 tristate "Reset driver in glue layer for UniPhier SoCs" 241 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 242 default ARCH_UNIPHIER 243 select RESET_SIMPLE 244 help 245 Support for peripheral core reset included in its own glue layer 246 on UniPhier SoCs. Say Y if you want to control reset signals 247 provided by the glue layer. 248 249config RESET_ZYNQ 250 bool "ZYNQ Reset Driver" if COMPILE_TEST 251 default ARCH_ZYNQ 252 help 253 This enables the reset controller driver for Xilinx Zynq SoCs. 254 255source "drivers/reset/sti/Kconfig" 256source "drivers/reset/hisilicon/Kconfig" 257source "drivers/reset/tegra/Kconfig" 258 259endif 260