1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BERLIN 39 bool "Berlin Reset Driver" if COMPILE_TEST 40 default ARCH_BERLIN 41 help 42 This enables the reset controller driver for Marvell Berlin SoCs. 43 44config RESET_BRCMSTB 45 tristate "Broadcom STB reset controller" 46 depends on ARCH_BRCMSTB || COMPILE_TEST 47 default ARCH_BRCMSTB 48 help 49 This enables the reset controller driver for Broadcom STB SoCs using 50 a SUN_TOP_CTRL_SW_INIT style controller. 51 52config RESET_HSDK 53 bool "Synopsys HSDK Reset Driver" 54 depends on HAS_IOMEM 55 depends on ARC_SOC_HSDK || COMPILE_TEST 56 help 57 This enables the reset controller driver for HSDK board. 58 59config RESET_IMX7 60 bool "i.MX7/8 Reset Driver" if COMPILE_TEST 61 depends on HAS_IOMEM 62 default SOC_IMX7D || (ARM64 && ARCH_MXC) 63 select MFD_SYSCON 64 help 65 This enables the reset controller driver for i.MX7 SoCs. 66 67config RESET_LANTIQ 68 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 69 default SOC_TYPE_XWAY 70 help 71 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 72 73config RESET_LPC18XX 74 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 75 default ARCH_LPC18XX 76 help 77 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 78 79config RESET_MESON 80 bool "Meson Reset Driver" if COMPILE_TEST 81 default ARCH_MESON 82 help 83 This enables the reset driver for Amlogic Meson SoCs. 84 85config RESET_MESON_AUDIO_ARB 86 tristate "Meson Audio Memory Arbiter Reset Driver" 87 depends on ARCH_MESON || COMPILE_TEST 88 help 89 This enables the reset driver for Audio Memory Arbiter of 90 Amlogic's A113 based SoCs 91 92config RESET_OXNAS 93 bool 94 95config RESET_PISTACHIO 96 bool "Pistachio Reset Driver" if COMPILE_TEST 97 default MACH_PISTACHIO 98 help 99 This enables the reset driver for ImgTec Pistachio SoCs. 100 101config RESET_QCOM_AOSS 102 bool "Qcom AOSS Reset Driver" 103 depends on ARCH_QCOM || COMPILE_TEST 104 help 105 This enables the AOSS (always on subsystem) reset driver 106 for Qualcomm SDM845 SoCs. Say Y if you want to control 107 reset signals provided by AOSS for Modem, Venus, ADSP, 108 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 109 110config RESET_QCOM_PDC 111 tristate "Qualcomm PDC Reset Driver" 112 depends on ARCH_QCOM || COMPILE_TEST 113 help 114 This enables the PDC (Power Domain Controller) reset driver 115 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 116 to control reset signals provided by PDC for Modem, Compute, 117 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 118 119config RESET_SCMI 120 tristate "Reset driver controlled via ARM SCMI interface" 121 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 122 default ARM_SCMI_PROTOCOL 123 help 124 This driver provides support for reset signal/domains that are 125 controlled by firmware that implements the SCMI interface. 126 127 This driver uses SCMI Message Protocol to interact with the 128 firmware controlling all the reset signals. 129 130config RESET_SIMPLE 131 bool "Simple Reset Controller Driver" if COMPILE_TEST 132 default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARC 133 help 134 This enables a simple reset controller driver for reset lines that 135 that can be asserted and deasserted by toggling bits in a contiguous, 136 exclusive register space. 137 138 Currently this driver supports: 139 - Altera SoCFPGAs 140 - ASPEED BMC SoCs 141 - RCC reset controller in STM32 MCUs 142 - Allwinner SoCs 143 - ZTE's zx2967 family 144 - Bitmain BM1880 SoC 145 146config RESET_STM32MP157 147 bool "STM32MP157 Reset Driver" if COMPILE_TEST 148 default MACH_STM32MP157 149 help 150 This enables the RCC reset controller driver for STM32 MPUs. 151 152config RESET_SOCFPGA 153 bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA 154 default ARCH_SOCFPGA 155 select RESET_SIMPLE 156 help 157 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 158 driver gets initialized early during platform init calls. 159 160config RESET_SUNXI 161 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 162 default ARCH_SUNXI 163 select RESET_SIMPLE 164 help 165 This enables the reset driver for Allwinner SoCs. 166 167config RESET_TI_SCI 168 tristate "TI System Control Interface (TI-SCI) reset driver" 169 depends on TI_SCI_PROTOCOL 170 help 171 This enables the reset driver support over TI System Control Interface 172 available on some new TI's SoCs. If you wish to use reset resources 173 managed by the TI System Controller, say Y here. Otherwise, say N. 174 175config RESET_TI_SYSCON 176 tristate "TI SYSCON Reset Driver" 177 depends on HAS_IOMEM 178 select MFD_SYSCON 179 help 180 This enables the reset driver support for TI devices with 181 memory-mapped reset registers as part of a syscon device node. If 182 you wish to use the reset framework for such memory-mapped devices, 183 say Y here. Otherwise, say N. 184 185config RESET_UNIPHIER 186 tristate "Reset controller driver for UniPhier SoCs" 187 depends on ARCH_UNIPHIER || COMPILE_TEST 188 depends on OF && MFD_SYSCON 189 default ARCH_UNIPHIER 190 help 191 Support for reset controllers on UniPhier SoCs. 192 Say Y if you want to control reset signals provided by System Control 193 block, Media I/O block, Peripheral Block. 194 195config RESET_UNIPHIER_GLUE 196 tristate "Reset driver in glue layer for UniPhier SoCs" 197 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 198 default ARCH_UNIPHIER 199 select RESET_SIMPLE 200 help 201 Support for peripheral core reset included in its own glue layer 202 on UniPhier SoCs. Say Y if you want to control reset signals 203 provided by the glue layer. 204 205config RESET_ZYNQ 206 bool "ZYNQ Reset Driver" if COMPILE_TEST 207 default ARCH_ZYNQ 208 help 209 This enables the reset controller driver for Xilinx Zynq SoCs. 210 211source "drivers/reset/sti/Kconfig" 212source "drivers/reset/hisilicon/Kconfig" 213source "drivers/reset/tegra/Kconfig" 214 215endif 216