1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER 361fc4131SPhilipp Zabel bool 461fc4131SPhilipp Zabel 561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER 661fc4131SPhilipp Zabel bool "Reset Controller Support" 761fc4131SPhilipp Zabel default y if ARCH_HAS_RESET_CONTROLLER 861fc4131SPhilipp Zabel help 961fc4131SPhilipp Zabel Generic Reset Controller support. 1061fc4131SPhilipp Zabel 1161fc4131SPhilipp Zabel This framework is designed to abstract reset handling of devices 1261fc4131SPhilipp Zabel via GPIOs or SoC-internal reset controller modules. 1361fc4131SPhilipp Zabel 1461fc4131SPhilipp Zabel If unsure, say no. 15e5d76075SStephen Gallimore 16998cd463SMasahiro Yamadaif RESET_CONTROLLER 17998cd463SMasahiro Yamada 1862700682SThor Thayerconfig RESET_A10SR 1962700682SThor Thayer tristate "Altera Arria10 System Resource Reset" 20*af19f193SPhilipp Zabel depends on MFD_ALTERA_A10SR || COMPILE_TEST 2162700682SThor Thayer help 2262700682SThor Thayer This option enables support for the external reset functions for 2362700682SThor Thayer peripheral PHYs on the Altera Arria10 System Resource Chip. 2462700682SThor Thayer 25e27b4a6eSPhilipp Zabelconfig RESET_ATH79 26e27b4a6eSPhilipp Zabel bool "AR71xx Reset Driver" if COMPILE_TEST 27e27b4a6eSPhilipp Zabel default ATH79 28e27b4a6eSPhilipp Zabel help 29e27b4a6eSPhilipp Zabel This enables the ATH79 reset controller driver that supports the 30e27b4a6eSPhilipp Zabel AR71xx SoC reset controller. 31e27b4a6eSPhilipp Zabel 3237634923SEugeniy Paltsevconfig RESET_AXS10X 3337634923SEugeniy Paltsev bool "AXS10x Reset Driver" if COMPILE_TEST 3437634923SEugeniy Paltsev default ARC_PLAT_AXS10X 3537634923SEugeniy Paltsev help 3637634923SEugeniy Paltsev This enables the reset controller driver for AXS10x. 3737634923SEugeniy Paltsev 38aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345 39aac02543SÁlvaro Fernández Rojas bool "BCM6345 Reset Controller" 40aac02543SÁlvaro Fernández Rojas depends on BMIPS_GENERIC || COMPILE_TEST 41aac02543SÁlvaro Fernández Rojas default BMIPS_GENERIC 42aac02543SÁlvaro Fernández Rojas help 43aac02543SÁlvaro Fernández Rojas This enables the reset controller driver for BCM6345 SoCs. 44aac02543SÁlvaro Fernández Rojas 4570d467eaSPhilipp Zabelconfig RESET_BERLIN 465e787cdfSJisheng Zhang tristate "Berlin Reset Driver" 475e787cdfSJisheng Zhang depends on ARCH_BERLIN || COMPILE_TEST 485e787cdfSJisheng Zhang default m if ARCH_BERLIN 4970d467eaSPhilipp Zabel help 5070d467eaSPhilipp Zabel This enables the reset controller driver for Marvell Berlin SoCs. 5170d467eaSPhilipp Zabel 5277750bc0SFlorian Fainelliconfig RESET_BRCMSTB 5377750bc0SFlorian Fainelli tristate "Broadcom STB reset controller" 5477750bc0SFlorian Fainelli depends on ARCH_BRCMSTB || COMPILE_TEST 5577750bc0SFlorian Fainelli default ARCH_BRCMSTB 5677750bc0SFlorian Fainelli help 5777750bc0SFlorian Fainelli This enables the reset controller driver for Broadcom STB SoCs using 5877750bc0SFlorian Fainelli a SUN_TOP_CTRL_SW_INIT style controller. 5977750bc0SFlorian Fainelli 604cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL 615694ca29SFlorian Fainelli tristate "Broadcom STB RESCAL reset controller" 627fbcc535SBrendan Higgins depends on HAS_IOMEM 6342f6a76fSGeert Uytterhoeven depends on ARCH_BRCMSTB || COMPILE_TEST 6442f6a76fSGeert Uytterhoeven default ARCH_BRCMSTB 654cf176e5SJim Quinlan help 664cf176e5SJim Quinlan This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 674cf176e5SJim Quinlan BCM7216. 684cf176e5SJim Quinlan 6913541226SVineet Guptaconfig RESET_HSDK 7013541226SVineet Gupta bool "Synopsys HSDK Reset Driver" 712d48a237SThomas Meyer depends on HAS_IOMEM 72544e3bf4SGeert Uytterhoeven depends on ARC_SOC_HSDK || COMPILE_TEST 73e0be864fSEugeniy Paltsev help 7413541226SVineet Gupta This enables the reset controller driver for HSDK board. 75e0be864fSEugeniy Paltsev 76abf97755SAndrey Smirnovconfig RESET_IMX7 77a442abbbSAnson Huang tristate "i.MX7/8 Reset Driver" 788fa56620SMasahiro Yamada depends on HAS_IOMEM 79a442abbbSAnson Huang depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 80a442abbbSAnson Huang default y if SOC_IMX7D 81abf97755SAndrey Smirnov select MFD_SYSCON 82abf97755SAndrey Smirnov help 83abf97755SAndrey Smirnov This enables the reset controller driver for i.MX7 SoCs. 84abf97755SAndrey Smirnov 85c9aef213SDilip Kotaconfig RESET_INTEL_GW 86c9aef213SDilip Kota bool "Intel Reset Controller Driver" 876ab9d621SGeert Uytterhoeven depends on X86 || COMPILE_TEST 88b460e0a9SBrendan Higgins depends on OF && HAS_IOMEM 89c9aef213SDilip Kota select REGMAP_MMIO 90c9aef213SDilip Kota help 91c9aef213SDilip Kota This enables the reset controller driver for Intel Gateway SoCs. 92c9aef213SDilip Kota Say Y to control the reset signals provided by reset controller. 93c9aef213SDilip Kota Otherwise, say N. 94c9aef213SDilip Kota 955a2308daSDamien Le Moalconfig RESET_K210 965a2308daSDamien Le Moal bool "Reset controller driver for Canaan Kendryte K210 SoC" 975a2308daSDamien Le Moal depends on (SOC_CANAAN || COMPILE_TEST) && OF 985a2308daSDamien Le Moal select MFD_SYSCON 995a2308daSDamien Le Moal default SOC_CANAAN 1005a2308daSDamien Le Moal help 1015a2308daSDamien Le Moal Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 1025a2308daSDamien Le Moal Say Y if you want to control reset signals provided by this 1035a2308daSDamien Le Moal controller. 1045a2308daSDamien Le Moal 10579797b6fSMartin Blumenstinglconfig RESET_LANTIQ 10679797b6fSMartin Blumenstingl bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 10779797b6fSMartin Blumenstingl default SOC_TYPE_XWAY 10879797b6fSMartin Blumenstingl help 10979797b6fSMartin Blumenstingl This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 11079797b6fSMartin Blumenstingl 111cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX 112cd7f4b81SPhilipp Zabel bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 113cd7f4b81SPhilipp Zabel default ARCH_LPC18XX 114cd7f4b81SPhilipp Zabel help 115cd7f4b81SPhilipp Zabel This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 116cd7f4b81SPhilipp Zabel 117453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5 118b6b95858SClément Léger tristate "Microchip Sparx5 reset driver" 1198c81620aSHoratiu Vultur depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 120453ed428SSteen Hegelund default y if SPARX5_SWITCH 121453ed428SSteen Hegelund select MFD_SYSCON 122453ed428SSteen Hegelund help 123453ed428SSteen Hegelund This driver supports switch core reset for the Microchip Sparx5 SoC. 124453ed428SSteen Hegelund 12544336c24SPhilipp Zabelconfig RESET_MESON 1263bfe8933SNeil Armstrong tristate "Meson Reset Driver" 1273bfe8933SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 12844336c24SPhilipp Zabel default ARCH_MESON 12944336c24SPhilipp Zabel help 13044336c24SPhilipp Zabel This enables the reset driver for Amlogic Meson SoCs. 13144336c24SPhilipp Zabel 132d903779bSJerome Brunetconfig RESET_MESON_AUDIO_ARB 133d903779bSJerome Brunet tristate "Meson Audio Memory Arbiter Reset Driver" 134d903779bSJerome Brunet depends on ARCH_MESON || COMPILE_TEST 135d903779bSJerome Brunet help 136d903779bSJerome Brunet This enables the reset driver for Audio Memory Arbiter of 137d903779bSJerome Brunet Amlogic's A113 based SoCs 138d903779bSJerome Brunet 1399c81b2ccSTomer Maimonconfig RESET_NPCM 1409c81b2ccSTomer Maimon bool "NPCM BMC Reset Driver" if COMPILE_TEST 1419c81b2ccSTomer Maimon default ARCH_NPCM 1429c81b2ccSTomer Maimon help 1439c81b2ccSTomer Maimon This enables the reset controller driver for Nuvoton NPCM 1449c81b2ccSTomer Maimon BMC SoCs. 1459c81b2ccSTomer Maimon 1466e667facSNeil Armstrongconfig RESET_OXNAS 1476e667facSNeil Armstrong bool 1486e667facSNeil Armstrong 149fab3f730SPhilipp Zabelconfig RESET_PISTACHIO 1504af16070SGeert Uytterhoeven bool "Pistachio Reset Driver" 1514af16070SGeert Uytterhoeven depends on MIPS || COMPILE_TEST 152fab3f730SPhilipp Zabel help 153fab3f730SPhilipp Zabel This enables the reset driver for ImgTec Pistachio SoCs. 154fab3f730SPhilipp Zabel 1555ecb0651SSibi Sankarconfig RESET_QCOM_AOSS 156e2d5e833SJohn Stultz tristate "Qcom AOSS Reset Driver" 1575ecb0651SSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 1585ecb0651SSibi Sankar help 1595ecb0651SSibi Sankar This enables the AOSS (always on subsystem) reset driver 1605ecb0651SSibi Sankar for Qualcomm SDM845 SoCs. Say Y if you want to control 1615ecb0651SSibi Sankar reset signals provided by AOSS for Modem, Venus, ADSP, 1625ecb0651SSibi Sankar GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 1635ecb0651SSibi Sankar 164eea2926bSSibi Sankarconfig RESET_QCOM_PDC 165eea2926bSSibi Sankar tristate "Qualcomm PDC Reset Driver" 166eea2926bSSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 167eea2926bSSibi Sankar help 168eea2926bSSibi Sankar This enables the PDC (Power Domain Controller) reset driver 169eea2926bSSibi Sankar for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 170eea2926bSSibi Sankar to control reset signals provided by PDC for Modem, Compute, 171eea2926bSSibi Sankar Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 172eea2926bSSibi Sankar 173abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI 174abffc82aSNicolas Saenz Julienne tristate "Raspberry Pi 4 Firmware Reset Driver" 175abffc82aSNicolas Saenz Julienne depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 176abffc82aSNicolas Saenz Julienne default USB_XHCI_PCI 177abffc82aSNicolas Saenz Julienne help 178abffc82aSNicolas Saenz Julienne Raspberry Pi 4's co-processor controls some of the board's HW 179abffc82aSNicolas Saenz Julienne initialization process, but it's up to Linux to trigger it when 180abffc82aSNicolas Saenz Julienne relevant. This driver provides a reset controller capable of 181abffc82aSNicolas Saenz Julienne interfacing with RPi4's co-processor and model these firmware 182abffc82aSNicolas Saenz Julienne initialization routines as reset lines. 183abffc82aSNicolas Saenz Julienne 184bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL 185bee08559SBiju Das tristate "Renesas RZ/G2L USBPHY control driver" 1869fe7dd4eSLad Prabhakar depends on ARCH_RZG2L || COMPILE_TEST 187bee08559SBiju Das help 188bee08559SBiju Das Support for USBPHY Control found on RZ/G2L family. It mainly 189bee08559SBiju Das controls reset and power down of the USB/PHY. 190bee08559SBiju Das 191c8ae9c2dSSudeep Hollaconfig RESET_SCMI 192c8ae9c2dSSudeep Holla tristate "Reset driver controlled via ARM SCMI interface" 193c8ae9c2dSSudeep Holla depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 194c8ae9c2dSSudeep Holla default ARM_SCMI_PROTOCOL 195c8ae9c2dSSudeep Holla help 196c8ae9c2dSSudeep Holla This driver provides support for reset signal/domains that are 197c8ae9c2dSSudeep Holla controlled by firmware that implements the SCMI interface. 198c8ae9c2dSSudeep Holla 199c8ae9c2dSSudeep Holla This driver uses SCMI Message Protocol to interact with the 200c8ae9c2dSSudeep Holla firmware controlling all the reset signals. 201c8ae9c2dSSudeep Holla 20281c22ad0SPhilipp Zabelconfig RESET_SIMPLE 20318d1909bSBen Dooks bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 2044a9a1a56SKrzysztof Kozlowski default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 20581c22ad0SPhilipp Zabel help 20681c22ad0SPhilipp Zabel This enables a simple reset controller driver for reset lines that 20781c22ad0SPhilipp Zabel that can be asserted and deasserted by toggling bits in a contiguous, 20881c22ad0SPhilipp Zabel exclusive register space. 20981c22ad0SPhilipp Zabel 2101d7592f8SJoel Stanley Currently this driver supports: 2111d7592f8SJoel Stanley - Altera SoCFPGAs 2121d7592f8SJoel Stanley - ASPEED BMC SoCs 2135ac33eebSAndreas Färber - Bitmain BM1880 SoC 2143ab831e5SAndreas Färber - Realtek SoCs 2151d7592f8SJoel Stanley - RCC reset controller in STM32 MCUs 2161d7592f8SJoel Stanley - Allwinner SoCs 217e4d368e0SGreentime Hu - SiFive FU740 SoCs 2187e0e901dSPhilipp Zabel 219b3ca9888SDinh Nguyenconfig RESET_SOCFPGA 220225c13f0SKrzysztof Kozlowski bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 221225c13f0SKrzysztof Kozlowski default ARM && ARCH_INTEL_SOCFPGA 222b3ca9888SDinh Nguyen select RESET_SIMPLE 223b3ca9888SDinh Nguyen help 224b3ca9888SDinh Nguyen This enables the reset driver for the SoCFPGA ARMv7 platforms. This 225b3ca9888SDinh Nguyen driver gets initialized early during platform init calls. 226b3ca9888SDinh Nguyen 2270be3a159SEmil Renner Berthingconfig RESET_STARFIVE_JH7100 2280be3a159SEmil Renner Berthing bool "StarFive JH7100 Reset Driver" 2290be3a159SEmil Renner Berthing depends on SOC_STARFIVE || COMPILE_TEST 2300be3a159SEmil Renner Berthing default SOC_STARFIVE 2310be3a159SEmil Renner Berthing help 2320be3a159SEmil Renner Berthing This enables the reset controller driver for the StarFive JH7100 SoC. 2330be3a159SEmil Renner Berthing 2340ae08419SPhilipp Zabelconfig RESET_SUNXI 2350ae08419SPhilipp Zabel bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 2360ae08419SPhilipp Zabel default ARCH_SUNXI 237e13c205aSPhilipp Zabel select RESET_SIMPLE 2380ae08419SPhilipp Zabel help 2390ae08419SPhilipp Zabel This enables the reset driver for Allwinner SoCs. 2400ae08419SPhilipp Zabel 24128df169bSAndrew F. Davisconfig RESET_TI_SCI 24228df169bSAndrew F. Davis tristate "TI System Control Interface (TI-SCI) reset driver" 243a6af5041SPhilipp Zabel depends on TI_SCI_PROTOCOL || COMPILE_TEST 24428df169bSAndrew F. Davis help 24528df169bSAndrew F. Davis This enables the reset driver support over TI System Control Interface 24628df169bSAndrew F. Davis available on some new TI's SoCs. If you wish to use reset resources 24728df169bSAndrew F. Davis managed by the TI System Controller, say Y here. Otherwise, say N. 24828df169bSAndrew F. Davis 249dd9bf863SSuman Annaconfig RESET_TI_SYSCON 250cc7c2bb1SAndrew F. Davis tristate "TI SYSCON Reset Driver" 251cc7c2bb1SAndrew F. Davis depends on HAS_IOMEM 252cc7c2bb1SAndrew F. Davis select MFD_SYSCON 253cc7c2bb1SAndrew F. Davis help 254cc7c2bb1SAndrew F. Davis This enables the reset driver support for TI devices with 255cc7c2bb1SAndrew F. Davis memory-mapped reset registers as part of a syscon device node. If 256cc7c2bb1SAndrew F. Davis you wish to use the reset framework for such memory-mapped devices, 257cc7c2bb1SAndrew F. Davis say Y here. Otherwise, say N. 258cc7c2bb1SAndrew F. Davis 2595cd3921dSRobert Markoconfig RESET_TN48M_CPLD 2605cd3921dSRobert Marko tristate "Delta Networks TN48M switch CPLD reset controller" 2615cd3921dSRobert Marko depends on MFD_TN48M_CPLD || COMPILE_TEST 2625cd3921dSRobert Marko default MFD_TN48M_CPLD 2635cd3921dSRobert Marko help 2645cd3921dSRobert Marko This enables the reset controller driver for the Delta TN48M CPLD. 2655cd3921dSRobert Marko It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 2665cd3921dSRobert Marko switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 2675cd3921dSRobert Marko Microchip PD69200 PoE PSE controller. 2685cd3921dSRobert Marko 2695cd3921dSRobert Marko This driver can also be built as a module. If so, the module will be 2705cd3921dSRobert Marko called reset-tn48m. 2715cd3921dSRobert Marko 27254e991b5SMasahiro Yamadaconfig RESET_UNIPHIER 27354e991b5SMasahiro Yamada tristate "Reset controller driver for UniPhier SoCs" 27454e991b5SMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 27554e991b5SMasahiro Yamada depends on OF && MFD_SYSCON 27654e991b5SMasahiro Yamada default ARCH_UNIPHIER 27754e991b5SMasahiro Yamada help 27854e991b5SMasahiro Yamada Support for reset controllers on UniPhier SoCs. 27954e991b5SMasahiro Yamada Say Y if you want to control reset signals provided by System Control 28054e991b5SMasahiro Yamada block, Media I/O block, Peripheral Block. 28154e991b5SMasahiro Yamada 2823eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE 2833eb8f765SKunihiko Hayashi tristate "Reset driver in glue layer for UniPhier SoCs" 284499fef09SKunihiko Hayashi depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 285499fef09SKunihiko Hayashi default ARCH_UNIPHIER 286499fef09SKunihiko Hayashi select RESET_SIMPLE 287499fef09SKunihiko Hayashi help 2883eb8f765SKunihiko Hayashi Support for peripheral core reset included in its own glue layer 2893eb8f765SKunihiko Hayashi on UniPhier SoCs. Say Y if you want to control reset signals 2903eb8f765SKunihiko Hayashi provided by the glue layer. 291499fef09SKunihiko Hayashi 2926f51b860SPhilipp Zabelconfig RESET_ZYNQ 2936f51b860SPhilipp Zabel bool "ZYNQ Reset Driver" if COMPILE_TEST 2946f51b860SPhilipp Zabel default ARCH_ZYNQ 2956f51b860SPhilipp Zabel help 2966f51b860SPhilipp Zabel This enables the reset controller driver for Xilinx Zynq SoCs. 2976f51b860SPhilipp Zabel 298e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig" 299f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig" 300dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig" 301998cd463SMasahiro Yamada 302998cd463SMasahiro Yamadaendif 303