1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER 361fc4131SPhilipp Zabel bool 461fc4131SPhilipp Zabel 561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER 661fc4131SPhilipp Zabel bool "Reset Controller Support" 761fc4131SPhilipp Zabel default y if ARCH_HAS_RESET_CONTROLLER 861fc4131SPhilipp Zabel help 961fc4131SPhilipp Zabel Generic Reset Controller support. 1061fc4131SPhilipp Zabel 1161fc4131SPhilipp Zabel This framework is designed to abstract reset handling of devices 1261fc4131SPhilipp Zabel via GPIOs or SoC-internal reset controller modules. 1361fc4131SPhilipp Zabel 1461fc4131SPhilipp Zabel If unsure, say no. 15e5d76075SStephen Gallimore 16998cd463SMasahiro Yamadaif RESET_CONTROLLER 17998cd463SMasahiro Yamada 1862700682SThor Thayerconfig RESET_A10SR 1962700682SThor Thayer tristate "Altera Arria10 System Resource Reset" 20af19f193SPhilipp Zabel depends on MFD_ALTERA_A10SR || COMPILE_TEST 2162700682SThor Thayer help 2262700682SThor Thayer This option enables support for the external reset functions for 2362700682SThor Thayer peripheral PHYs on the Altera Arria10 System Resource Chip. 2462700682SThor Thayer 25e27b4a6eSPhilipp Zabelconfig RESET_ATH79 26e27b4a6eSPhilipp Zabel bool "AR71xx Reset Driver" if COMPILE_TEST 27e27b4a6eSPhilipp Zabel default ATH79 28e27b4a6eSPhilipp Zabel help 29e27b4a6eSPhilipp Zabel This enables the ATH79 reset controller driver that supports the 30e27b4a6eSPhilipp Zabel AR71xx SoC reset controller. 31e27b4a6eSPhilipp Zabel 3237634923SEugeniy Paltsevconfig RESET_AXS10X 3337634923SEugeniy Paltsev bool "AXS10x Reset Driver" if COMPILE_TEST 3437634923SEugeniy Paltsev default ARC_PLAT_AXS10X 3537634923SEugeniy Paltsev help 3637634923SEugeniy Paltsev This enables the reset controller driver for AXS10x. 3737634923SEugeniy Paltsev 38aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345 39aac02543SÁlvaro Fernández Rojas bool "BCM6345 Reset Controller" 40aac02543SÁlvaro Fernández Rojas depends on BMIPS_GENERIC || COMPILE_TEST 41aac02543SÁlvaro Fernández Rojas default BMIPS_GENERIC 42aac02543SÁlvaro Fernández Rojas help 43aac02543SÁlvaro Fernández Rojas This enables the reset controller driver for BCM6345 SoCs. 44aac02543SÁlvaro Fernández Rojas 4570d467eaSPhilipp Zabelconfig RESET_BERLIN 465e787cdfSJisheng Zhang tristate "Berlin Reset Driver" 475e787cdfSJisheng Zhang depends on ARCH_BERLIN || COMPILE_TEST 485e787cdfSJisheng Zhang default m if ARCH_BERLIN 4970d467eaSPhilipp Zabel help 5070d467eaSPhilipp Zabel This enables the reset controller driver for Marvell Berlin SoCs. 5170d467eaSPhilipp Zabel 5277750bc0SFlorian Fainelliconfig RESET_BRCMSTB 5377750bc0SFlorian Fainelli tristate "Broadcom STB reset controller" 5477750bc0SFlorian Fainelli depends on ARCH_BRCMSTB || COMPILE_TEST 5577750bc0SFlorian Fainelli default ARCH_BRCMSTB 5677750bc0SFlorian Fainelli help 5777750bc0SFlorian Fainelli This enables the reset controller driver for Broadcom STB SoCs using 5877750bc0SFlorian Fainelli a SUN_TOP_CTRL_SW_INIT style controller. 5977750bc0SFlorian Fainelli 604cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL 615694ca29SFlorian Fainelli tristate "Broadcom STB RESCAL reset controller" 627fbcc535SBrendan Higgins depends on HAS_IOMEM 6342f6a76fSGeert Uytterhoeven depends on ARCH_BRCMSTB || COMPILE_TEST 6442f6a76fSGeert Uytterhoeven default ARCH_BRCMSTB 654cf176e5SJim Quinlan help 664cf176e5SJim Quinlan This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 674cf176e5SJim Quinlan BCM7216. 684cf176e5SJim Quinlan 6913541226SVineet Guptaconfig RESET_HSDK 7013541226SVineet Gupta bool "Synopsys HSDK Reset Driver" 712d48a237SThomas Meyer depends on HAS_IOMEM 72544e3bf4SGeert Uytterhoeven depends on ARC_SOC_HSDK || COMPILE_TEST 73e0be864fSEugeniy Paltsev help 7413541226SVineet Gupta This enables the reset controller driver for HSDK board. 75e0be864fSEugeniy Paltsev 76abf97755SAndrey Smirnovconfig RESET_IMX7 77a442abbbSAnson Huang tristate "i.MX7/8 Reset Driver" 788fa56620SMasahiro Yamada depends on HAS_IOMEM 79a442abbbSAnson Huang depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 80a442abbbSAnson Huang default y if SOC_IMX7D 81abf97755SAndrey Smirnov select MFD_SYSCON 82abf97755SAndrey Smirnov help 83abf97755SAndrey Smirnov This enables the reset controller driver for i.MX7 SoCs. 84abf97755SAndrey Smirnov 85c9aef213SDilip Kotaconfig RESET_INTEL_GW 86c9aef213SDilip Kota bool "Intel Reset Controller Driver" 876ab9d621SGeert Uytterhoeven depends on X86 || COMPILE_TEST 88b460e0a9SBrendan Higgins depends on OF && HAS_IOMEM 89c9aef213SDilip Kota select REGMAP_MMIO 90c9aef213SDilip Kota help 91c9aef213SDilip Kota This enables the reset controller driver for Intel Gateway SoCs. 92c9aef213SDilip Kota Say Y to control the reset signals provided by reset controller. 93c9aef213SDilip Kota Otherwise, say N. 94c9aef213SDilip Kota 955a2308daSDamien Le Moalconfig RESET_K210 965a2308daSDamien Le Moal bool "Reset controller driver for Canaan Kendryte K210 SoC" 975a2308daSDamien Le Moal depends on (SOC_CANAAN || COMPILE_TEST) && OF 985a2308daSDamien Le Moal select MFD_SYSCON 995a2308daSDamien Le Moal default SOC_CANAAN 1005a2308daSDamien Le Moal help 1015a2308daSDamien Le Moal Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 1025a2308daSDamien Le Moal Say Y if you want to control reset signals provided by this 1035a2308daSDamien Le Moal controller. 1045a2308daSDamien Le Moal 10579797b6fSMartin Blumenstinglconfig RESET_LANTIQ 10679797b6fSMartin Blumenstingl bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 10779797b6fSMartin Blumenstingl default SOC_TYPE_XWAY 10879797b6fSMartin Blumenstingl help 10979797b6fSMartin Blumenstingl This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 11079797b6fSMartin Blumenstingl 111cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX 112cd7f4b81SPhilipp Zabel bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 113cd7f4b81SPhilipp Zabel default ARCH_LPC18XX 114cd7f4b81SPhilipp Zabel help 115cd7f4b81SPhilipp Zabel This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 116cd7f4b81SPhilipp Zabel 117453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5 118453ed428SSteen Hegelund bool "Microchip Sparx5 reset driver" 1198c81620aSHoratiu Vultur depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 120453ed428SSteen Hegelund default y if SPARX5_SWITCH 121453ed428SSteen Hegelund select MFD_SYSCON 122453ed428SSteen Hegelund help 123453ed428SSteen Hegelund This driver supports switch core reset for the Microchip Sparx5 SoC. 124453ed428SSteen Hegelund 12544336c24SPhilipp Zabelconfig RESET_MESON 1263bfe8933SNeil Armstrong tristate "Meson Reset Driver" 1273bfe8933SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 12844336c24SPhilipp Zabel default ARCH_MESON 12944336c24SPhilipp Zabel help 13044336c24SPhilipp Zabel This enables the reset driver for Amlogic Meson SoCs. 13144336c24SPhilipp Zabel 132d903779bSJerome Brunetconfig RESET_MESON_AUDIO_ARB 133d903779bSJerome Brunet tristate "Meson Audio Memory Arbiter Reset Driver" 134d903779bSJerome Brunet depends on ARCH_MESON || COMPILE_TEST 135d903779bSJerome Brunet help 136d903779bSJerome Brunet This enables the reset driver for Audio Memory Arbiter of 137d903779bSJerome Brunet Amlogic's A113 based SoCs 138d903779bSJerome Brunet 1399c81b2ccSTomer Maimonconfig RESET_NPCM 1409c81b2ccSTomer Maimon bool "NPCM BMC Reset Driver" if COMPILE_TEST 1419c81b2ccSTomer Maimon default ARCH_NPCM 1429c81b2ccSTomer Maimon help 1439c81b2ccSTomer Maimon This enables the reset controller driver for Nuvoton NPCM 1449c81b2ccSTomer Maimon BMC SoCs. 1459c81b2ccSTomer Maimon 1466e667facSNeil Armstrongconfig RESET_OXNAS 1476e667facSNeil Armstrong bool 1486e667facSNeil Armstrong 149fab3f730SPhilipp Zabelconfig RESET_PISTACHIO 1504af16070SGeert Uytterhoeven bool "Pistachio Reset Driver" 1514af16070SGeert Uytterhoeven depends on MIPS || COMPILE_TEST 152fab3f730SPhilipp Zabel help 153fab3f730SPhilipp Zabel This enables the reset driver for ImgTec Pistachio SoCs. 154fab3f730SPhilipp Zabel 15505f9e363SConor Dooleyconfig RESET_POLARFIRE_SOC 15605f9e363SConor Dooley bool "Microchip PolarFire SoC (MPFS) Reset Driver" 15705f9e363SConor Dooley depends on AUXILIARY_BUS && MCHP_CLK_MPFS 15805f9e363SConor Dooley default MCHP_CLK_MPFS 15905f9e363SConor Dooley help 16005f9e363SConor Dooley This driver supports peripheral reset for the Microchip PolarFire SoC 16105f9e363SConor Dooley 1625ecb0651SSibi Sankarconfig RESET_QCOM_AOSS 163e2d5e833SJohn Stultz tristate "Qcom AOSS Reset Driver" 1645ecb0651SSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 1655ecb0651SSibi Sankar help 1665ecb0651SSibi Sankar This enables the AOSS (always on subsystem) reset driver 1675ecb0651SSibi Sankar for Qualcomm SDM845 SoCs. Say Y if you want to control 1685ecb0651SSibi Sankar reset signals provided by AOSS for Modem, Venus, ADSP, 1695ecb0651SSibi Sankar GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 1705ecb0651SSibi Sankar 171eea2926bSSibi Sankarconfig RESET_QCOM_PDC 172eea2926bSSibi Sankar tristate "Qualcomm PDC Reset Driver" 173eea2926bSSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 174eea2926bSSibi Sankar help 175eea2926bSSibi Sankar This enables the PDC (Power Domain Controller) reset driver 176eea2926bSSibi Sankar for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 177eea2926bSSibi Sankar to control reset signals provided by PDC for Modem, Compute, 178eea2926bSSibi Sankar Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 179eea2926bSSibi Sankar 180abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI 181abffc82aSNicolas Saenz Julienne tristate "Raspberry Pi 4 Firmware Reset Driver" 182abffc82aSNicolas Saenz Julienne depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 183abffc82aSNicolas Saenz Julienne default USB_XHCI_PCI 184abffc82aSNicolas Saenz Julienne help 185abffc82aSNicolas Saenz Julienne Raspberry Pi 4's co-processor controls some of the board's HW 186abffc82aSNicolas Saenz Julienne initialization process, but it's up to Linux to trigger it when 187abffc82aSNicolas Saenz Julienne relevant. This driver provides a reset controller capable of 188abffc82aSNicolas Saenz Julienne interfacing with RPi4's co-processor and model these firmware 189abffc82aSNicolas Saenz Julienne initialization routines as reset lines. 190abffc82aSNicolas Saenz Julienne 191bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL 192bee08559SBiju Das tristate "Renesas RZ/G2L USBPHY control driver" 1939fe7dd4eSLad Prabhakar depends on ARCH_RZG2L || COMPILE_TEST 194bee08559SBiju Das help 195bee08559SBiju Das Support for USBPHY Control found on RZ/G2L family. It mainly 196bee08559SBiju Das controls reset and power down of the USB/PHY. 197bee08559SBiju Das 198c8ae9c2dSSudeep Hollaconfig RESET_SCMI 199c8ae9c2dSSudeep Holla tristate "Reset driver controlled via ARM SCMI interface" 200c8ae9c2dSSudeep Holla depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 201c8ae9c2dSSudeep Holla default ARM_SCMI_PROTOCOL 202c8ae9c2dSSudeep Holla help 203c8ae9c2dSSudeep Holla This driver provides support for reset signal/domains that are 204c8ae9c2dSSudeep Holla controlled by firmware that implements the SCMI interface. 205c8ae9c2dSSudeep Holla 206c8ae9c2dSSudeep Holla This driver uses SCMI Message Protocol to interact with the 207c8ae9c2dSSudeep Holla firmware controlling all the reset signals. 208c8ae9c2dSSudeep Holla 20981c22ad0SPhilipp Zabelconfig RESET_SIMPLE 21018d1909bSBen Dooks bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 2117bb49d77SWilliam Zhang default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 212c4ada3caSBen Dooks depends on HAS_IOMEM 21381c22ad0SPhilipp Zabel help 21481c22ad0SPhilipp Zabel This enables a simple reset controller driver for reset lines that 21581c22ad0SPhilipp Zabel that can be asserted and deasserted by toggling bits in a contiguous, 21681c22ad0SPhilipp Zabel exclusive register space. 21781c22ad0SPhilipp Zabel 2181d7592f8SJoel Stanley Currently this driver supports: 2191d7592f8SJoel Stanley - Altera SoCFPGAs 2201d7592f8SJoel Stanley - ASPEED BMC SoCs 2215ac33eebSAndreas Färber - Bitmain BM1880 SoC 2223ab831e5SAndreas Färber - Realtek SoCs 2231d7592f8SJoel Stanley - RCC reset controller in STM32 MCUs 2241d7592f8SJoel Stanley - Allwinner SoCs 225e4d368e0SGreentime Hu - SiFive FU740 SoCs 2267e0e901dSPhilipp Zabel 227b3ca9888SDinh Nguyenconfig RESET_SOCFPGA 228225c13f0SKrzysztof Kozlowski bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 229225c13f0SKrzysztof Kozlowski default ARM && ARCH_INTEL_SOCFPGA 230b3ca9888SDinh Nguyen select RESET_SIMPLE 231b3ca9888SDinh Nguyen help 232b3ca9888SDinh Nguyen This enables the reset driver for the SoCFPGA ARMv7 platforms. This 233b3ca9888SDinh Nguyen driver gets initialized early during platform init calls. 234b3ca9888SDinh Nguyen 235dbf018beSQin Jianconfig RESET_SUNPLUS 236dbf018beSQin Jian bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 237dbf018beSQin Jian default ARCH_SUNPLUS 238dbf018beSQin Jian help 239dbf018beSQin Jian This enables the reset driver support for Sunplus SoCs. 240dbf018beSQin Jian The reset lines that can be asserted and deasserted by toggling bits 241dbf018beSQin Jian in a contiguous, exclusive register space. The register is HIWORD_MASKED, 242dbf018beSQin Jian which means each register holds 16 reset lines. 243dbf018beSQin Jian 2440ae08419SPhilipp Zabelconfig RESET_SUNXI 2450ae08419SPhilipp Zabel bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 2460ae08419SPhilipp Zabel default ARCH_SUNXI 247e13c205aSPhilipp Zabel select RESET_SIMPLE 2480ae08419SPhilipp Zabel help 2490ae08419SPhilipp Zabel This enables the reset driver for Allwinner SoCs. 2500ae08419SPhilipp Zabel 25128df169bSAndrew F. Davisconfig RESET_TI_SCI 25228df169bSAndrew F. Davis tristate "TI System Control Interface (TI-SCI) reset driver" 25313678f3fSRandy Dunlap depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 25428df169bSAndrew F. Davis help 25528df169bSAndrew F. Davis This enables the reset driver support over TI System Control Interface 25628df169bSAndrew F. Davis available on some new TI's SoCs. If you wish to use reset resources 25728df169bSAndrew F. Davis managed by the TI System Controller, say Y here. Otherwise, say N. 25828df169bSAndrew F. Davis 259dd9bf863SSuman Annaconfig RESET_TI_SYSCON 260cc7c2bb1SAndrew F. Davis tristate "TI SYSCON Reset Driver" 261cc7c2bb1SAndrew F. Davis depends on HAS_IOMEM 262cc7c2bb1SAndrew F. Davis select MFD_SYSCON 263cc7c2bb1SAndrew F. Davis help 264cc7c2bb1SAndrew F. Davis This enables the reset driver support for TI devices with 265cc7c2bb1SAndrew F. Davis memory-mapped reset registers as part of a syscon device node. If 266cc7c2bb1SAndrew F. Davis you wish to use the reset framework for such memory-mapped devices, 267cc7c2bb1SAndrew F. Davis say Y here. Otherwise, say N. 268cc7c2bb1SAndrew F. Davis 2698a4e6154SMarco Felschconfig RESET_TI_TPS380X 2708a4e6154SMarco Felsch tristate "TI TPS380x Reset Driver" 2718a4e6154SMarco Felsch select GPIOLIB 2728a4e6154SMarco Felsch help 2738a4e6154SMarco Felsch This enables the reset driver support for TI TPS380x devices. If 2748a4e6154SMarco Felsch you wish to use the reset framework for such devices, say Y here. 2758a4e6154SMarco Felsch Otherwise, say N. 2768a4e6154SMarco Felsch 2775cd3921dSRobert Markoconfig RESET_TN48M_CPLD 2785cd3921dSRobert Marko tristate "Delta Networks TN48M switch CPLD reset controller" 2795cd3921dSRobert Marko depends on MFD_TN48M_CPLD || COMPILE_TEST 2805cd3921dSRobert Marko default MFD_TN48M_CPLD 2815cd3921dSRobert Marko help 2825cd3921dSRobert Marko This enables the reset controller driver for the Delta TN48M CPLD. 2835cd3921dSRobert Marko It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 2845cd3921dSRobert Marko switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 2855cd3921dSRobert Marko Microchip PD69200 PoE PSE controller. 2865cd3921dSRobert Marko 2875cd3921dSRobert Marko This driver can also be built as a module. If so, the module will be 2885cd3921dSRobert Marko called reset-tn48m. 2895cd3921dSRobert Marko 29054e991b5SMasahiro Yamadaconfig RESET_UNIPHIER 29154e991b5SMasahiro Yamada tristate "Reset controller driver for UniPhier SoCs" 29254e991b5SMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 29354e991b5SMasahiro Yamada depends on OF && MFD_SYSCON 29454e991b5SMasahiro Yamada default ARCH_UNIPHIER 29554e991b5SMasahiro Yamada help 29654e991b5SMasahiro Yamada Support for reset controllers on UniPhier SoCs. 29754e991b5SMasahiro Yamada Say Y if you want to control reset signals provided by System Control 29854e991b5SMasahiro Yamada block, Media I/O block, Peripheral Block. 29954e991b5SMasahiro Yamada 3003eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE 3013eb8f765SKunihiko Hayashi tristate "Reset driver in glue layer for UniPhier SoCs" 302499fef09SKunihiko Hayashi depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 303499fef09SKunihiko Hayashi default ARCH_UNIPHIER 304499fef09SKunihiko Hayashi select RESET_SIMPLE 305499fef09SKunihiko Hayashi help 3063eb8f765SKunihiko Hayashi Support for peripheral core reset included in its own glue layer 3073eb8f765SKunihiko Hayashi on UniPhier SoCs. Say Y if you want to control reset signals 3083eb8f765SKunihiko Hayashi provided by the glue layer. 309499fef09SKunihiko Hayashi 3106f51b860SPhilipp Zabelconfig RESET_ZYNQ 3116f51b860SPhilipp Zabel bool "ZYNQ Reset Driver" if COMPILE_TEST 3126f51b860SPhilipp Zabel default ARCH_ZYNQ 3136f51b860SPhilipp Zabel help 3146f51b860SPhilipp Zabel This enables the reset controller driver for Xilinx Zynq SoCs. 3156f51b860SPhilipp Zabel 316*69bfec75SEmil Renner Berthingsource "drivers/reset/starfive/Kconfig" 317e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig" 318f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig" 319dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig" 320998cd463SMasahiro Yamada 321998cd463SMasahiro Yamadaendif 322