1 /* 2 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader 3 * 4 * Copyright (C) 2016 Linaro Ltd 5 * Copyright (C) 2014 Sony Mobile Communications AB 6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/firmware.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/qcom_scm.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/remoteproc.h> 31 #include <linux/soc/qcom/smem.h> 32 #include <linux/soc/qcom/smem_state.h> 33 34 #include "qcom_mdt_loader.h" 35 #include "remoteproc_internal.h" 36 #include "qcom_wcnss.h" 37 38 #define WCNSS_CRASH_REASON_SMEM 422 39 #define WCNSS_FIRMWARE_NAME "wcnss.mdt" 40 #define WCNSS_PAS_ID 6 41 42 #define WCNSS_SPARE_NVBIN_DLND BIT(25) 43 44 #define WCNSS_PMU_IRIS_XO_CFG BIT(3) 45 #define WCNSS_PMU_IRIS_XO_EN BIT(4) 46 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5) 47 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */ 48 49 #define WCNSS_PMU_IRIS_RESET BIT(7) 50 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */ 51 #define WCNSS_PMU_IRIS_XO_READ BIT(9) 52 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10) 53 54 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1) 55 #define WCNSS_PMU_XO_MODE_19p2 0 56 #define WCNSS_PMU_XO_MODE_48 3 57 58 struct wcnss_data { 59 size_t pmu_offset; 60 size_t spare_offset; 61 62 const struct wcnss_vreg_info *vregs; 63 size_t num_vregs; 64 }; 65 66 struct qcom_wcnss { 67 struct device *dev; 68 struct rproc *rproc; 69 70 void __iomem *pmu_cfg; 71 void __iomem *spare_out; 72 73 bool use_48mhz_xo; 74 75 int wdog_irq; 76 int fatal_irq; 77 int ready_irq; 78 int handover_irq; 79 int stop_ack_irq; 80 81 struct qcom_smem_state *state; 82 unsigned stop_bit; 83 84 struct mutex iris_lock; 85 struct qcom_iris *iris; 86 87 struct regulator_bulk_data *vregs; 88 size_t num_vregs; 89 90 struct completion start_done; 91 struct completion stop_done; 92 93 phys_addr_t mem_phys; 94 phys_addr_t mem_reloc; 95 void *mem_region; 96 size_t mem_size; 97 }; 98 99 static const struct wcnss_data riva_data = { 100 .pmu_offset = 0x28, 101 .spare_offset = 0xb4, 102 103 .vregs = (struct wcnss_vreg_info[]) { 104 { "vddmx", 1050000, 1150000, 0 }, 105 { "vddcx", 1050000, 1150000, 0 }, 106 { "vddpx", 1800000, 1800000, 0 }, 107 }, 108 .num_vregs = 3, 109 }; 110 111 static const struct wcnss_data pronto_v1_data = { 112 .pmu_offset = 0x1004, 113 .spare_offset = 0x1088, 114 115 .vregs = (struct wcnss_vreg_info[]) { 116 { "vddmx", 950000, 1150000, 0 }, 117 { "vddcx", .super_turbo = true}, 118 { "vddpx", 1800000, 1800000, 0 }, 119 }, 120 .num_vregs = 3, 121 }; 122 123 static const struct wcnss_data pronto_v2_data = { 124 .pmu_offset = 0x1004, 125 .spare_offset = 0x1088, 126 127 .vregs = (struct wcnss_vreg_info[]) { 128 { "vddmx", 1287500, 1287500, 0 }, 129 { "vddcx", .super_turbo = true }, 130 { "vddpx", 1800000, 1800000, 0 }, 131 }, 132 .num_vregs = 3, 133 }; 134 135 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss, 136 struct qcom_iris *iris, 137 bool use_48mhz_xo) 138 { 139 mutex_lock(&wcnss->iris_lock); 140 141 wcnss->iris = iris; 142 wcnss->use_48mhz_xo = use_48mhz_xo; 143 144 mutex_unlock(&wcnss->iris_lock); 145 } 146 EXPORT_SYMBOL_GPL(qcom_wcnss_assign_iris); 147 148 static int wcnss_load(struct rproc *rproc, const struct firmware *fw) 149 { 150 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 151 phys_addr_t fw_addr; 152 size_t fw_size; 153 bool relocate; 154 int ret; 155 156 ret = qcom_scm_pas_init_image(WCNSS_PAS_ID, fw->data, fw->size); 157 if (ret) { 158 dev_err(&rproc->dev, "invalid firmware metadata\n"); 159 return ret; 160 } 161 162 ret = qcom_mdt_parse(fw, &fw_addr, &fw_size, &relocate); 163 if (ret) { 164 dev_err(&rproc->dev, "failed to parse mdt header\n"); 165 return ret; 166 } 167 168 if (relocate) { 169 wcnss->mem_reloc = fw_addr; 170 171 ret = qcom_scm_pas_mem_setup(WCNSS_PAS_ID, wcnss->mem_phys, fw_size); 172 if (ret) { 173 dev_err(&rproc->dev, "unable to setup memory for image\n"); 174 return ret; 175 } 176 } 177 178 return qcom_mdt_load(rproc, fw, rproc->firmware); 179 } 180 181 static const struct rproc_fw_ops wcnss_fw_ops = { 182 .find_rsc_table = qcom_mdt_find_rsc_table, 183 .load = wcnss_load, 184 }; 185 186 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) 187 { 188 u32 val; 189 190 /* Indicate NV download capability */ 191 val = readl(wcnss->spare_out); 192 val |= WCNSS_SPARE_NVBIN_DLND; 193 writel(val, wcnss->spare_out); 194 } 195 196 static void wcnss_configure_iris(struct qcom_wcnss *wcnss) 197 { 198 u32 val; 199 200 /* Clear PMU cfg register */ 201 writel(0, wcnss->pmu_cfg); 202 203 val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN; 204 writel(val, wcnss->pmu_cfg); 205 206 /* Clear XO_MODE */ 207 val &= ~WCNSS_PMU_XO_MODE_MASK; 208 if (wcnss->use_48mhz_xo) 209 val |= WCNSS_PMU_XO_MODE_48 << 1; 210 else 211 val |= WCNSS_PMU_XO_MODE_19p2 << 1; 212 writel(val, wcnss->pmu_cfg); 213 214 /* Reset IRIS */ 215 val |= WCNSS_PMU_IRIS_RESET; 216 writel(val, wcnss->pmu_cfg); 217 218 /* Wait for PMU.iris_reg_reset_sts */ 219 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS) 220 cpu_relax(); 221 222 /* Clear IRIS reset */ 223 val &= ~WCNSS_PMU_IRIS_RESET; 224 writel(val, wcnss->pmu_cfg); 225 226 /* Start IRIS XO configuration */ 227 val |= WCNSS_PMU_IRIS_XO_CFG; 228 writel(val, wcnss->pmu_cfg); 229 230 /* Wait for XO configuration to finish */ 231 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS) 232 cpu_relax(); 233 234 /* Stop IRIS XO configuration */ 235 val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP; 236 val &= ~WCNSS_PMU_IRIS_XO_CFG; 237 writel(val, wcnss->pmu_cfg); 238 239 /* Add some delay for XO to settle */ 240 msleep(20); 241 } 242 243 static int wcnss_start(struct rproc *rproc) 244 { 245 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 246 int ret; 247 248 mutex_lock(&wcnss->iris_lock); 249 if (!wcnss->iris) { 250 dev_err(wcnss->dev, "no iris registered\n"); 251 ret = -EINVAL; 252 goto release_iris_lock; 253 } 254 255 ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs); 256 if (ret) 257 goto release_iris_lock; 258 259 ret = qcom_iris_enable(wcnss->iris); 260 if (ret) 261 goto disable_regulators; 262 263 wcnss_indicate_nv_download(wcnss); 264 wcnss_configure_iris(wcnss); 265 266 ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); 267 if (ret) { 268 dev_err(wcnss->dev, 269 "failed to authenticate image and release reset\n"); 270 goto disable_iris; 271 } 272 273 ret = wait_for_completion_timeout(&wcnss->start_done, 274 msecs_to_jiffies(5000)); 275 if (wcnss->ready_irq > 0 && ret == 0) { 276 /* We have a ready_irq, but it didn't fire in time. */ 277 dev_err(wcnss->dev, "start timed out\n"); 278 qcom_scm_pas_shutdown(WCNSS_PAS_ID); 279 ret = -ETIMEDOUT; 280 goto disable_iris; 281 } 282 283 ret = 0; 284 285 disable_iris: 286 qcom_iris_disable(wcnss->iris); 287 disable_regulators: 288 regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs); 289 release_iris_lock: 290 mutex_unlock(&wcnss->iris_lock); 291 292 return ret; 293 } 294 295 static int wcnss_stop(struct rproc *rproc) 296 { 297 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 298 int ret; 299 300 if (wcnss->state) { 301 qcom_smem_state_update_bits(wcnss->state, 302 BIT(wcnss->stop_bit), 303 BIT(wcnss->stop_bit)); 304 305 ret = wait_for_completion_timeout(&wcnss->stop_done, 306 msecs_to_jiffies(5000)); 307 if (ret == 0) 308 dev_err(wcnss->dev, "timed out on wait\n"); 309 310 qcom_smem_state_update_bits(wcnss->state, 311 BIT(wcnss->stop_bit), 312 0); 313 } 314 315 ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID); 316 if (ret) 317 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret); 318 319 return ret; 320 } 321 322 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len) 323 { 324 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 325 int offset; 326 327 offset = da - wcnss->mem_reloc; 328 if (offset < 0 || offset + len > wcnss->mem_size) 329 return NULL; 330 331 return wcnss->mem_region + offset; 332 } 333 334 static const struct rproc_ops wcnss_ops = { 335 .start = wcnss_start, 336 .stop = wcnss_stop, 337 .da_to_va = wcnss_da_to_va, 338 }; 339 340 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev) 341 { 342 struct qcom_wcnss *wcnss = dev; 343 344 rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG); 345 346 return IRQ_HANDLED; 347 } 348 349 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev) 350 { 351 struct qcom_wcnss *wcnss = dev; 352 size_t len; 353 char *msg; 354 355 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len); 356 if (!IS_ERR(msg) && len > 0 && msg[0]) 357 dev_err(wcnss->dev, "fatal error received: %s\n", msg); 358 359 rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR); 360 361 if (!IS_ERR(msg)) 362 msg[0] = '\0'; 363 364 return IRQ_HANDLED; 365 } 366 367 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev) 368 { 369 struct qcom_wcnss *wcnss = dev; 370 371 complete(&wcnss->start_done); 372 373 return IRQ_HANDLED; 374 } 375 376 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev) 377 { 378 /* 379 * XXX: At this point we're supposed to release the resources that we 380 * have been holding on behalf of the WCNSS. Unfortunately this 381 * interrupt comes way before the other side seems to be done. 382 * 383 * So we're currently relying on the ready interrupt firing later then 384 * this and we just disable the resources at the end of wcnss_start(). 385 */ 386 387 return IRQ_HANDLED; 388 } 389 390 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev) 391 { 392 struct qcom_wcnss *wcnss = dev; 393 394 complete(&wcnss->stop_done); 395 396 return IRQ_HANDLED; 397 } 398 399 static int wcnss_init_regulators(struct qcom_wcnss *wcnss, 400 const struct wcnss_vreg_info *info, 401 int num_vregs) 402 { 403 struct regulator_bulk_data *bulk; 404 int ret; 405 int i; 406 407 bulk = devm_kcalloc(wcnss->dev, 408 num_vregs, sizeof(struct regulator_bulk_data), 409 GFP_KERNEL); 410 if (!bulk) 411 return -ENOMEM; 412 413 for (i = 0; i < num_vregs; i++) 414 bulk[i].supply = info[i].name; 415 416 ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk); 417 if (ret) 418 return ret; 419 420 for (i = 0; i < num_vregs; i++) { 421 if (info[i].max_voltage) 422 regulator_set_voltage(bulk[i].consumer, 423 info[i].min_voltage, 424 info[i].max_voltage); 425 426 if (info[i].load_uA) 427 regulator_set_load(bulk[i].consumer, info[i].load_uA); 428 } 429 430 wcnss->vregs = bulk; 431 wcnss->num_vregs = num_vregs; 432 433 return 0; 434 } 435 436 static int wcnss_request_irq(struct qcom_wcnss *wcnss, 437 struct platform_device *pdev, 438 const char *name, 439 bool optional, 440 irq_handler_t thread_fn) 441 { 442 int ret; 443 444 ret = platform_get_irq_byname(pdev, name); 445 if (ret < 0 && optional) { 446 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name); 447 return 0; 448 } else if (ret < 0) { 449 dev_err(&pdev->dev, "no %s IRQ defined\n", name); 450 return ret; 451 } 452 453 ret = devm_request_threaded_irq(&pdev->dev, ret, 454 NULL, thread_fn, 455 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 456 "wcnss", wcnss); 457 if (ret) 458 dev_err(&pdev->dev, "request %s IRQ failed\n", name); 459 460 return ret; 461 } 462 463 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss) 464 { 465 struct device_node *node; 466 struct resource r; 467 int ret; 468 469 node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0); 470 if (!node) { 471 dev_err(wcnss->dev, "no memory-region specified\n"); 472 return -EINVAL; 473 } 474 475 ret = of_address_to_resource(node, 0, &r); 476 if (ret) 477 return ret; 478 479 wcnss->mem_phys = wcnss->mem_reloc = r.start; 480 wcnss->mem_size = resource_size(&r); 481 wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size); 482 if (!wcnss->mem_region) { 483 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n", 484 &r.start, wcnss->mem_size); 485 return -EBUSY; 486 } 487 488 return 0; 489 } 490 491 static int wcnss_probe(struct platform_device *pdev) 492 { 493 const struct wcnss_data *data; 494 struct qcom_wcnss *wcnss; 495 struct resource *res; 496 struct rproc *rproc; 497 void __iomem *mmio; 498 int ret; 499 500 data = of_device_get_match_data(&pdev->dev); 501 502 if (!qcom_scm_is_available()) 503 return -EPROBE_DEFER; 504 505 if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) { 506 dev_err(&pdev->dev, "PAS is not available for WCNSS\n"); 507 return -ENXIO; 508 } 509 510 rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops, 511 WCNSS_FIRMWARE_NAME, sizeof(*wcnss)); 512 if (!rproc) { 513 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 514 return -ENOMEM; 515 } 516 517 rproc->fw_ops = &wcnss_fw_ops; 518 519 wcnss = (struct qcom_wcnss *)rproc->priv; 520 wcnss->dev = &pdev->dev; 521 wcnss->rproc = rproc; 522 platform_set_drvdata(pdev, wcnss); 523 524 init_completion(&wcnss->start_done); 525 init_completion(&wcnss->stop_done); 526 527 mutex_init(&wcnss->iris_lock); 528 529 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu"); 530 mmio = devm_ioremap_resource(&pdev->dev, res); 531 if (IS_ERR(mmio)) { 532 ret = PTR_ERR(mmio); 533 goto free_rproc; 534 }; 535 536 ret = wcnss_alloc_memory_region(wcnss); 537 if (ret) 538 goto free_rproc; 539 540 wcnss->pmu_cfg = mmio + data->pmu_offset; 541 wcnss->spare_out = mmio + data->spare_offset; 542 543 ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs); 544 if (ret) 545 goto free_rproc; 546 547 ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt); 548 if (ret < 0) 549 goto free_rproc; 550 wcnss->wdog_irq = ret; 551 552 ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt); 553 if (ret < 0) 554 goto free_rproc; 555 wcnss->fatal_irq = ret; 556 557 ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt); 558 if (ret < 0) 559 goto free_rproc; 560 wcnss->ready_irq = ret; 561 562 ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt); 563 if (ret < 0) 564 goto free_rproc; 565 wcnss->handover_irq = ret; 566 567 ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt); 568 if (ret < 0) 569 goto free_rproc; 570 wcnss->stop_ack_irq = ret; 571 572 if (wcnss->stop_ack_irq) { 573 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop", 574 &wcnss->stop_bit); 575 if (IS_ERR(wcnss->state)) { 576 ret = PTR_ERR(wcnss->state); 577 goto free_rproc; 578 } 579 } 580 581 ret = rproc_add(rproc); 582 if (ret) 583 goto free_rproc; 584 585 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 586 587 free_rproc: 588 rproc_free(rproc); 589 590 return ret; 591 } 592 593 static int wcnss_remove(struct platform_device *pdev) 594 { 595 struct qcom_wcnss *wcnss = platform_get_drvdata(pdev); 596 597 of_platform_depopulate(&pdev->dev); 598 599 qcom_smem_state_put(wcnss->state); 600 rproc_del(wcnss->rproc); 601 rproc_free(wcnss->rproc); 602 603 return 0; 604 } 605 606 static const struct of_device_id wcnss_of_match[] = { 607 { .compatible = "qcom,riva-pil", &riva_data }, 608 { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data }, 609 { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data }, 610 { }, 611 }; 612 613 static struct platform_driver wcnss_driver = { 614 .probe = wcnss_probe, 615 .remove = wcnss_remove, 616 .driver = { 617 .name = "qcom-wcnss-pil", 618 .of_match_table = wcnss_of_match, 619 }, 620 }; 621 622 module_platform_driver(wcnss_driver); 623 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem"); 624 MODULE_LICENSE("GPL v2"); 625