1 /* 2 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader 3 * 4 * Copyright (C) 2016 Linaro Ltd 5 * Copyright (C) 2014 Sony Mobile Communications AB 6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/firmware.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/qcom_scm.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/remoteproc.h> 31 #include <linux/soc/qcom/mdt_loader.h> 32 #include <linux/soc/qcom/smem.h> 33 #include <linux/soc/qcom/smem_state.h> 34 #include <linux/rpmsg/qcom_smd.h> 35 36 #include "qcom_common.h" 37 #include "remoteproc_internal.h" 38 #include "qcom_wcnss.h" 39 40 #define WCNSS_CRASH_REASON_SMEM 422 41 #define WCNSS_FIRMWARE_NAME "wcnss.mdt" 42 #define WCNSS_PAS_ID 6 43 44 #define WCNSS_SPARE_NVBIN_DLND BIT(25) 45 46 #define WCNSS_PMU_IRIS_XO_CFG BIT(3) 47 #define WCNSS_PMU_IRIS_XO_EN BIT(4) 48 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5) 49 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */ 50 51 #define WCNSS_PMU_IRIS_RESET BIT(7) 52 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */ 53 #define WCNSS_PMU_IRIS_XO_READ BIT(9) 54 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10) 55 56 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1) 57 #define WCNSS_PMU_XO_MODE_19p2 0 58 #define WCNSS_PMU_XO_MODE_48 3 59 60 struct wcnss_data { 61 size_t pmu_offset; 62 size_t spare_offset; 63 64 const struct wcnss_vreg_info *vregs; 65 size_t num_vregs; 66 }; 67 68 struct qcom_wcnss { 69 struct device *dev; 70 struct rproc *rproc; 71 72 void __iomem *pmu_cfg; 73 void __iomem *spare_out; 74 75 bool use_48mhz_xo; 76 77 int wdog_irq; 78 int fatal_irq; 79 int ready_irq; 80 int handover_irq; 81 int stop_ack_irq; 82 83 struct qcom_smem_state *state; 84 unsigned stop_bit; 85 86 struct mutex iris_lock; 87 struct qcom_iris *iris; 88 89 struct regulator_bulk_data *vregs; 90 size_t num_vregs; 91 92 struct completion start_done; 93 struct completion stop_done; 94 95 phys_addr_t mem_phys; 96 phys_addr_t mem_reloc; 97 void *mem_region; 98 size_t mem_size; 99 100 struct qcom_rproc_subdev smd_subdev; 101 }; 102 103 static const struct wcnss_data riva_data = { 104 .pmu_offset = 0x28, 105 .spare_offset = 0xb4, 106 107 .vregs = (struct wcnss_vreg_info[]) { 108 { "vddmx", 1050000, 1150000, 0 }, 109 { "vddcx", 1050000, 1150000, 0 }, 110 { "vddpx", 1800000, 1800000, 0 }, 111 }, 112 .num_vregs = 3, 113 }; 114 115 static const struct wcnss_data pronto_v1_data = { 116 .pmu_offset = 0x1004, 117 .spare_offset = 0x1088, 118 119 .vregs = (struct wcnss_vreg_info[]) { 120 { "vddmx", 950000, 1150000, 0 }, 121 { "vddcx", .super_turbo = true}, 122 { "vddpx", 1800000, 1800000, 0 }, 123 }, 124 .num_vregs = 3, 125 }; 126 127 static const struct wcnss_data pronto_v2_data = { 128 .pmu_offset = 0x1004, 129 .spare_offset = 0x1088, 130 131 .vregs = (struct wcnss_vreg_info[]) { 132 { "vddmx", 1287500, 1287500, 0 }, 133 { "vddcx", .super_turbo = true }, 134 { "vddpx", 1800000, 1800000, 0 }, 135 }, 136 .num_vregs = 3, 137 }; 138 139 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss, 140 struct qcom_iris *iris, 141 bool use_48mhz_xo) 142 { 143 mutex_lock(&wcnss->iris_lock); 144 145 wcnss->iris = iris; 146 wcnss->use_48mhz_xo = use_48mhz_xo; 147 148 mutex_unlock(&wcnss->iris_lock); 149 } 150 151 static int wcnss_load(struct rproc *rproc, const struct firmware *fw) 152 { 153 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 154 155 return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, 156 wcnss->mem_region, wcnss->mem_phys, wcnss->mem_size); 157 } 158 159 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) 160 { 161 u32 val; 162 163 /* Indicate NV download capability */ 164 val = readl(wcnss->spare_out); 165 val |= WCNSS_SPARE_NVBIN_DLND; 166 writel(val, wcnss->spare_out); 167 } 168 169 static void wcnss_configure_iris(struct qcom_wcnss *wcnss) 170 { 171 u32 val; 172 173 /* Clear PMU cfg register */ 174 writel(0, wcnss->pmu_cfg); 175 176 val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN; 177 writel(val, wcnss->pmu_cfg); 178 179 /* Clear XO_MODE */ 180 val &= ~WCNSS_PMU_XO_MODE_MASK; 181 if (wcnss->use_48mhz_xo) 182 val |= WCNSS_PMU_XO_MODE_48 << 1; 183 else 184 val |= WCNSS_PMU_XO_MODE_19p2 << 1; 185 writel(val, wcnss->pmu_cfg); 186 187 /* Reset IRIS */ 188 val |= WCNSS_PMU_IRIS_RESET; 189 writel(val, wcnss->pmu_cfg); 190 191 /* Wait for PMU.iris_reg_reset_sts */ 192 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS) 193 cpu_relax(); 194 195 /* Clear IRIS reset */ 196 val &= ~WCNSS_PMU_IRIS_RESET; 197 writel(val, wcnss->pmu_cfg); 198 199 /* Start IRIS XO configuration */ 200 val |= WCNSS_PMU_IRIS_XO_CFG; 201 writel(val, wcnss->pmu_cfg); 202 203 /* Wait for XO configuration to finish */ 204 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS) 205 cpu_relax(); 206 207 /* Stop IRIS XO configuration */ 208 val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP; 209 val &= ~WCNSS_PMU_IRIS_XO_CFG; 210 writel(val, wcnss->pmu_cfg); 211 212 /* Add some delay for XO to settle */ 213 msleep(20); 214 } 215 216 static int wcnss_start(struct rproc *rproc) 217 { 218 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 219 int ret; 220 221 mutex_lock(&wcnss->iris_lock); 222 if (!wcnss->iris) { 223 dev_err(wcnss->dev, "no iris registered\n"); 224 ret = -EINVAL; 225 goto release_iris_lock; 226 } 227 228 ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs); 229 if (ret) 230 goto release_iris_lock; 231 232 ret = qcom_iris_enable(wcnss->iris); 233 if (ret) 234 goto disable_regulators; 235 236 wcnss_indicate_nv_download(wcnss); 237 wcnss_configure_iris(wcnss); 238 239 ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); 240 if (ret) { 241 dev_err(wcnss->dev, 242 "failed to authenticate image and release reset\n"); 243 goto disable_iris; 244 } 245 246 ret = wait_for_completion_timeout(&wcnss->start_done, 247 msecs_to_jiffies(5000)); 248 if (wcnss->ready_irq > 0 && ret == 0) { 249 /* We have a ready_irq, but it didn't fire in time. */ 250 dev_err(wcnss->dev, "start timed out\n"); 251 qcom_scm_pas_shutdown(WCNSS_PAS_ID); 252 ret = -ETIMEDOUT; 253 goto disable_iris; 254 } 255 256 ret = 0; 257 258 disable_iris: 259 qcom_iris_disable(wcnss->iris); 260 disable_regulators: 261 regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs); 262 release_iris_lock: 263 mutex_unlock(&wcnss->iris_lock); 264 265 return ret; 266 } 267 268 static int wcnss_stop(struct rproc *rproc) 269 { 270 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 271 int ret; 272 273 if (wcnss->state) { 274 qcom_smem_state_update_bits(wcnss->state, 275 BIT(wcnss->stop_bit), 276 BIT(wcnss->stop_bit)); 277 278 ret = wait_for_completion_timeout(&wcnss->stop_done, 279 msecs_to_jiffies(5000)); 280 if (ret == 0) 281 dev_err(wcnss->dev, "timed out on wait\n"); 282 283 qcom_smem_state_update_bits(wcnss->state, 284 BIT(wcnss->stop_bit), 285 0); 286 } 287 288 ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID); 289 if (ret) 290 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret); 291 292 return ret; 293 } 294 295 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len) 296 { 297 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 298 int offset; 299 300 offset = da - wcnss->mem_reloc; 301 if (offset < 0 || offset + len > wcnss->mem_size) 302 return NULL; 303 304 return wcnss->mem_region + offset; 305 } 306 307 static const struct rproc_ops wcnss_ops = { 308 .start = wcnss_start, 309 .stop = wcnss_stop, 310 .da_to_va = wcnss_da_to_va, 311 .load = wcnss_load, 312 }; 313 314 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev) 315 { 316 struct qcom_wcnss *wcnss = dev; 317 318 rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG); 319 320 return IRQ_HANDLED; 321 } 322 323 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev) 324 { 325 struct qcom_wcnss *wcnss = dev; 326 size_t len; 327 char *msg; 328 329 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len); 330 if (!IS_ERR(msg) && len > 0 && msg[0]) 331 dev_err(wcnss->dev, "fatal error received: %s\n", msg); 332 333 rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR); 334 335 if (!IS_ERR(msg)) 336 msg[0] = '\0'; 337 338 return IRQ_HANDLED; 339 } 340 341 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev) 342 { 343 struct qcom_wcnss *wcnss = dev; 344 345 complete(&wcnss->start_done); 346 347 return IRQ_HANDLED; 348 } 349 350 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev) 351 { 352 /* 353 * XXX: At this point we're supposed to release the resources that we 354 * have been holding on behalf of the WCNSS. Unfortunately this 355 * interrupt comes way before the other side seems to be done. 356 * 357 * So we're currently relying on the ready interrupt firing later then 358 * this and we just disable the resources at the end of wcnss_start(). 359 */ 360 361 return IRQ_HANDLED; 362 } 363 364 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev) 365 { 366 struct qcom_wcnss *wcnss = dev; 367 368 complete(&wcnss->stop_done); 369 370 return IRQ_HANDLED; 371 } 372 373 static int wcnss_init_regulators(struct qcom_wcnss *wcnss, 374 const struct wcnss_vreg_info *info, 375 int num_vregs) 376 { 377 struct regulator_bulk_data *bulk; 378 int ret; 379 int i; 380 381 bulk = devm_kcalloc(wcnss->dev, 382 num_vregs, sizeof(struct regulator_bulk_data), 383 GFP_KERNEL); 384 if (!bulk) 385 return -ENOMEM; 386 387 for (i = 0; i < num_vregs; i++) 388 bulk[i].supply = info[i].name; 389 390 ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk); 391 if (ret) 392 return ret; 393 394 for (i = 0; i < num_vregs; i++) { 395 if (info[i].max_voltage) 396 regulator_set_voltage(bulk[i].consumer, 397 info[i].min_voltage, 398 info[i].max_voltage); 399 400 if (info[i].load_uA) 401 regulator_set_load(bulk[i].consumer, info[i].load_uA); 402 } 403 404 wcnss->vregs = bulk; 405 wcnss->num_vregs = num_vregs; 406 407 return 0; 408 } 409 410 static int wcnss_request_irq(struct qcom_wcnss *wcnss, 411 struct platform_device *pdev, 412 const char *name, 413 bool optional, 414 irq_handler_t thread_fn) 415 { 416 int ret; 417 418 ret = platform_get_irq_byname(pdev, name); 419 if (ret < 0 && optional) { 420 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name); 421 return 0; 422 } else if (ret < 0) { 423 dev_err(&pdev->dev, "no %s IRQ defined\n", name); 424 return ret; 425 } 426 427 ret = devm_request_threaded_irq(&pdev->dev, ret, 428 NULL, thread_fn, 429 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 430 "wcnss", wcnss); 431 if (ret) 432 dev_err(&pdev->dev, "request %s IRQ failed\n", name); 433 434 return ret; 435 } 436 437 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss) 438 { 439 struct device_node *node; 440 struct resource r; 441 int ret; 442 443 node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0); 444 if (!node) { 445 dev_err(wcnss->dev, "no memory-region specified\n"); 446 return -EINVAL; 447 } 448 449 ret = of_address_to_resource(node, 0, &r); 450 if (ret) 451 return ret; 452 453 wcnss->mem_phys = wcnss->mem_reloc = r.start; 454 wcnss->mem_size = resource_size(&r); 455 wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size); 456 if (!wcnss->mem_region) { 457 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n", 458 &r.start, wcnss->mem_size); 459 return -EBUSY; 460 } 461 462 return 0; 463 } 464 465 static int wcnss_probe(struct platform_device *pdev) 466 { 467 const struct wcnss_data *data; 468 struct qcom_wcnss *wcnss; 469 struct resource *res; 470 struct rproc *rproc; 471 void __iomem *mmio; 472 int ret; 473 474 data = of_device_get_match_data(&pdev->dev); 475 476 if (!qcom_scm_is_available()) 477 return -EPROBE_DEFER; 478 479 if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) { 480 dev_err(&pdev->dev, "PAS is not available for WCNSS\n"); 481 return -ENXIO; 482 } 483 484 rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops, 485 WCNSS_FIRMWARE_NAME, sizeof(*wcnss)); 486 if (!rproc) { 487 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 488 return -ENOMEM; 489 } 490 491 wcnss = (struct qcom_wcnss *)rproc->priv; 492 wcnss->dev = &pdev->dev; 493 wcnss->rproc = rproc; 494 platform_set_drvdata(pdev, wcnss); 495 496 init_completion(&wcnss->start_done); 497 init_completion(&wcnss->stop_done); 498 499 mutex_init(&wcnss->iris_lock); 500 501 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu"); 502 mmio = devm_ioremap_resource(&pdev->dev, res); 503 if (IS_ERR(mmio)) { 504 ret = PTR_ERR(mmio); 505 goto free_rproc; 506 }; 507 508 ret = wcnss_alloc_memory_region(wcnss); 509 if (ret) 510 goto free_rproc; 511 512 wcnss->pmu_cfg = mmio + data->pmu_offset; 513 wcnss->spare_out = mmio + data->spare_offset; 514 515 ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs); 516 if (ret) 517 goto free_rproc; 518 519 ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt); 520 if (ret < 0) 521 goto free_rproc; 522 wcnss->wdog_irq = ret; 523 524 ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt); 525 if (ret < 0) 526 goto free_rproc; 527 wcnss->fatal_irq = ret; 528 529 ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt); 530 if (ret < 0) 531 goto free_rproc; 532 wcnss->ready_irq = ret; 533 534 ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt); 535 if (ret < 0) 536 goto free_rproc; 537 wcnss->handover_irq = ret; 538 539 ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt); 540 if (ret < 0) 541 goto free_rproc; 542 wcnss->stop_ack_irq = ret; 543 544 if (wcnss->stop_ack_irq) { 545 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop", 546 &wcnss->stop_bit); 547 if (IS_ERR(wcnss->state)) { 548 ret = PTR_ERR(wcnss->state); 549 goto free_rproc; 550 } 551 } 552 553 qcom_add_smd_subdev(rproc, &wcnss->smd_subdev); 554 555 ret = rproc_add(rproc); 556 if (ret) 557 goto free_rproc; 558 559 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 560 561 free_rproc: 562 rproc_free(rproc); 563 564 return ret; 565 } 566 567 static int wcnss_remove(struct platform_device *pdev) 568 { 569 struct qcom_wcnss *wcnss = platform_get_drvdata(pdev); 570 571 of_platform_depopulate(&pdev->dev); 572 573 qcom_smem_state_put(wcnss->state); 574 rproc_del(wcnss->rproc); 575 576 qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev); 577 rproc_free(wcnss->rproc); 578 579 return 0; 580 } 581 582 static const struct of_device_id wcnss_of_match[] = { 583 { .compatible = "qcom,riva-pil", &riva_data }, 584 { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data }, 585 { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data }, 586 { }, 587 }; 588 MODULE_DEVICE_TABLE(of, wcnss_of_match); 589 590 static struct platform_driver wcnss_driver = { 591 .probe = wcnss_probe, 592 .remove = wcnss_remove, 593 .driver = { 594 .name = "qcom-wcnss-pil", 595 .of_match_table = wcnss_of_match, 596 }, 597 }; 598 599 static int __init wcnss_init(void) 600 { 601 int ret; 602 603 ret = platform_driver_register(&wcnss_driver); 604 if (ret) 605 return ret; 606 607 ret = platform_driver_register(&qcom_iris_driver); 608 if (ret) 609 platform_driver_unregister(&wcnss_driver); 610 611 return ret; 612 } 613 module_init(wcnss_init); 614 615 static void __exit wcnss_exit(void) 616 { 617 platform_driver_unregister(&qcom_iris_driver); 618 platform_driver_unregister(&wcnss_driver); 619 } 620 module_exit(wcnss_exit); 621 622 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem"); 623 MODULE_LICENSE("GPL v2"); 624