1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996 4 * 5 * Copyright (C) 2016 Linaro Ltd 6 * Copyright (C) 2014 Sony Mobile Communications AB 7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/firmware.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_domain.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/qcom_scm.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/remoteproc.h> 23 #include <linux/soc/qcom/mdt_loader.h> 24 #include <linux/soc/qcom/smem.h> 25 #include <linux/soc/qcom/smem_state.h> 26 27 #include "qcom_common.h" 28 #include "qcom_pil_info.h" 29 #include "qcom_q6v5.h" 30 #include "remoteproc_internal.h" 31 32 struct adsp_data { 33 int crash_reason_smem; 34 const char *firmware_name; 35 int pas_id; 36 bool has_aggre2_clk; 37 bool auto_boot; 38 39 char **active_pd_names; 40 char **proxy_pd_names; 41 42 const char *ssr_name; 43 const char *sysmon_name; 44 int ssctl_id; 45 }; 46 47 struct qcom_adsp { 48 struct device *dev; 49 struct rproc *rproc; 50 51 struct qcom_q6v5 q6v5; 52 53 struct clk *xo; 54 struct clk *aggre2_clk; 55 56 struct regulator *cx_supply; 57 struct regulator *px_supply; 58 59 struct device *active_pds[1]; 60 struct device *proxy_pds[3]; 61 62 int active_pd_count; 63 int proxy_pd_count; 64 65 int pas_id; 66 int crash_reason_smem; 67 bool has_aggre2_clk; 68 const char *info_name; 69 70 struct completion start_done; 71 struct completion stop_done; 72 73 phys_addr_t mem_phys; 74 phys_addr_t mem_reloc; 75 void *mem_region; 76 size_t mem_size; 77 78 struct qcom_rproc_glink glink_subdev; 79 struct qcom_rproc_subdev smd_subdev; 80 struct qcom_rproc_ssr ssr_subdev; 81 struct qcom_sysmon *sysmon; 82 }; 83 84 static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds, 85 size_t pd_count) 86 { 87 int ret; 88 int i; 89 90 for (i = 0; i < pd_count; i++) { 91 dev_pm_genpd_set_performance_state(pds[i], INT_MAX); 92 ret = pm_runtime_get_sync(pds[i]); 93 if (ret < 0) 94 goto unroll_pd_votes; 95 } 96 97 return 0; 98 99 unroll_pd_votes: 100 for (i--; i >= 0; i--) { 101 dev_pm_genpd_set_performance_state(pds[i], 0); 102 pm_runtime_put(pds[i]); 103 } 104 105 return ret; 106 }; 107 108 static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds, 109 size_t pd_count) 110 { 111 int i; 112 113 for (i = 0; i < pd_count; i++) { 114 dev_pm_genpd_set_performance_state(pds[i], 0); 115 pm_runtime_put(pds[i]); 116 } 117 } 118 119 static int adsp_load(struct rproc *rproc, const struct firmware *fw) 120 { 121 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 122 int ret; 123 124 ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id, 125 adsp->mem_region, adsp->mem_phys, adsp->mem_size, 126 &adsp->mem_reloc); 127 if (ret) 128 return ret; 129 130 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); 131 132 return 0; 133 } 134 135 static int adsp_start(struct rproc *rproc) 136 { 137 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 138 int ret; 139 140 qcom_q6v5_prepare(&adsp->q6v5); 141 142 ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count); 143 if (ret < 0) 144 goto disable_irqs; 145 146 ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 147 if (ret < 0) 148 goto disable_active_pds; 149 150 ret = clk_prepare_enable(adsp->xo); 151 if (ret) 152 goto disable_proxy_pds; 153 154 ret = clk_prepare_enable(adsp->aggre2_clk); 155 if (ret) 156 goto disable_xo_clk; 157 158 ret = regulator_enable(adsp->cx_supply); 159 if (ret) 160 goto disable_aggre2_clk; 161 162 ret = regulator_enable(adsp->px_supply); 163 if (ret) 164 goto disable_cx_supply; 165 166 ret = qcom_scm_pas_auth_and_reset(adsp->pas_id); 167 if (ret) { 168 dev_err(adsp->dev, 169 "failed to authenticate image and release reset\n"); 170 goto disable_px_supply; 171 } 172 173 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000)); 174 if (ret == -ETIMEDOUT) { 175 dev_err(adsp->dev, "start timed out\n"); 176 qcom_scm_pas_shutdown(adsp->pas_id); 177 goto disable_px_supply; 178 } 179 180 return 0; 181 182 disable_px_supply: 183 regulator_disable(adsp->px_supply); 184 disable_cx_supply: 185 regulator_disable(adsp->cx_supply); 186 disable_aggre2_clk: 187 clk_disable_unprepare(adsp->aggre2_clk); 188 disable_xo_clk: 189 clk_disable_unprepare(adsp->xo); 190 disable_proxy_pds: 191 adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 192 disable_active_pds: 193 adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count); 194 disable_irqs: 195 qcom_q6v5_unprepare(&adsp->q6v5); 196 197 return ret; 198 } 199 200 static void qcom_pas_handover(struct qcom_q6v5 *q6v5) 201 { 202 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5); 203 204 regulator_disable(adsp->px_supply); 205 regulator_disable(adsp->cx_supply); 206 clk_disable_unprepare(adsp->aggre2_clk); 207 clk_disable_unprepare(adsp->xo); 208 adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 209 } 210 211 static int adsp_stop(struct rproc *rproc) 212 { 213 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 214 int handover; 215 int ret; 216 217 ret = qcom_q6v5_request_stop(&adsp->q6v5); 218 if (ret == -ETIMEDOUT) 219 dev_err(adsp->dev, "timed out on wait\n"); 220 221 ret = qcom_scm_pas_shutdown(adsp->pas_id); 222 if (ret) 223 dev_err(adsp->dev, "failed to shutdown: %d\n", ret); 224 225 adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count); 226 handover = qcom_q6v5_unprepare(&adsp->q6v5); 227 if (handover) 228 qcom_pas_handover(&adsp->q6v5); 229 230 return ret; 231 } 232 233 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len) 234 { 235 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 236 int offset; 237 238 offset = da - adsp->mem_reloc; 239 if (offset < 0 || offset + len > adsp->mem_size) 240 return NULL; 241 242 return adsp->mem_region + offset; 243 } 244 245 static unsigned long adsp_panic(struct rproc *rproc) 246 { 247 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 248 249 return qcom_q6v5_panic(&adsp->q6v5); 250 } 251 252 static const struct rproc_ops adsp_ops = { 253 .start = adsp_start, 254 .stop = adsp_stop, 255 .da_to_va = adsp_da_to_va, 256 .parse_fw = qcom_register_dump_segments, 257 .load = adsp_load, 258 .panic = adsp_panic, 259 }; 260 261 static int adsp_init_clock(struct qcom_adsp *adsp) 262 { 263 int ret; 264 265 adsp->xo = devm_clk_get(adsp->dev, "xo"); 266 if (IS_ERR(adsp->xo)) { 267 ret = PTR_ERR(adsp->xo); 268 if (ret != -EPROBE_DEFER) 269 dev_err(adsp->dev, "failed to get xo clock"); 270 return ret; 271 } 272 273 if (adsp->has_aggre2_clk) { 274 adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2"); 275 if (IS_ERR(adsp->aggre2_clk)) { 276 ret = PTR_ERR(adsp->aggre2_clk); 277 if (ret != -EPROBE_DEFER) 278 dev_err(adsp->dev, 279 "failed to get aggre2 clock"); 280 return ret; 281 } 282 } 283 284 return 0; 285 } 286 287 static int adsp_init_regulator(struct qcom_adsp *adsp) 288 { 289 adsp->cx_supply = devm_regulator_get(adsp->dev, "cx"); 290 if (IS_ERR(adsp->cx_supply)) 291 return PTR_ERR(adsp->cx_supply); 292 293 regulator_set_load(adsp->cx_supply, 100000); 294 295 adsp->px_supply = devm_regulator_get(adsp->dev, "px"); 296 return PTR_ERR_OR_ZERO(adsp->px_supply); 297 } 298 299 static int adsp_pds_attach(struct device *dev, struct device **devs, 300 char **pd_names) 301 { 302 size_t num_pds = 0; 303 int ret; 304 int i; 305 306 if (!pd_names) 307 return 0; 308 309 /* Handle single power domain */ 310 if (dev->pm_domain) { 311 devs[0] = dev; 312 pm_runtime_enable(dev); 313 return 1; 314 } 315 316 while (pd_names[num_pds]) 317 num_pds++; 318 319 for (i = 0; i < num_pds; i++) { 320 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); 321 if (IS_ERR_OR_NULL(devs[i])) { 322 ret = PTR_ERR(devs[i]) ? : -ENODATA; 323 goto unroll_attach; 324 } 325 } 326 327 return num_pds; 328 329 unroll_attach: 330 for (i--; i >= 0; i--) 331 dev_pm_domain_detach(devs[i], false); 332 333 return ret; 334 }; 335 336 static void adsp_pds_detach(struct qcom_adsp *adsp, struct device **pds, 337 size_t pd_count) 338 { 339 struct device *dev = adsp->dev; 340 int i; 341 342 /* Handle single power domain */ 343 if (dev->pm_domain && pd_count) { 344 pm_runtime_disable(dev); 345 return; 346 } 347 348 for (i = 0; i < pd_count; i++) 349 dev_pm_domain_detach(pds[i], false); 350 } 351 352 static int adsp_alloc_memory_region(struct qcom_adsp *adsp) 353 { 354 struct device_node *node; 355 struct resource r; 356 int ret; 357 358 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0); 359 if (!node) { 360 dev_err(adsp->dev, "no memory-region specified\n"); 361 return -EINVAL; 362 } 363 364 ret = of_address_to_resource(node, 0, &r); 365 if (ret) 366 return ret; 367 368 adsp->mem_phys = adsp->mem_reloc = r.start; 369 adsp->mem_size = resource_size(&r); 370 adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size); 371 if (!adsp->mem_region) { 372 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n", 373 &r.start, adsp->mem_size); 374 return -EBUSY; 375 } 376 377 return 0; 378 } 379 380 static int adsp_probe(struct platform_device *pdev) 381 { 382 const struct adsp_data *desc; 383 struct qcom_adsp *adsp; 384 struct rproc *rproc; 385 const char *fw_name; 386 int ret; 387 388 desc = of_device_get_match_data(&pdev->dev); 389 if (!desc) 390 return -EINVAL; 391 392 if (!qcom_scm_is_available()) 393 return -EPROBE_DEFER; 394 395 fw_name = desc->firmware_name; 396 ret = of_property_read_string(pdev->dev.of_node, "firmware-name", 397 &fw_name); 398 if (ret < 0 && ret != -EINVAL) 399 return ret; 400 401 rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops, 402 fw_name, sizeof(*adsp)); 403 if (!rproc) { 404 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 405 return -ENOMEM; 406 } 407 408 rproc->auto_boot = desc->auto_boot; 409 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 410 411 adsp = (struct qcom_adsp *)rproc->priv; 412 adsp->dev = &pdev->dev; 413 adsp->rproc = rproc; 414 adsp->pas_id = desc->pas_id; 415 adsp->has_aggre2_clk = desc->has_aggre2_clk; 416 adsp->info_name = desc->sysmon_name; 417 platform_set_drvdata(pdev, adsp); 418 419 device_wakeup_enable(adsp->dev); 420 421 ret = adsp_alloc_memory_region(adsp); 422 if (ret) 423 goto free_rproc; 424 425 ret = adsp_init_clock(adsp); 426 if (ret) 427 goto free_rproc; 428 429 ret = adsp_init_regulator(adsp); 430 if (ret) 431 goto free_rproc; 432 433 ret = adsp_pds_attach(&pdev->dev, adsp->active_pds, 434 desc->active_pd_names); 435 if (ret < 0) 436 goto free_rproc; 437 adsp->active_pd_count = ret; 438 439 ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds, 440 desc->proxy_pd_names); 441 if (ret < 0) 442 goto detach_active_pds; 443 adsp->proxy_pd_count = ret; 444 445 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, 446 qcom_pas_handover); 447 if (ret) 448 goto detach_proxy_pds; 449 450 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name); 451 qcom_add_smd_subdev(rproc, &adsp->smd_subdev); 452 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); 453 adsp->sysmon = qcom_add_sysmon_subdev(rproc, 454 desc->sysmon_name, 455 desc->ssctl_id); 456 if (IS_ERR(adsp->sysmon)) { 457 ret = PTR_ERR(adsp->sysmon); 458 goto detach_proxy_pds; 459 } 460 461 ret = rproc_add(rproc); 462 if (ret) 463 goto detach_proxy_pds; 464 465 return 0; 466 467 detach_proxy_pds: 468 adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 469 detach_active_pds: 470 adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count); 471 free_rproc: 472 rproc_free(rproc); 473 474 return ret; 475 } 476 477 static int adsp_remove(struct platform_device *pdev) 478 { 479 struct qcom_adsp *adsp = platform_get_drvdata(pdev); 480 481 rproc_del(adsp->rproc); 482 483 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); 484 qcom_remove_sysmon_subdev(adsp->sysmon); 485 qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev); 486 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev); 487 rproc_free(adsp->rproc); 488 489 return 0; 490 } 491 492 static const struct adsp_data adsp_resource_init = { 493 .crash_reason_smem = 423, 494 .firmware_name = "adsp.mdt", 495 .pas_id = 1, 496 .has_aggre2_clk = false, 497 .auto_boot = true, 498 .ssr_name = "lpass", 499 .sysmon_name = "adsp", 500 .ssctl_id = 0x14, 501 }; 502 503 static const struct adsp_data sm8150_adsp_resource = { 504 .crash_reason_smem = 423, 505 .firmware_name = "adsp.mdt", 506 .pas_id = 1, 507 .has_aggre2_clk = false, 508 .auto_boot = true, 509 .active_pd_names = (char*[]){ 510 "load_state", 511 NULL 512 }, 513 .proxy_pd_names = (char*[]){ 514 "cx", 515 NULL 516 }, 517 .ssr_name = "lpass", 518 .sysmon_name = "adsp", 519 .ssctl_id = 0x14, 520 }; 521 522 static const struct adsp_data sm8250_adsp_resource = { 523 .crash_reason_smem = 423, 524 .firmware_name = "adsp.mdt", 525 .pas_id = 1, 526 .has_aggre2_clk = false, 527 .auto_boot = true, 528 .active_pd_names = (char*[]){ 529 "load_state", 530 NULL 531 }, 532 .proxy_pd_names = (char*[]){ 533 "lcx", 534 "lmx", 535 NULL 536 }, 537 .ssr_name = "lpass", 538 .sysmon_name = "adsp", 539 .ssctl_id = 0x14, 540 }; 541 542 static const struct adsp_data msm8998_adsp_resource = { 543 .crash_reason_smem = 423, 544 .firmware_name = "adsp.mdt", 545 .pas_id = 1, 546 .has_aggre2_clk = false, 547 .auto_boot = true, 548 .proxy_pd_names = (char*[]){ 549 "cx", 550 NULL 551 }, 552 .ssr_name = "lpass", 553 .sysmon_name = "adsp", 554 .ssctl_id = 0x14, 555 }; 556 557 static const struct adsp_data cdsp_resource_init = { 558 .crash_reason_smem = 601, 559 .firmware_name = "cdsp.mdt", 560 .pas_id = 18, 561 .has_aggre2_clk = false, 562 .auto_boot = true, 563 .ssr_name = "cdsp", 564 .sysmon_name = "cdsp", 565 .ssctl_id = 0x17, 566 }; 567 568 static const struct adsp_data sm8150_cdsp_resource = { 569 .crash_reason_smem = 601, 570 .firmware_name = "cdsp.mdt", 571 .pas_id = 18, 572 .has_aggre2_clk = false, 573 .auto_boot = true, 574 .active_pd_names = (char*[]){ 575 "load_state", 576 NULL 577 }, 578 .proxy_pd_names = (char*[]){ 579 "cx", 580 NULL 581 }, 582 .ssr_name = "cdsp", 583 .sysmon_name = "cdsp", 584 .ssctl_id = 0x17, 585 }; 586 587 static const struct adsp_data sm8250_cdsp_resource = { 588 .crash_reason_smem = 601, 589 .firmware_name = "cdsp.mdt", 590 .pas_id = 18, 591 .has_aggre2_clk = false, 592 .auto_boot = true, 593 .active_pd_names = (char*[]){ 594 "load_state", 595 NULL 596 }, 597 .proxy_pd_names = (char*[]){ 598 "cx", 599 NULL 600 }, 601 .ssr_name = "cdsp", 602 .sysmon_name = "cdsp", 603 .ssctl_id = 0x17, 604 }; 605 606 static const struct adsp_data mpss_resource_init = { 607 .crash_reason_smem = 421, 608 .firmware_name = "modem.mdt", 609 .pas_id = 4, 610 .has_aggre2_clk = false, 611 .auto_boot = false, 612 .active_pd_names = (char*[]){ 613 "load_state", 614 NULL 615 }, 616 .proxy_pd_names = (char*[]){ 617 "cx", 618 "mss", 619 NULL 620 }, 621 .ssr_name = "mpss", 622 .sysmon_name = "modem", 623 .ssctl_id = 0x12, 624 }; 625 626 static const struct adsp_data slpi_resource_init = { 627 .crash_reason_smem = 424, 628 .firmware_name = "slpi.mdt", 629 .pas_id = 12, 630 .has_aggre2_clk = true, 631 .auto_boot = true, 632 .ssr_name = "dsps", 633 .sysmon_name = "slpi", 634 .ssctl_id = 0x16, 635 }; 636 637 static const struct adsp_data sm8150_slpi_resource = { 638 .crash_reason_smem = 424, 639 .firmware_name = "slpi.mdt", 640 .pas_id = 12, 641 .has_aggre2_clk = false, 642 .auto_boot = true, 643 .active_pd_names = (char*[]){ 644 "load_state", 645 NULL 646 }, 647 .proxy_pd_names = (char*[]){ 648 "lcx", 649 "lmx", 650 NULL 651 }, 652 .ssr_name = "dsps", 653 .sysmon_name = "slpi", 654 .ssctl_id = 0x16, 655 }; 656 657 static const struct adsp_data sm8250_slpi_resource = { 658 .crash_reason_smem = 424, 659 .firmware_name = "slpi.mdt", 660 .pas_id = 12, 661 .has_aggre2_clk = false, 662 .auto_boot = true, 663 .active_pd_names = (char*[]){ 664 "load_state", 665 NULL 666 }, 667 .proxy_pd_names = (char*[]){ 668 "lcx", 669 "lmx", 670 NULL 671 }, 672 .ssr_name = "dsps", 673 .sysmon_name = "slpi", 674 .ssctl_id = 0x16, 675 }; 676 677 static const struct adsp_data msm8998_slpi_resource = { 678 .crash_reason_smem = 424, 679 .firmware_name = "slpi.mdt", 680 .pas_id = 12, 681 .has_aggre2_clk = true, 682 .auto_boot = true, 683 .proxy_pd_names = (char*[]){ 684 "ssc_cx", 685 NULL 686 }, 687 .ssr_name = "dsps", 688 .sysmon_name = "slpi", 689 .ssctl_id = 0x16, 690 }; 691 692 static const struct adsp_data wcss_resource_init = { 693 .crash_reason_smem = 421, 694 .firmware_name = "wcnss.mdt", 695 .pas_id = 6, 696 .auto_boot = true, 697 .ssr_name = "mpss", 698 .sysmon_name = "wcnss", 699 .ssctl_id = 0x12, 700 }; 701 702 static const struct of_device_id adsp_of_match[] = { 703 { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init}, 704 { .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init}, 705 { .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init}, 706 { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource}, 707 { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource}, 708 { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init }, 709 { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init }, 710 { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init }, 711 { .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init}, 712 { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init}, 713 { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init}, 714 { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource}, 715 { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource}, 716 { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init}, 717 { .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource}, 718 { .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource}, 719 { .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource}, 720 { .compatible = "qcom,sm8250-slpi-pas", .data = &sm8250_slpi_resource}, 721 { }, 722 }; 723 MODULE_DEVICE_TABLE(of, adsp_of_match); 724 725 static struct platform_driver adsp_driver = { 726 .probe = adsp_probe, 727 .remove = adsp_remove, 728 .driver = { 729 .name = "qcom_q6v5_pas", 730 .of_match_table = adsp_of_match, 731 }, 732 }; 733 734 module_platform_driver(adsp_driver); 735 MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver"); 736 MODULE_LICENSE("GPL v2"); 737