1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
4  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/firmware.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_domain.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/remoteproc.h>
23 #include <linux/reset.h>
24 #include <linux/soc/qcom/mdt_loader.h>
25 #include <linux/soc/qcom/smem.h>
26 #include <linux/soc/qcom/smem_state.h>
27 
28 #include "qcom_common.h"
29 #include "qcom_pil_info.h"
30 #include "qcom_q6v5.h"
31 #include "remoteproc_internal.h"
32 
33 /* time out value */
34 #define ACK_TIMEOUT			1000
35 #define BOOT_FSM_TIMEOUT		10000
36 /* mask values */
37 #define EVB_MASK			GENMASK(27, 4)
38 /*QDSP6SS register offsets*/
39 #define RST_EVB_REG			0x10
40 #define CORE_START_REG			0x400
41 #define BOOT_CMD_REG			0x404
42 #define BOOT_STATUS_REG			0x408
43 #define RET_CFG_REG			0x1C
44 /*TCSR register offsets*/
45 #define LPASS_MASTER_IDLE_REG		0x8
46 #define LPASS_HALTACK_REG		0x4
47 #define LPASS_PWR_ON_REG		0x10
48 #define LPASS_HALTREQ_REG		0x0
49 
50 #define QDSP6SS_XO_CBCR		0x38
51 #define QDSP6SS_CORE_CBCR	0x20
52 #define QDSP6SS_SLEEP_CBCR	0x3c
53 
54 struct adsp_pil_data {
55 	int crash_reason_smem;
56 	const char *firmware_name;
57 
58 	const char *ssr_name;
59 	const char *sysmon_name;
60 	int ssctl_id;
61 
62 	const char **clk_ids;
63 	int num_clks;
64 };
65 
66 struct qcom_adsp {
67 	struct device *dev;
68 	struct rproc *rproc;
69 
70 	struct qcom_q6v5 q6v5;
71 
72 	struct clk *xo;
73 
74 	int num_clks;
75 	struct clk_bulk_data *clks;
76 
77 	void __iomem *qdsp6ss_base;
78 
79 	struct reset_control *pdc_sync_reset;
80 	struct reset_control *restart;
81 
82 	struct regmap *halt_map;
83 	unsigned int halt_lpass;
84 
85 	int crash_reason_smem;
86 	const char *info_name;
87 
88 	struct completion start_done;
89 	struct completion stop_done;
90 
91 	phys_addr_t mem_phys;
92 	phys_addr_t mem_reloc;
93 	void *mem_region;
94 	size_t mem_size;
95 
96 	struct qcom_rproc_glink glink_subdev;
97 	struct qcom_rproc_ssr ssr_subdev;
98 	struct qcom_sysmon *sysmon;
99 };
100 
101 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
102 {
103 	unsigned long timeout;
104 	unsigned int val;
105 	int ret;
106 
107 	/* Reset the retention logic */
108 	val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
109 	val |= 0x1;
110 	writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
111 
112 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
113 
114 	/* QDSP6 master port needs to be explicitly halted */
115 	ret = regmap_read(adsp->halt_map,
116 			adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
117 	if (ret || !val)
118 		goto reset;
119 
120 	ret = regmap_read(adsp->halt_map,
121 			adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
122 			&val);
123 	if (ret || val)
124 		goto reset;
125 
126 	regmap_write(adsp->halt_map,
127 			adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
128 
129 	/* Wait for halt ACK from QDSP6 */
130 	timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
131 	for (;;) {
132 		ret = regmap_read(adsp->halt_map,
133 			adsp->halt_lpass + LPASS_HALTACK_REG, &val);
134 		if (ret || val || time_after(jiffies, timeout))
135 			break;
136 
137 		usleep_range(1000, 1100);
138 	}
139 
140 	ret = regmap_read(adsp->halt_map,
141 			adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
142 	if (ret || !val)
143 		dev_err(adsp->dev, "port failed halt\n");
144 
145 reset:
146 	/* Assert the LPASS PDC Reset */
147 	reset_control_assert(adsp->pdc_sync_reset);
148 	/* Place the LPASS processor into reset */
149 	reset_control_assert(adsp->restart);
150 	/* wait after asserting subsystem restart from AOSS */
151 	usleep_range(200, 300);
152 
153 	/* Clear the halt request for the AXIM and AHBM for Q6 */
154 	regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
155 
156 	/* De-assert the LPASS PDC Reset */
157 	reset_control_deassert(adsp->pdc_sync_reset);
158 	/* Remove the LPASS reset */
159 	reset_control_deassert(adsp->restart);
160 	/* wait after de-asserting subsystem restart from AOSS */
161 	usleep_range(200, 300);
162 
163 	return 0;
164 }
165 
166 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
167 {
168 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
169 	int ret;
170 
171 	ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
172 				    adsp->mem_region, adsp->mem_phys,
173 				    adsp->mem_size, &adsp->mem_reloc);
174 	if (ret)
175 		return ret;
176 
177 	qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
178 
179 	return 0;
180 }
181 
182 static int adsp_start(struct rproc *rproc)
183 {
184 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
185 	int ret;
186 	unsigned int val;
187 
188 	qcom_q6v5_prepare(&adsp->q6v5);
189 
190 	ret = clk_prepare_enable(adsp->xo);
191 	if (ret)
192 		goto disable_irqs;
193 
194 	dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
195 	ret = pm_runtime_get_sync(adsp->dev);
196 	if (ret) {
197 		pm_runtime_put_noidle(adsp->dev);
198 		goto disable_xo_clk;
199 	}
200 
201 	ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
202 	if (ret) {
203 		dev_err(adsp->dev, "adsp clk_enable failed\n");
204 		goto disable_power_domain;
205 	}
206 
207 	/* Enable the XO clock */
208 	writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
209 
210 	/* Enable the QDSP6SS sleep clock */
211 	writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
212 
213 	/* Enable the QDSP6 core clock */
214 	writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
215 
216 	/* Program boot address */
217 	writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
218 
219 	/* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
220 	writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
221 
222 	/* Trigger boot FSM to start QDSP6 */
223 	writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
224 
225 	/* Wait for core to come out of reset */
226 	ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
227 			val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
228 	if (ret) {
229 		dev_err(adsp->dev, "failed to bootup adsp\n");
230 		goto disable_adsp_clks;
231 	}
232 
233 	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
234 	if (ret == -ETIMEDOUT) {
235 		dev_err(adsp->dev, "start timed out\n");
236 		goto disable_adsp_clks;
237 	}
238 
239 	return 0;
240 
241 disable_adsp_clks:
242 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
243 disable_power_domain:
244 	dev_pm_genpd_set_performance_state(adsp->dev, 0);
245 	pm_runtime_put(adsp->dev);
246 disable_xo_clk:
247 	clk_disable_unprepare(adsp->xo);
248 disable_irqs:
249 	qcom_q6v5_unprepare(&adsp->q6v5);
250 
251 	return ret;
252 }
253 
254 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
255 {
256 	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
257 
258 	clk_disable_unprepare(adsp->xo);
259 	dev_pm_genpd_set_performance_state(adsp->dev, 0);
260 	pm_runtime_put(adsp->dev);
261 }
262 
263 static int adsp_stop(struct rproc *rproc)
264 {
265 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
266 	int handover;
267 	int ret;
268 
269 	ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
270 	if (ret == -ETIMEDOUT)
271 		dev_err(adsp->dev, "timed out on wait\n");
272 
273 	ret = qcom_adsp_shutdown(adsp);
274 	if (ret)
275 		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
276 
277 	handover = qcom_q6v5_unprepare(&adsp->q6v5);
278 	if (handover)
279 		qcom_adsp_pil_handover(&adsp->q6v5);
280 
281 	return ret;
282 }
283 
284 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
285 {
286 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
287 	int offset;
288 
289 	offset = da - adsp->mem_reloc;
290 	if (offset < 0 || offset + len > adsp->mem_size)
291 		return NULL;
292 
293 	return adsp->mem_region + offset;
294 }
295 
296 static unsigned long adsp_panic(struct rproc *rproc)
297 {
298 	struct qcom_adsp *adsp = rproc->priv;
299 
300 	return qcom_q6v5_panic(&adsp->q6v5);
301 }
302 
303 static const struct rproc_ops adsp_ops = {
304 	.start = adsp_start,
305 	.stop = adsp_stop,
306 	.da_to_va = adsp_da_to_va,
307 	.parse_fw = qcom_register_dump_segments,
308 	.load = adsp_load,
309 	.panic = adsp_panic,
310 };
311 
312 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
313 {
314 	int num_clks = 0;
315 	int i, ret;
316 
317 	adsp->xo = devm_clk_get(adsp->dev, "xo");
318 	if (IS_ERR(adsp->xo)) {
319 		ret = PTR_ERR(adsp->xo);
320 		if (ret != -EPROBE_DEFER)
321 			dev_err(adsp->dev, "failed to get xo clock");
322 		return ret;
323 	}
324 
325 	for (i = 0; clk_ids[i]; i++)
326 		num_clks++;
327 
328 	adsp->num_clks = num_clks;
329 	adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
330 				sizeof(*adsp->clks), GFP_KERNEL);
331 	if (!adsp->clks)
332 		return -ENOMEM;
333 
334 	for (i = 0; i < adsp->num_clks; i++)
335 		adsp->clks[i].id = clk_ids[i];
336 
337 	return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
338 }
339 
340 static int adsp_init_reset(struct qcom_adsp *adsp)
341 {
342 	adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
343 			"pdc_sync");
344 	if (IS_ERR(adsp->pdc_sync_reset)) {
345 		dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
346 		return PTR_ERR(adsp->pdc_sync_reset);
347 	}
348 
349 	adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
350 
351 	/* Fall back to the  old "cc_lpass" if "restart" is absent */
352 	if (!adsp->restart)
353 		adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
354 
355 	if (IS_ERR(adsp->restart)) {
356 		dev_err(adsp->dev, "failed to acquire restart\n");
357 		return PTR_ERR(adsp->restart);
358 	}
359 
360 	return 0;
361 }
362 
363 static int adsp_init_mmio(struct qcom_adsp *adsp,
364 				struct platform_device *pdev)
365 {
366 	struct device_node *syscon;
367 	int ret;
368 
369 	adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);
370 	if (IS_ERR(adsp->qdsp6ss_base)) {
371 		dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
372 		return PTR_ERR(adsp->qdsp6ss_base);
373 	}
374 
375 	syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
376 	if (!syscon) {
377 		dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
378 		return -EINVAL;
379 	}
380 
381 	adsp->halt_map = syscon_node_to_regmap(syscon);
382 	of_node_put(syscon);
383 	if (IS_ERR(adsp->halt_map))
384 		return PTR_ERR(adsp->halt_map);
385 
386 	ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
387 			1, &adsp->halt_lpass);
388 	if (ret < 0) {
389 		dev_err(&pdev->dev, "no offset in syscon\n");
390 		return ret;
391 	}
392 
393 	return 0;
394 }
395 
396 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
397 {
398 	struct device_node *node;
399 	struct resource r;
400 	int ret;
401 
402 	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
403 	if (!node) {
404 		dev_err(adsp->dev, "no memory-region specified\n");
405 		return -EINVAL;
406 	}
407 
408 	ret = of_address_to_resource(node, 0, &r);
409 	if (ret)
410 		return ret;
411 
412 	adsp->mem_phys = adsp->mem_reloc = r.start;
413 	adsp->mem_size = resource_size(&r);
414 	adsp->mem_region = devm_ioremap_wc(adsp->dev,
415 				adsp->mem_phys, adsp->mem_size);
416 	if (!adsp->mem_region) {
417 		dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
418 			&r.start, adsp->mem_size);
419 		return -EBUSY;
420 	}
421 
422 	return 0;
423 }
424 
425 static int adsp_probe(struct platform_device *pdev)
426 {
427 	const struct adsp_pil_data *desc;
428 	struct qcom_adsp *adsp;
429 	struct rproc *rproc;
430 	int ret;
431 
432 	desc = of_device_get_match_data(&pdev->dev);
433 	if (!desc)
434 		return -EINVAL;
435 
436 	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
437 			    desc->firmware_name, sizeof(*adsp));
438 	if (!rproc) {
439 		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
440 		return -ENOMEM;
441 	}
442 	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
443 
444 	adsp = (struct qcom_adsp *)rproc->priv;
445 	adsp->dev = &pdev->dev;
446 	adsp->rproc = rproc;
447 	adsp->info_name = desc->sysmon_name;
448 	platform_set_drvdata(pdev, adsp);
449 
450 	ret = adsp_alloc_memory_region(adsp);
451 	if (ret)
452 		goto free_rproc;
453 
454 	ret = adsp_init_clock(adsp, desc->clk_ids);
455 	if (ret)
456 		goto free_rproc;
457 
458 	pm_runtime_enable(adsp->dev);
459 
460 	ret = adsp_init_reset(adsp);
461 	if (ret)
462 		goto disable_pm;
463 
464 	ret = adsp_init_mmio(adsp, pdev);
465 	if (ret)
466 		goto disable_pm;
467 
468 	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
469 			     qcom_adsp_pil_handover);
470 	if (ret)
471 		goto disable_pm;
472 
473 	qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
474 	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
475 	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
476 					      desc->sysmon_name,
477 					      desc->ssctl_id);
478 	if (IS_ERR(adsp->sysmon)) {
479 		ret = PTR_ERR(adsp->sysmon);
480 		goto disable_pm;
481 	}
482 
483 	ret = rproc_add(rproc);
484 	if (ret)
485 		goto disable_pm;
486 
487 	return 0;
488 
489 disable_pm:
490 	pm_runtime_disable(adsp->dev);
491 free_rproc:
492 	rproc_free(rproc);
493 
494 	return ret;
495 }
496 
497 static int adsp_remove(struct platform_device *pdev)
498 {
499 	struct qcom_adsp *adsp = platform_get_drvdata(pdev);
500 
501 	rproc_del(adsp->rproc);
502 
503 	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
504 	qcom_remove_sysmon_subdev(adsp->sysmon);
505 	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
506 	pm_runtime_disable(adsp->dev);
507 	rproc_free(adsp->rproc);
508 
509 	return 0;
510 }
511 
512 static const struct adsp_pil_data adsp_resource_init = {
513 	.crash_reason_smem = 423,
514 	.firmware_name = "adsp.mdt",
515 	.ssr_name = "lpass",
516 	.sysmon_name = "adsp",
517 	.ssctl_id = 0x14,
518 	.clk_ids = (const char*[]) {
519 		"sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
520 		"qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
521 	},
522 	.num_clks = 7,
523 };
524 
525 static const struct adsp_pil_data cdsp_resource_init = {
526 	.crash_reason_smem = 601,
527 	.firmware_name = "cdsp.mdt",
528 	.ssr_name = "cdsp",
529 	.sysmon_name = "cdsp",
530 	.ssctl_id = 0x17,
531 	.clk_ids = (const char*[]) {
532 		"sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
533 		"q6_axim", NULL
534 	},
535 	.num_clks = 7,
536 };
537 
538 static const struct of_device_id adsp_of_match[] = {
539 	{ .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
540 	{ .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
541 	{ },
542 };
543 MODULE_DEVICE_TABLE(of, adsp_of_match);
544 
545 static struct platform_driver adsp_pil_driver = {
546 	.probe = adsp_probe,
547 	.remove = adsp_remove,
548 	.driver = {
549 		.name = "qcom_q6v5_adsp",
550 		.of_match_table = adsp_of_match,
551 	},
552 };
553 
554 module_platform_driver(adsp_pil_driver);
555 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
556 MODULE_LICENSE("GPL v2");
557