1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_domain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/remoteproc.h> 23 #include <linux/reset.h> 24 #include <linux/soc/qcom/mdt_loader.h> 25 #include <linux/soc/qcom/smem.h> 26 #include <linux/soc/qcom/smem_state.h> 27 28 #include "qcom_common.h" 29 #include "qcom_pil_info.h" 30 #include "qcom_q6v5.h" 31 #include "remoteproc_internal.h" 32 33 /* time out value */ 34 #define ACK_TIMEOUT 1000 35 #define ACK_TIMEOUT_US 1000000 36 #define BOOT_FSM_TIMEOUT 10000 37 /* mask values */ 38 #define EVB_MASK GENMASK(27, 4) 39 /*QDSP6SS register offsets*/ 40 #define RST_EVB_REG 0x10 41 #define CORE_START_REG 0x400 42 #define BOOT_CMD_REG 0x404 43 #define BOOT_STATUS_REG 0x408 44 #define RET_CFG_REG 0x1C 45 /*TCSR register offsets*/ 46 #define LPASS_MASTER_IDLE_REG 0x8 47 #define LPASS_HALTACK_REG 0x4 48 #define LPASS_PWR_ON_REG 0x10 49 #define LPASS_HALTREQ_REG 0x0 50 51 #define QDSP6SS_XO_CBCR 0x38 52 #define QDSP6SS_CORE_CBCR 0x20 53 #define QDSP6SS_SLEEP_CBCR 0x3c 54 55 #define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3 56 57 struct adsp_pil_data { 58 int crash_reason_smem; 59 const char *firmware_name; 60 61 const char *ssr_name; 62 const char *sysmon_name; 63 int ssctl_id; 64 bool is_wpss; 65 bool auto_boot; 66 67 const char **clk_ids; 68 int num_clks; 69 const char **proxy_pd_names; 70 const char *load_state; 71 }; 72 73 struct qcom_adsp { 74 struct device *dev; 75 struct rproc *rproc; 76 77 struct qcom_q6v5 q6v5; 78 79 struct clk *xo; 80 81 int num_clks; 82 struct clk_bulk_data *clks; 83 84 void __iomem *qdsp6ss_base; 85 86 struct reset_control *pdc_sync_reset; 87 struct reset_control *restart; 88 89 struct regmap *halt_map; 90 unsigned int halt_lpass; 91 92 int crash_reason_smem; 93 const char *info_name; 94 95 struct completion start_done; 96 struct completion stop_done; 97 98 phys_addr_t mem_phys; 99 phys_addr_t mem_reloc; 100 void *mem_region; 101 size_t mem_size; 102 103 struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX]; 104 size_t proxy_pd_count; 105 106 struct qcom_rproc_glink glink_subdev; 107 struct qcom_rproc_ssr ssr_subdev; 108 struct qcom_sysmon *sysmon; 109 110 int (*shutdown)(struct qcom_adsp *adsp); 111 }; 112 113 static int qcom_rproc_pds_attach(struct device *dev, struct qcom_adsp *adsp, 114 const char **pd_names) 115 { 116 struct device **devs = adsp->proxy_pds; 117 size_t num_pds = 0; 118 int ret; 119 int i; 120 121 if (!pd_names) 122 return 0; 123 124 /* Handle single power domain */ 125 if (dev->pm_domain) { 126 devs[0] = dev; 127 pm_runtime_enable(dev); 128 return 1; 129 } 130 131 while (pd_names[num_pds]) 132 num_pds++; 133 134 if (num_pds > ARRAY_SIZE(adsp->proxy_pds)) 135 return -E2BIG; 136 137 for (i = 0; i < num_pds; i++) { 138 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); 139 if (IS_ERR_OR_NULL(devs[i])) { 140 ret = PTR_ERR(devs[i]) ? : -ENODATA; 141 goto unroll_attach; 142 } 143 } 144 145 return num_pds; 146 147 unroll_attach: 148 for (i--; i >= 0; i--) 149 dev_pm_domain_detach(devs[i], false); 150 151 return ret; 152 } 153 154 static void qcom_rproc_pds_detach(struct qcom_adsp *adsp, struct device **pds, 155 size_t pd_count) 156 { 157 struct device *dev = adsp->dev; 158 int i; 159 160 /* Handle single power domain */ 161 if (dev->pm_domain && pd_count) { 162 pm_runtime_disable(dev); 163 return; 164 } 165 166 for (i = 0; i < pd_count; i++) 167 dev_pm_domain_detach(pds[i], false); 168 } 169 170 static int qcom_rproc_pds_enable(struct qcom_adsp *adsp, struct device **pds, 171 size_t pd_count) 172 { 173 int ret; 174 int i; 175 176 for (i = 0; i < pd_count; i++) { 177 dev_pm_genpd_set_performance_state(pds[i], INT_MAX); 178 ret = pm_runtime_resume_and_get(pds[i]); 179 if (ret < 0) { 180 dev_pm_genpd_set_performance_state(pds[i], 0); 181 goto unroll_pd_votes; 182 } 183 } 184 185 return 0; 186 187 unroll_pd_votes: 188 for (i--; i >= 0; i--) { 189 dev_pm_genpd_set_performance_state(pds[i], 0); 190 pm_runtime_put(pds[i]); 191 } 192 193 return ret; 194 } 195 196 static void qcom_rproc_pds_disable(struct qcom_adsp *adsp, struct device **pds, 197 size_t pd_count) 198 { 199 int i; 200 201 for (i = 0; i < pd_count; i++) { 202 dev_pm_genpd_set_performance_state(pds[i], 0); 203 pm_runtime_put(pds[i]); 204 } 205 } 206 207 static int qcom_wpss_shutdown(struct qcom_adsp *adsp) 208 { 209 unsigned int val; 210 211 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1); 212 213 /* Wait for halt ACK from QDSP6 */ 214 regmap_read_poll_timeout(adsp->halt_map, 215 adsp->halt_lpass + LPASS_HALTACK_REG, val, 216 val, 1000, ACK_TIMEOUT_US); 217 218 /* Assert the WPSS PDC Reset */ 219 reset_control_assert(adsp->pdc_sync_reset); 220 221 /* Place the WPSS processor into reset */ 222 reset_control_assert(adsp->restart); 223 224 /* wait after asserting subsystem restart from AOSS */ 225 usleep_range(200, 205); 226 227 /* Remove the WPSS reset */ 228 reset_control_deassert(adsp->restart); 229 230 /* De-assert the WPSS PDC Reset */ 231 reset_control_deassert(adsp->pdc_sync_reset); 232 233 usleep_range(100, 105); 234 235 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 236 237 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0); 238 239 /* Wait for halt ACK from QDSP6 */ 240 regmap_read_poll_timeout(adsp->halt_map, 241 adsp->halt_lpass + LPASS_HALTACK_REG, val, 242 !val, 1000, ACK_TIMEOUT_US); 243 244 return 0; 245 } 246 247 static int qcom_adsp_shutdown(struct qcom_adsp *adsp) 248 { 249 unsigned long timeout; 250 unsigned int val; 251 int ret; 252 253 /* Reset the retention logic */ 254 val = readl(adsp->qdsp6ss_base + RET_CFG_REG); 255 val |= 0x1; 256 writel(val, adsp->qdsp6ss_base + RET_CFG_REG); 257 258 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 259 260 /* QDSP6 master port needs to be explicitly halted */ 261 ret = regmap_read(adsp->halt_map, 262 adsp->halt_lpass + LPASS_PWR_ON_REG, &val); 263 if (ret || !val) 264 goto reset; 265 266 ret = regmap_read(adsp->halt_map, 267 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, 268 &val); 269 if (ret || val) 270 goto reset; 271 272 regmap_write(adsp->halt_map, 273 adsp->halt_lpass + LPASS_HALTREQ_REG, 1); 274 275 /* Wait for halt ACK from QDSP6 */ 276 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT); 277 for (;;) { 278 ret = regmap_read(adsp->halt_map, 279 adsp->halt_lpass + LPASS_HALTACK_REG, &val); 280 if (ret || val || time_after(jiffies, timeout)) 281 break; 282 283 usleep_range(1000, 1100); 284 } 285 286 ret = regmap_read(adsp->halt_map, 287 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val); 288 if (ret || !val) 289 dev_err(adsp->dev, "port failed halt\n"); 290 291 reset: 292 /* Assert the LPASS PDC Reset */ 293 reset_control_assert(adsp->pdc_sync_reset); 294 /* Place the LPASS processor into reset */ 295 reset_control_assert(adsp->restart); 296 /* wait after asserting subsystem restart from AOSS */ 297 usleep_range(200, 300); 298 299 /* Clear the halt request for the AXIM and AHBM for Q6 */ 300 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0); 301 302 /* De-assert the LPASS PDC Reset */ 303 reset_control_deassert(adsp->pdc_sync_reset); 304 /* Remove the LPASS reset */ 305 reset_control_deassert(adsp->restart); 306 /* wait after de-asserting subsystem restart from AOSS */ 307 usleep_range(200, 300); 308 309 return 0; 310 } 311 312 static int adsp_load(struct rproc *rproc, const struct firmware *fw) 313 { 314 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 315 int ret; 316 317 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0, 318 adsp->mem_region, adsp->mem_phys, 319 adsp->mem_size, &adsp->mem_reloc); 320 if (ret) 321 return ret; 322 323 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); 324 325 return 0; 326 } 327 328 static int adsp_start(struct rproc *rproc) 329 { 330 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 331 int ret; 332 unsigned int val; 333 334 ret = qcom_q6v5_prepare(&adsp->q6v5); 335 if (ret) 336 return ret; 337 338 ret = clk_prepare_enable(adsp->xo); 339 if (ret) 340 goto disable_irqs; 341 342 ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds, 343 adsp->proxy_pd_count); 344 if (ret < 0) 345 goto disable_xo_clk; 346 347 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks); 348 if (ret) { 349 dev_err(adsp->dev, "adsp clk_enable failed\n"); 350 goto disable_power_domain; 351 } 352 353 /* Enable the XO clock */ 354 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR); 355 356 /* Enable the QDSP6SS sleep clock */ 357 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR); 358 359 /* Enable the QDSP6 core clock */ 360 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR); 361 362 /* Program boot address */ 363 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); 364 365 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ 366 writel(0x1, adsp->qdsp6ss_base + CORE_START_REG); 367 368 /* Trigger boot FSM to start QDSP6 */ 369 writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG); 370 371 /* Wait for core to come out of reset */ 372 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG, 373 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); 374 if (ret) { 375 dev_err(adsp->dev, "failed to bootup adsp\n"); 376 goto disable_adsp_clks; 377 } 378 379 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ)); 380 if (ret == -ETIMEDOUT) { 381 dev_err(adsp->dev, "start timed out\n"); 382 goto disable_adsp_clks; 383 } 384 385 return 0; 386 387 disable_adsp_clks: 388 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 389 disable_power_domain: 390 qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 391 disable_xo_clk: 392 clk_disable_unprepare(adsp->xo); 393 disable_irqs: 394 qcom_q6v5_unprepare(&adsp->q6v5); 395 396 return ret; 397 } 398 399 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5) 400 { 401 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5); 402 403 clk_disable_unprepare(adsp->xo); 404 qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 405 } 406 407 static int adsp_stop(struct rproc *rproc) 408 { 409 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 410 int handover; 411 int ret; 412 413 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon); 414 if (ret == -ETIMEDOUT) 415 dev_err(adsp->dev, "timed out on wait\n"); 416 417 ret = adsp->shutdown(adsp); 418 if (ret) 419 dev_err(adsp->dev, "failed to shutdown: %d\n", ret); 420 421 handover = qcom_q6v5_unprepare(&adsp->q6v5); 422 if (handover) 423 qcom_adsp_pil_handover(&adsp->q6v5); 424 425 return ret; 426 } 427 428 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) 429 { 430 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 431 int offset; 432 433 offset = da - adsp->mem_reloc; 434 if (offset < 0 || offset + len > adsp->mem_size) 435 return NULL; 436 437 return adsp->mem_region + offset; 438 } 439 440 static unsigned long adsp_panic(struct rproc *rproc) 441 { 442 struct qcom_adsp *adsp = rproc->priv; 443 444 return qcom_q6v5_panic(&adsp->q6v5); 445 } 446 447 static const struct rproc_ops adsp_ops = { 448 .start = adsp_start, 449 .stop = adsp_stop, 450 .da_to_va = adsp_da_to_va, 451 .parse_fw = qcom_register_dump_segments, 452 .load = adsp_load, 453 .panic = adsp_panic, 454 }; 455 456 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids) 457 { 458 int num_clks = 0; 459 int i, ret; 460 461 adsp->xo = devm_clk_get(adsp->dev, "xo"); 462 if (IS_ERR(adsp->xo)) { 463 ret = PTR_ERR(adsp->xo); 464 if (ret != -EPROBE_DEFER) 465 dev_err(adsp->dev, "failed to get xo clock"); 466 return ret; 467 } 468 469 for (i = 0; clk_ids[i]; i++) 470 num_clks++; 471 472 adsp->num_clks = num_clks; 473 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks, 474 sizeof(*adsp->clks), GFP_KERNEL); 475 if (!adsp->clks) 476 return -ENOMEM; 477 478 for (i = 0; i < adsp->num_clks; i++) 479 adsp->clks[i].id = clk_ids[i]; 480 481 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks); 482 } 483 484 static int adsp_init_reset(struct qcom_adsp *adsp) 485 { 486 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev, 487 "pdc_sync"); 488 if (IS_ERR(adsp->pdc_sync_reset)) { 489 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n"); 490 return PTR_ERR(adsp->pdc_sync_reset); 491 } 492 493 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart"); 494 495 /* Fall back to the old "cc_lpass" if "restart" is absent */ 496 if (!adsp->restart) 497 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass"); 498 499 if (IS_ERR(adsp->restart)) { 500 dev_err(adsp->dev, "failed to acquire restart\n"); 501 return PTR_ERR(adsp->restart); 502 } 503 504 return 0; 505 } 506 507 static int adsp_init_mmio(struct qcom_adsp *adsp, 508 struct platform_device *pdev) 509 { 510 struct device_node *syscon; 511 int ret; 512 513 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0); 514 if (IS_ERR(adsp->qdsp6ss_base)) { 515 dev_err(adsp->dev, "failed to map QDSP6SS registers\n"); 516 return PTR_ERR(adsp->qdsp6ss_base); 517 } 518 519 syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0); 520 if (!syscon) { 521 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 522 return -EINVAL; 523 } 524 525 adsp->halt_map = syscon_node_to_regmap(syscon); 526 of_node_put(syscon); 527 if (IS_ERR(adsp->halt_map)) 528 return PTR_ERR(adsp->halt_map); 529 530 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs", 531 1, &adsp->halt_lpass); 532 if (ret < 0) { 533 dev_err(&pdev->dev, "no offset in syscon\n"); 534 return ret; 535 } 536 537 return 0; 538 } 539 540 static int adsp_alloc_memory_region(struct qcom_adsp *adsp) 541 { 542 struct device_node *node; 543 struct resource r; 544 int ret; 545 546 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0); 547 if (!node) { 548 dev_err(adsp->dev, "no memory-region specified\n"); 549 return -EINVAL; 550 } 551 552 ret = of_address_to_resource(node, 0, &r); 553 of_node_put(node); 554 if (ret) 555 return ret; 556 557 adsp->mem_phys = adsp->mem_reloc = r.start; 558 adsp->mem_size = resource_size(&r); 559 adsp->mem_region = devm_ioremap_wc(adsp->dev, 560 adsp->mem_phys, adsp->mem_size); 561 if (!adsp->mem_region) { 562 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n", 563 &r.start, adsp->mem_size); 564 return -EBUSY; 565 } 566 567 return 0; 568 } 569 570 static int adsp_probe(struct platform_device *pdev) 571 { 572 const struct adsp_pil_data *desc; 573 const char *firmware_name; 574 struct qcom_adsp *adsp; 575 struct rproc *rproc; 576 int ret; 577 578 desc = of_device_get_match_data(&pdev->dev); 579 if (!desc) 580 return -EINVAL; 581 582 firmware_name = desc->firmware_name; 583 ret = of_property_read_string(pdev->dev.of_node, "firmware-name", 584 &firmware_name); 585 if (ret < 0 && ret != -EINVAL) { 586 dev_err(&pdev->dev, "unable to read firmware-name\n"); 587 return ret; 588 } 589 590 rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops, 591 firmware_name, sizeof(*adsp)); 592 if (!rproc) { 593 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 594 return -ENOMEM; 595 } 596 597 rproc->auto_boot = desc->auto_boot; 598 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 599 600 adsp = (struct qcom_adsp *)rproc->priv; 601 adsp->dev = &pdev->dev; 602 adsp->rproc = rproc; 603 adsp->info_name = desc->sysmon_name; 604 platform_set_drvdata(pdev, adsp); 605 606 if (desc->is_wpss) 607 adsp->shutdown = qcom_wpss_shutdown; 608 else 609 adsp->shutdown = qcom_adsp_shutdown; 610 611 ret = adsp_alloc_memory_region(adsp); 612 if (ret) 613 goto free_rproc; 614 615 ret = adsp_init_clock(adsp, desc->clk_ids); 616 if (ret) 617 goto free_rproc; 618 619 ret = qcom_rproc_pds_attach(adsp->dev, adsp, 620 desc->proxy_pd_names); 621 if (ret < 0) { 622 dev_err(&pdev->dev, "Failed to attach proxy power domains\n"); 623 goto free_rproc; 624 } 625 adsp->proxy_pd_count = ret; 626 627 ret = adsp_init_reset(adsp); 628 if (ret) 629 goto disable_pm; 630 631 ret = adsp_init_mmio(adsp, pdev); 632 if (ret) 633 goto disable_pm; 634 635 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, 636 desc->load_state, qcom_adsp_pil_handover); 637 if (ret) 638 goto disable_pm; 639 640 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name); 641 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); 642 adsp->sysmon = qcom_add_sysmon_subdev(rproc, 643 desc->sysmon_name, 644 desc->ssctl_id); 645 if (IS_ERR(adsp->sysmon)) { 646 ret = PTR_ERR(adsp->sysmon); 647 goto disable_pm; 648 } 649 650 ret = rproc_add(rproc); 651 if (ret) 652 goto disable_pm; 653 654 return 0; 655 656 disable_pm: 657 qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 658 659 free_rproc: 660 rproc_free(rproc); 661 662 return ret; 663 } 664 665 static int adsp_remove(struct platform_device *pdev) 666 { 667 struct qcom_adsp *adsp = platform_get_drvdata(pdev); 668 669 rproc_del(adsp->rproc); 670 671 qcom_q6v5_deinit(&adsp->q6v5); 672 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); 673 qcom_remove_sysmon_subdev(adsp->sysmon); 674 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev); 675 qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 676 rproc_free(adsp->rproc); 677 678 return 0; 679 } 680 681 static const struct adsp_pil_data adsp_resource_init = { 682 .crash_reason_smem = 423, 683 .firmware_name = "adsp.mdt", 684 .ssr_name = "lpass", 685 .sysmon_name = "adsp", 686 .ssctl_id = 0x14, 687 .is_wpss = false, 688 .auto_boot = true, 689 .clk_ids = (const char*[]) { 690 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", 691 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL 692 }, 693 .num_clks = 7, 694 .proxy_pd_names = (const char*[]) { 695 "cx", NULL 696 }, 697 }; 698 699 static const struct adsp_pil_data cdsp_resource_init = { 700 .crash_reason_smem = 601, 701 .firmware_name = "cdsp.mdt", 702 .ssr_name = "cdsp", 703 .sysmon_name = "cdsp", 704 .ssctl_id = 0x17, 705 .is_wpss = false, 706 .auto_boot = true, 707 .clk_ids = (const char*[]) { 708 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master", 709 "q6_axim", NULL 710 }, 711 .num_clks = 7, 712 .proxy_pd_names = (const char*[]) { 713 "cx", NULL 714 }, 715 }; 716 717 static const struct adsp_pil_data wpss_resource_init = { 718 .crash_reason_smem = 626, 719 .firmware_name = "wpss.mdt", 720 .ssr_name = "wpss", 721 .sysmon_name = "wpss", 722 .ssctl_id = 0x19, 723 .is_wpss = true, 724 .auto_boot = false, 725 .load_state = "wpss", 726 .clk_ids = (const char*[]) { 727 "ahb_bdg", "ahb", "rscp", NULL 728 }, 729 .num_clks = 3, 730 .proxy_pd_names = (const char*[]) { 731 "cx", "mx", NULL 732 }, 733 }; 734 735 static const struct of_device_id adsp_of_match[] = { 736 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, 737 { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init }, 738 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, 739 { }, 740 }; 741 MODULE_DEVICE_TABLE(of, adsp_of_match); 742 743 static struct platform_driver adsp_pil_driver = { 744 .probe = adsp_probe, 745 .remove = adsp_remove, 746 .driver = { 747 .name = "qcom_q6v5_adsp", 748 .of_match_table = adsp_of_match, 749 }, 750 }; 751 752 module_platform_driver(adsp_pil_driver); 753 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader"); 754 MODULE_LICENSE("GPL v2"); 755