1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
4  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/firmware.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_domain.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/remoteproc.h>
23 #include <linux/reset.h>
24 #include <linux/soc/qcom/mdt_loader.h>
25 #include <linux/soc/qcom/smem.h>
26 #include <linux/soc/qcom/smem_state.h>
27 
28 #include "qcom_common.h"
29 #include "qcom_pil_info.h"
30 #include "qcom_q6v5.h"
31 #include "remoteproc_internal.h"
32 
33 /* time out value */
34 #define ACK_TIMEOUT			1000
35 #define BOOT_FSM_TIMEOUT		10000
36 /* mask values */
37 #define EVB_MASK			GENMASK(27, 4)
38 /*QDSP6SS register offsets*/
39 #define RST_EVB_REG			0x10
40 #define CORE_START_REG			0x400
41 #define BOOT_CMD_REG			0x404
42 #define BOOT_STATUS_REG			0x408
43 #define RET_CFG_REG			0x1C
44 /*TCSR register offsets*/
45 #define LPASS_MASTER_IDLE_REG		0x8
46 #define LPASS_HALTACK_REG		0x4
47 #define LPASS_PWR_ON_REG		0x10
48 #define LPASS_HALTREQ_REG		0x0
49 
50 #define QDSP6SS_XO_CBCR		0x38
51 #define QDSP6SS_CORE_CBCR	0x20
52 #define QDSP6SS_SLEEP_CBCR	0x3c
53 
54 struct adsp_pil_data {
55 	int crash_reason_smem;
56 	const char *firmware_name;
57 
58 	const char *ssr_name;
59 	const char *sysmon_name;
60 	int ssctl_id;
61 
62 	const char **clk_ids;
63 	int num_clks;
64 };
65 
66 struct qcom_adsp {
67 	struct device *dev;
68 	struct rproc *rproc;
69 
70 	struct qcom_q6v5 q6v5;
71 
72 	struct clk *xo;
73 
74 	int num_clks;
75 	struct clk_bulk_data *clks;
76 
77 	void __iomem *qdsp6ss_base;
78 
79 	struct reset_control *pdc_sync_reset;
80 	struct reset_control *restart;
81 
82 	struct regmap *halt_map;
83 	unsigned int halt_lpass;
84 
85 	int crash_reason_smem;
86 	const char *info_name;
87 
88 	struct completion start_done;
89 	struct completion stop_done;
90 
91 	phys_addr_t mem_phys;
92 	phys_addr_t mem_reloc;
93 	void *mem_region;
94 	size_t mem_size;
95 
96 	struct qcom_rproc_glink glink_subdev;
97 	struct qcom_rproc_ssr ssr_subdev;
98 	struct qcom_sysmon *sysmon;
99 };
100 
101 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
102 {
103 	unsigned long timeout;
104 	unsigned int val;
105 	int ret;
106 
107 	/* Reset the retention logic */
108 	val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
109 	val |= 0x1;
110 	writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
111 
112 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
113 
114 	/* QDSP6 master port needs to be explicitly halted */
115 	ret = regmap_read(adsp->halt_map,
116 			adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
117 	if (ret || !val)
118 		goto reset;
119 
120 	ret = regmap_read(adsp->halt_map,
121 			adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
122 			&val);
123 	if (ret || val)
124 		goto reset;
125 
126 	regmap_write(adsp->halt_map,
127 			adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
128 
129 	/* Wait for halt ACK from QDSP6 */
130 	timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
131 	for (;;) {
132 		ret = regmap_read(adsp->halt_map,
133 			adsp->halt_lpass + LPASS_HALTACK_REG, &val);
134 		if (ret || val || time_after(jiffies, timeout))
135 			break;
136 
137 		usleep_range(1000, 1100);
138 	}
139 
140 	ret = regmap_read(adsp->halt_map,
141 			adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
142 	if (ret || !val)
143 		dev_err(adsp->dev, "port failed halt\n");
144 
145 reset:
146 	/* Assert the LPASS PDC Reset */
147 	reset_control_assert(adsp->pdc_sync_reset);
148 	/* Place the LPASS processor into reset */
149 	reset_control_assert(adsp->restart);
150 	/* wait after asserting subsystem restart from AOSS */
151 	usleep_range(200, 300);
152 
153 	/* Clear the halt request for the AXIM and AHBM for Q6 */
154 	regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
155 
156 	/* De-assert the LPASS PDC Reset */
157 	reset_control_deassert(adsp->pdc_sync_reset);
158 	/* Remove the LPASS reset */
159 	reset_control_deassert(adsp->restart);
160 	/* wait after de-asserting subsystem restart from AOSS */
161 	usleep_range(200, 300);
162 
163 	return 0;
164 }
165 
166 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
167 {
168 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
169 	int ret;
170 
171 	ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
172 				    adsp->mem_region, adsp->mem_phys,
173 				    adsp->mem_size, &adsp->mem_reloc);
174 	if (ret)
175 		return ret;
176 
177 	qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
178 
179 	return 0;
180 }
181 
182 static int adsp_start(struct rproc *rproc)
183 {
184 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
185 	int ret;
186 	unsigned int val;
187 
188 	qcom_q6v5_prepare(&adsp->q6v5);
189 
190 	ret = clk_prepare_enable(adsp->xo);
191 	if (ret)
192 		goto disable_irqs;
193 
194 	dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
195 	ret = pm_runtime_get_sync(adsp->dev);
196 	if (ret)
197 		goto disable_xo_clk;
198 
199 	ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
200 	if (ret) {
201 		dev_err(adsp->dev, "adsp clk_enable failed\n");
202 		goto disable_power_domain;
203 	}
204 
205 	/* Enable the XO clock */
206 	writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
207 
208 	/* Enable the QDSP6SS sleep clock */
209 	writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
210 
211 	/* Enable the QDSP6 core clock */
212 	writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
213 
214 	/* Program boot address */
215 	writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
216 
217 	/* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
218 	writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
219 
220 	/* Trigger boot FSM to start QDSP6 */
221 	writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
222 
223 	/* Wait for core to come out of reset */
224 	ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
225 			val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
226 	if (ret) {
227 		dev_err(adsp->dev, "failed to bootup adsp\n");
228 		goto disable_adsp_clks;
229 	}
230 
231 	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
232 	if (ret == -ETIMEDOUT) {
233 		dev_err(adsp->dev, "start timed out\n");
234 		goto disable_adsp_clks;
235 	}
236 
237 	return 0;
238 
239 disable_adsp_clks:
240 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
241 disable_power_domain:
242 	dev_pm_genpd_set_performance_state(adsp->dev, 0);
243 	pm_runtime_put(adsp->dev);
244 disable_xo_clk:
245 	clk_disable_unprepare(adsp->xo);
246 disable_irqs:
247 	qcom_q6v5_unprepare(&adsp->q6v5);
248 
249 	return ret;
250 }
251 
252 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
253 {
254 	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
255 
256 	clk_disable_unprepare(adsp->xo);
257 	dev_pm_genpd_set_performance_state(adsp->dev, 0);
258 	pm_runtime_put(adsp->dev);
259 }
260 
261 static int adsp_stop(struct rproc *rproc)
262 {
263 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
264 	int handover;
265 	int ret;
266 
267 	ret = qcom_q6v5_request_stop(&adsp->q6v5);
268 	if (ret == -ETIMEDOUT)
269 		dev_err(adsp->dev, "timed out on wait\n");
270 
271 	ret = qcom_adsp_shutdown(adsp);
272 	if (ret)
273 		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
274 
275 	handover = qcom_q6v5_unprepare(&adsp->q6v5);
276 	if (handover)
277 		qcom_adsp_pil_handover(&adsp->q6v5);
278 
279 	return ret;
280 }
281 
282 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len)
283 {
284 	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
285 	int offset;
286 
287 	offset = da - adsp->mem_reloc;
288 	if (offset < 0 || offset + len > adsp->mem_size)
289 		return NULL;
290 
291 	return adsp->mem_region + offset;
292 }
293 
294 static unsigned long adsp_panic(struct rproc *rproc)
295 {
296 	struct qcom_adsp *adsp = rproc->priv;
297 
298 	return qcom_q6v5_panic(&adsp->q6v5);
299 }
300 
301 static const struct rproc_ops adsp_ops = {
302 	.start = adsp_start,
303 	.stop = adsp_stop,
304 	.da_to_va = adsp_da_to_va,
305 	.parse_fw = qcom_register_dump_segments,
306 	.load = adsp_load,
307 	.panic = adsp_panic,
308 };
309 
310 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
311 {
312 	int num_clks = 0;
313 	int i, ret;
314 
315 	adsp->xo = devm_clk_get(adsp->dev, "xo");
316 	if (IS_ERR(adsp->xo)) {
317 		ret = PTR_ERR(adsp->xo);
318 		if (ret != -EPROBE_DEFER)
319 			dev_err(adsp->dev, "failed to get xo clock");
320 		return ret;
321 	}
322 
323 	for (i = 0; clk_ids[i]; i++)
324 		num_clks++;
325 
326 	adsp->num_clks = num_clks;
327 	adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
328 				sizeof(*adsp->clks), GFP_KERNEL);
329 	if (!adsp->clks)
330 		return -ENOMEM;
331 
332 	for (i = 0; i < adsp->num_clks; i++)
333 		adsp->clks[i].id = clk_ids[i];
334 
335 	return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
336 }
337 
338 static int adsp_init_reset(struct qcom_adsp *adsp)
339 {
340 	adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
341 			"pdc_sync");
342 	if (IS_ERR(adsp->pdc_sync_reset)) {
343 		dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
344 		return PTR_ERR(adsp->pdc_sync_reset);
345 	}
346 
347 	adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
348 
349 	/* Fall back to the  old "cc_lpass" if "restart" is absent */
350 	if (!adsp->restart)
351 		adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
352 
353 	if (IS_ERR(adsp->restart)) {
354 		dev_err(adsp->dev, "failed to acquire restart\n");
355 		return PTR_ERR(adsp->restart);
356 	}
357 
358 	return 0;
359 }
360 
361 static int adsp_init_mmio(struct qcom_adsp *adsp,
362 				struct platform_device *pdev)
363 {
364 	struct device_node *syscon;
365 	struct resource *res;
366 	int ret;
367 
368 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369 	adsp->qdsp6ss_base = devm_ioremap(&pdev->dev, res->start,
370 			resource_size(res));
371 	if (!adsp->qdsp6ss_base) {
372 		dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
373 		return -ENOMEM;
374 	}
375 
376 	syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
377 	if (!syscon) {
378 		dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
379 		return -EINVAL;
380 	}
381 
382 	adsp->halt_map = syscon_node_to_regmap(syscon);
383 	of_node_put(syscon);
384 	if (IS_ERR(adsp->halt_map))
385 		return PTR_ERR(adsp->halt_map);
386 
387 	ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
388 			1, &adsp->halt_lpass);
389 	if (ret < 0) {
390 		dev_err(&pdev->dev, "no offset in syscon\n");
391 		return ret;
392 	}
393 
394 	return 0;
395 }
396 
397 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
398 {
399 	struct device_node *node;
400 	struct resource r;
401 	int ret;
402 
403 	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
404 	if (!node) {
405 		dev_err(adsp->dev, "no memory-region specified\n");
406 		return -EINVAL;
407 	}
408 
409 	ret = of_address_to_resource(node, 0, &r);
410 	if (ret)
411 		return ret;
412 
413 	adsp->mem_phys = adsp->mem_reloc = r.start;
414 	adsp->mem_size = resource_size(&r);
415 	adsp->mem_region = devm_ioremap_wc(adsp->dev,
416 				adsp->mem_phys, adsp->mem_size);
417 	if (!adsp->mem_region) {
418 		dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
419 			&r.start, adsp->mem_size);
420 		return -EBUSY;
421 	}
422 
423 	return 0;
424 }
425 
426 static int adsp_probe(struct platform_device *pdev)
427 {
428 	const struct adsp_pil_data *desc;
429 	struct qcom_adsp *adsp;
430 	struct rproc *rproc;
431 	int ret;
432 
433 	desc = of_device_get_match_data(&pdev->dev);
434 	if (!desc)
435 		return -EINVAL;
436 
437 	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
438 			    desc->firmware_name, sizeof(*adsp));
439 	if (!rproc) {
440 		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
441 		return -ENOMEM;
442 	}
443 	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
444 
445 	adsp = (struct qcom_adsp *)rproc->priv;
446 	adsp->dev = &pdev->dev;
447 	adsp->rproc = rproc;
448 	adsp->info_name = desc->sysmon_name;
449 	platform_set_drvdata(pdev, adsp);
450 
451 	ret = adsp_alloc_memory_region(adsp);
452 	if (ret)
453 		goto free_rproc;
454 
455 	ret = adsp_init_clock(adsp, desc->clk_ids);
456 	if (ret)
457 		goto free_rproc;
458 
459 	pm_runtime_enable(adsp->dev);
460 
461 	ret = adsp_init_reset(adsp);
462 	if (ret)
463 		goto disable_pm;
464 
465 	ret = adsp_init_mmio(adsp, pdev);
466 	if (ret)
467 		goto disable_pm;
468 
469 	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
470 			     qcom_adsp_pil_handover);
471 	if (ret)
472 		goto disable_pm;
473 
474 	qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
475 	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
476 	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
477 					      desc->sysmon_name,
478 					      desc->ssctl_id);
479 	if (IS_ERR(adsp->sysmon)) {
480 		ret = PTR_ERR(adsp->sysmon);
481 		goto disable_pm;
482 	}
483 
484 	ret = rproc_add(rproc);
485 	if (ret)
486 		goto disable_pm;
487 
488 	return 0;
489 
490 disable_pm:
491 	pm_runtime_disable(adsp->dev);
492 free_rproc:
493 	rproc_free(rproc);
494 
495 	return ret;
496 }
497 
498 static int adsp_remove(struct platform_device *pdev)
499 {
500 	struct qcom_adsp *adsp = platform_get_drvdata(pdev);
501 
502 	rproc_del(adsp->rproc);
503 
504 	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
505 	qcom_remove_sysmon_subdev(adsp->sysmon);
506 	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
507 	pm_runtime_disable(adsp->dev);
508 	rproc_free(adsp->rproc);
509 
510 	return 0;
511 }
512 
513 static const struct adsp_pil_data adsp_resource_init = {
514 	.crash_reason_smem = 423,
515 	.firmware_name = "adsp.mdt",
516 	.ssr_name = "lpass",
517 	.sysmon_name = "adsp",
518 	.ssctl_id = 0x14,
519 	.clk_ids = (const char*[]) {
520 		"sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
521 		"qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
522 	},
523 	.num_clks = 7,
524 };
525 
526 static const struct adsp_pil_data cdsp_resource_init = {
527 	.crash_reason_smem = 601,
528 	.firmware_name = "cdsp.mdt",
529 	.ssr_name = "cdsp",
530 	.sysmon_name = "cdsp",
531 	.ssctl_id = 0x17,
532 	.clk_ids = (const char*[]) {
533 		"sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
534 		"q6_axim", NULL
535 	},
536 	.num_clks = 7,
537 };
538 
539 static const struct of_device_id adsp_of_match[] = {
540 	{ .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
541 	{ .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
542 	{ },
543 };
544 MODULE_DEVICE_TABLE(of, adsp_of_match);
545 
546 static struct platform_driver adsp_pil_driver = {
547 	.probe = adsp_probe,
548 	.remove = adsp_remove,
549 	.driver = {
550 		.name = "qcom_q6v5_adsp",
551 		.of_match_table = adsp_of_match,
552 	},
553 };
554 
555 module_platform_driver(adsp_pil_driver);
556 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
557 MODULE_LICENSE("GPL v2");
558