1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 */ 5 6 #ifndef __RPROC_MTK_COMMON_H 7 #define __RPROC_MTK_COMMON_H 8 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/platform_device.h> 12 #include <linux/remoteproc.h> 13 #include <linux/remoteproc/mtk_scp.h> 14 15 #define MT8183_SW_RSTN 0x0 16 #define MT8183_SW_RSTN_BIT BIT(0) 17 #define MT8183_SCP_TO_HOST 0x1C 18 #define MT8183_SCP_IPC_INT_BIT BIT(0) 19 #define MT8183_SCP_WDT_INT_BIT BIT(8) 20 #define MT8183_HOST_TO_SCP 0x28 21 #define MT8183_HOST_IPC_INT_BIT BIT(0) 22 #define MT8183_WDT_CFG 0x84 23 #define MT8183_SCP_CLK_SW_SEL 0x4000 24 #define MT8183_SCP_CLK_DIV_SEL 0x4024 25 #define MT8183_SCP_SRAM_PDN 0x402C 26 #define MT8183_SCP_L1_SRAM_PD 0x4080 27 #define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094 28 29 #define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000) 30 #define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0) 31 #define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1) 32 #define MT8183_SCP_CACHESIZE_8KB BIT(8) 33 #define MT8183_SCP_CACHE_CON_WAYEN BIT(10) 34 35 #define MT8186_SCP_L1_SRAM_PD_P1 0x40B0 36 #define MT8186_SCP_L1_SRAM_PD_p2 0x40B4 37 38 #define MT8192_L2TCM_SRAM_PD_0 0x10C0 39 #define MT8192_L2TCM_SRAM_PD_1 0x10C4 40 #define MT8192_L2TCM_SRAM_PD_2 0x10C8 41 #define MT8192_L1TCM_SRAM_PDN 0x102C 42 #define MT8192_CPU0_SRAM_PD 0x1080 43 44 #define MT8192_SCP2APMCU_IPC_SET 0x4080 45 #define MT8192_SCP2APMCU_IPC_CLR 0x4084 46 #define MT8192_SCP_IPC_INT_BIT BIT(0) 47 #define MT8192_SCP2SPM_IPC_CLR 0x4094 48 #define MT8192_GIPC_IN_SET 0x4098 49 #define MT8192_HOST_IPC_INT_BIT BIT(0) 50 51 #define MT8192_CORE0_SW_RSTN_CLR 0x10000 52 #define MT8192_CORE0_SW_RSTN_SET 0x10004 53 #define MT8192_CORE0_MEM_ATT_PREDEF 0x10008 54 #define MT8192_CORE0_WDT_IRQ 0x10030 55 #define MT8192_CORE0_WDT_CFG 0x10034 56 57 #define SCP_FW_VER_LEN 32 58 #define SCP_SHARE_BUFFER_SIZE 288 59 60 struct scp_run { 61 u32 signaled; 62 s8 fw_ver[SCP_FW_VER_LEN]; 63 u32 dec_capability; 64 u32 enc_capability; 65 wait_queue_head_t wq; 66 }; 67 68 struct scp_ipi_desc { 69 /* For protecting handler. */ 70 struct mutex lock; 71 scp_ipi_handler_t handler; 72 void *priv; 73 }; 74 75 struct mtk_scp; 76 77 struct mtk_scp_of_data { 78 int (*scp_clk_get)(struct mtk_scp *scp); 79 int (*scp_before_load)(struct mtk_scp *scp); 80 void (*scp_irq_handler)(struct mtk_scp *scp); 81 void (*scp_reset_assert)(struct mtk_scp *scp); 82 void (*scp_reset_deassert)(struct mtk_scp *scp); 83 void (*scp_stop)(struct mtk_scp *scp); 84 void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len); 85 86 u32 host_to_scp_reg; 87 u32 host_to_scp_int_bit; 88 89 size_t ipi_buf_offset; 90 }; 91 92 struct mtk_scp { 93 struct device *dev; 94 struct rproc *rproc; 95 struct clk *clk; 96 void __iomem *reg_base; 97 void __iomem *sram_base; 98 size_t sram_size; 99 phys_addr_t sram_phys; 100 void __iomem *l1tcm_base; 101 size_t l1tcm_size; 102 phys_addr_t l1tcm_phys; 103 104 const struct mtk_scp_of_data *data; 105 106 struct mtk_share_obj __iomem *recv_buf; 107 struct mtk_share_obj __iomem *send_buf; 108 struct scp_run run; 109 /* To prevent multiple ipi_send run concurrently. */ 110 struct mutex send_lock; 111 struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; 112 bool ipi_id_ack[SCP_IPI_MAX]; 113 wait_queue_head_t ack_wq; 114 115 void *cpu_addr; 116 dma_addr_t dma_addr; 117 size_t dram_size; 118 119 struct rproc_subdev *rpmsg_subdev; 120 }; 121 122 /** 123 * struct mtk_share_obj - SRAM buffer shared with AP and SCP 124 * 125 * @id: IPI id 126 * @len: share buffer length 127 * @share_buf: share buffer data 128 */ 129 struct mtk_share_obj { 130 u32 id; 131 u32 len; 132 u8 share_buf[SCP_SHARE_BUFFER_SIZE]; 133 }; 134 135 void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); 136 void scp_ipi_lock(struct mtk_scp *scp, u32 id); 137 void scp_ipi_unlock(struct mtk_scp *scp, u32 id); 138 139 #endif 140