163c13d61SErin Lo /* SPDX-License-Identifier: GPL-2.0 */ 263c13d61SErin Lo /* 363c13d61SErin Lo * Copyright (c) 2019 MediaTek Inc. 463c13d61SErin Lo */ 563c13d61SErin Lo 663c13d61SErin Lo #ifndef __RPROC_MTK_COMMON_H 763c13d61SErin Lo #define __RPROC_MTK_COMMON_H 863c13d61SErin Lo 963c13d61SErin Lo #include <linux/interrupt.h> 1063c13d61SErin Lo #include <linux/kernel.h> 1163c13d61SErin Lo #include <linux/platform_device.h> 1263c13d61SErin Lo #include <linux/remoteproc.h> 1363c13d61SErin Lo #include <linux/remoteproc/mtk_scp.h> 1463c13d61SErin Lo 1563c13d61SErin Lo #define MT8183_SW_RSTN 0x0 1663c13d61SErin Lo #define MT8183_SW_RSTN_BIT BIT(0) 1763c13d61SErin Lo #define MT8183_SCP_TO_HOST 0x1C 1863c13d61SErin Lo #define MT8183_SCP_IPC_INT_BIT BIT(0) 1963c13d61SErin Lo #define MT8183_SCP_WDT_INT_BIT BIT(8) 2063c13d61SErin Lo #define MT8183_HOST_TO_SCP 0x28 2163c13d61SErin Lo #define MT8183_HOST_IPC_INT_BIT BIT(0) 2263c13d61SErin Lo #define MT8183_WDT_CFG 0x84 2363c13d61SErin Lo #define MT8183_SCP_CLK_SW_SEL 0x4000 2463c13d61SErin Lo #define MT8183_SCP_CLK_DIV_SEL 0x4024 2563c13d61SErin Lo #define MT8183_SCP_SRAM_PDN 0x402C 2663c13d61SErin Lo #define MT8183_SCP_L1_SRAM_PD 0x4080 2763c13d61SErin Lo #define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094 2863c13d61SErin Lo 2963c13d61SErin Lo #define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000) 3063c13d61SErin Lo #define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0) 3163c13d61SErin Lo #define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1) 3263c13d61SErin Lo #define MT8183_SCP_CACHESIZE_8KB BIT(8) 3363c13d61SErin Lo #define MT8183_SCP_CACHE_CON_WAYEN BIT(10) 3463c13d61SErin Lo 35*0a441514STzung-Bi Shih #define MT8192_L2TCM_SRAM_PD_0 0x10C0 36*0a441514STzung-Bi Shih #define MT8192_L2TCM_SRAM_PD_1 0x10C4 37*0a441514STzung-Bi Shih #define MT8192_L2TCM_SRAM_PD_2 0x10C8 38*0a441514STzung-Bi Shih #define MT8192_L1TCM_SRAM_PDN 0x102C 39*0a441514STzung-Bi Shih #define MT8192_CPU0_SRAM_PD 0x1080 40fd0b6c1fSPi-Hsun Shih 41*0a441514STzung-Bi Shih #define MT8192_SCP2APMCU_IPC_SET 0x4080 42*0a441514STzung-Bi Shih #define MT8192_SCP2APMCU_IPC_CLR 0x4084 43fd0b6c1fSPi-Hsun Shih #define MT8192_SCP_IPC_INT_BIT BIT(0) 44*0a441514STzung-Bi Shih #define MT8192_SCP2SPM_IPC_CLR 0x4094 45*0a441514STzung-Bi Shih #define MT8192_GIPC_IN_SET 0x4098 46fd0b6c1fSPi-Hsun Shih #define MT8192_HOST_IPC_INT_BIT BIT(0) 47fd0b6c1fSPi-Hsun Shih 48*0a441514STzung-Bi Shih #define MT8192_CORE0_SW_RSTN_CLR 0x10000 49*0a441514STzung-Bi Shih #define MT8192_CORE0_SW_RSTN_SET 0x10004 50*0a441514STzung-Bi Shih #define MT8192_CORE0_WDT_CFG 0x10034 51fd0b6c1fSPi-Hsun Shih 5263c13d61SErin Lo #define SCP_FW_VER_LEN 32 5363c13d61SErin Lo #define SCP_SHARE_BUFFER_SIZE 288 5463c13d61SErin Lo 5563c13d61SErin Lo struct scp_run { 5663c13d61SErin Lo u32 signaled; 5763c13d61SErin Lo s8 fw_ver[SCP_FW_VER_LEN]; 5863c13d61SErin Lo u32 dec_capability; 5963c13d61SErin Lo u32 enc_capability; 6063c13d61SErin Lo wait_queue_head_t wq; 6163c13d61SErin Lo }; 6263c13d61SErin Lo 6363c13d61SErin Lo struct scp_ipi_desc { 6463c13d61SErin Lo /* For protecting handler. */ 6563c13d61SErin Lo struct mutex lock; 6663c13d61SErin Lo scp_ipi_handler_t handler; 6763c13d61SErin Lo void *priv; 6863c13d61SErin Lo }; 6963c13d61SErin Lo 70fd0b6c1fSPi-Hsun Shih struct mtk_scp; 71fd0b6c1fSPi-Hsun Shih 72fd0b6c1fSPi-Hsun Shih struct mtk_scp_of_data { 73fd0b6c1fSPi-Hsun Shih int (*scp_before_load)(struct mtk_scp *scp); 74fd0b6c1fSPi-Hsun Shih void (*scp_irq_handler)(struct mtk_scp *scp); 75fd0b6c1fSPi-Hsun Shih void (*scp_reset_assert)(struct mtk_scp *scp); 76fd0b6c1fSPi-Hsun Shih void (*scp_reset_deassert)(struct mtk_scp *scp); 77fd0b6c1fSPi-Hsun Shih void (*scp_stop)(struct mtk_scp *scp); 78fd0b6c1fSPi-Hsun Shih 79fd0b6c1fSPi-Hsun Shih u32 host_to_scp_reg; 80fd0b6c1fSPi-Hsun Shih u32 host_to_scp_int_bit; 81fd0b6c1fSPi-Hsun Shih }; 82fd0b6c1fSPi-Hsun Shih 8363c13d61SErin Lo struct mtk_scp { 8463c13d61SErin Lo struct device *dev; 8563c13d61SErin Lo struct rproc *rproc; 8663c13d61SErin Lo struct clk *clk; 8763c13d61SErin Lo void __iomem *reg_base; 8863c13d61SErin Lo void __iomem *sram_base; 8963c13d61SErin Lo size_t sram_size; 9063c13d61SErin Lo 91fd0b6c1fSPi-Hsun Shih const struct mtk_scp_of_data *data; 92fd0b6c1fSPi-Hsun Shih 9363c13d61SErin Lo struct mtk_share_obj __iomem *recv_buf; 9463c13d61SErin Lo struct mtk_share_obj __iomem *send_buf; 9563c13d61SErin Lo struct scp_run run; 9663c13d61SErin Lo /* To prevent multiple ipi_send run concurrently. */ 9763c13d61SErin Lo struct mutex send_lock; 9863c13d61SErin Lo struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; 9963c13d61SErin Lo bool ipi_id_ack[SCP_IPI_MAX]; 10063c13d61SErin Lo wait_queue_head_t ack_wq; 10163c13d61SErin Lo 102903635cbSTzung-Bi Shih void *cpu_addr; 103c2781e4dSArnd Bergmann dma_addr_t dma_addr; 10463c13d61SErin Lo size_t dram_size; 10570179969SPi-Hsun Shih 10670179969SPi-Hsun Shih struct rproc_subdev *rpmsg_subdev; 10763c13d61SErin Lo }; 10863c13d61SErin Lo 10963c13d61SErin Lo /** 11063c13d61SErin Lo * struct mtk_share_obj - SRAM buffer shared with AP and SCP 11163c13d61SErin Lo * 11263c13d61SErin Lo * @id: IPI id 11363c13d61SErin Lo * @len: share buffer length 11463c13d61SErin Lo * @share_buf: share buffer data 11563c13d61SErin Lo */ 11663c13d61SErin Lo struct mtk_share_obj { 11763c13d61SErin Lo u32 id; 11863c13d61SErin Lo u32 len; 11963c13d61SErin Lo u8 share_buf[SCP_SHARE_BUFFER_SIZE]; 12063c13d61SErin Lo }; 12163c13d61SErin Lo 12263c13d61SErin Lo void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); 12363c13d61SErin Lo void scp_ipi_lock(struct mtk_scp *scp, u32 id); 12463c13d61SErin Lo void scp_ipi_unlock(struct mtk_scp *scp, u32 id); 12563c13d61SErin Lo 12663c13d61SErin Lo #endif 127