1*ebcd5d51SShengjiu Wang /* SPDX-License-Identifier: GPL-2.0-only */ 2*ebcd5d51SShengjiu Wang /* 3*ebcd5d51SShengjiu Wang * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 4*ebcd5d51SShengjiu Wang * Copyright 2021 NXP 5*ebcd5d51SShengjiu Wang */ 6*ebcd5d51SShengjiu Wang 7*ebcd5d51SShengjiu Wang #ifndef _IMX_RPROC_H 8*ebcd5d51SShengjiu Wang #define _IMX_RPROC_H 9*ebcd5d51SShengjiu Wang 10*ebcd5d51SShengjiu Wang /* address translation table */ 11*ebcd5d51SShengjiu Wang struct imx_rproc_att { 12*ebcd5d51SShengjiu Wang u32 da; /* device address (From Cortex M4 view)*/ 13*ebcd5d51SShengjiu Wang u32 sa; /* system bus address */ 14*ebcd5d51SShengjiu Wang u32 size; /* size of reg range */ 15*ebcd5d51SShengjiu Wang int flags; 16*ebcd5d51SShengjiu Wang }; 17*ebcd5d51SShengjiu Wang 18*ebcd5d51SShengjiu Wang /* Remote core start/stop method */ 19*ebcd5d51SShengjiu Wang enum imx_rproc_method { 20*ebcd5d51SShengjiu Wang IMX_RPROC_NONE, 21*ebcd5d51SShengjiu Wang /* Through syscon regmap */ 22*ebcd5d51SShengjiu Wang IMX_RPROC_MMIO, 23*ebcd5d51SShengjiu Wang /* Through ARM SMCCC */ 24*ebcd5d51SShengjiu Wang IMX_RPROC_SMC, 25*ebcd5d51SShengjiu Wang }; 26*ebcd5d51SShengjiu Wang 27*ebcd5d51SShengjiu Wang struct imx_rproc_dcfg { 28*ebcd5d51SShengjiu Wang u32 src_reg; 29*ebcd5d51SShengjiu Wang u32 src_mask; 30*ebcd5d51SShengjiu Wang u32 src_start; 31*ebcd5d51SShengjiu Wang u32 src_stop; 32*ebcd5d51SShengjiu Wang const struct imx_rproc_att *att; 33*ebcd5d51SShengjiu Wang size_t att_size; 34*ebcd5d51SShengjiu Wang enum imx_rproc_method method; 35*ebcd5d51SShengjiu Wang }; 36*ebcd5d51SShengjiu Wang 37*ebcd5d51SShengjiu Wang #endif /* _IMX_RPROC_H */ 38