1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright 2021 NXP */ 3 4 #include <dt-bindings/firmware/imx/rsrc.h> 5 #include <linux/arm-smccc.h> 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/firmware.h> 9 #include <linux/firmware/imx/sci.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/mailbox_client.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_domain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/remoteproc.h> 23 #include <linux/slab.h> 24 25 #include "imx_rproc.h" 26 #include "remoteproc_elf_helpers.h" 27 #include "remoteproc_internal.h" 28 29 #define DSP_RPROC_CLK_MAX 5 30 31 #define REMOTE_IS_READY BIT(0) 32 #define REMOTE_READY_WAIT_MAX_RETRIES 500 33 34 /* att flags */ 35 /* DSP own area */ 36 #define ATT_OWN BIT(31) 37 /* DSP instruction area */ 38 #define ATT_IRAM BIT(30) 39 40 /* Definitions for i.MX8MP */ 41 /* DAP registers */ 42 #define IMX8M_DAP_DEBUG 0x28800000 43 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024) 44 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) 45 #define IMX8M_PWRCTL_CORERESET BIT(16) 46 47 /* DSP audio mix registers */ 48 #define IMX8M_AudioDSP_REG0 0x100 49 #define IMX8M_AudioDSP_REG1 0x104 50 #define IMX8M_AudioDSP_REG2 0x108 51 #define IMX8M_AudioDSP_REG3 0x10c 52 53 #define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5) 54 #define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1) 55 56 /* Definitions for i.MX8ULP */ 57 #define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8 58 #define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25) 59 #define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19) 60 #define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18) 61 #define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17) 62 #define IMX8ULP_SYSCTRL0_DSP_RST BIT(16) 63 #define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14) 64 #define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13) 65 66 #define IMX8ULP_SIP_HIFI_XRDC 0xc200000e 67 68 /* 69 * enum - Predefined Mailbox Messages 70 * 71 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor 72 * 73 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a 74 * suspend request 75 * 76 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor 77 * 78 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a 79 * resume request 80 */ 81 enum imx_dsp_rp_mbox_messages { 82 RP_MBOX_SUSPEND_SYSTEM = 0xFF11, 83 RP_MBOX_SUSPEND_ACK = 0xFF12, 84 RP_MBOX_RESUME_SYSTEM = 0xFF13, 85 RP_MBOX_RESUME_ACK = 0xFF14, 86 }; 87 88 /** 89 * struct imx_dsp_rproc - DSP remote processor state 90 * @regmap: regmap handler 91 * @rproc: rproc handler 92 * @dsp_dcfg: device configuration pointer 93 * @clks: clocks needed by this device 94 * @cl: mailbox client to request the mailbox channel 95 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell 96 * @tx_ch: mailbox tx channel handle 97 * @rx_ch: mailbox rx channel handle 98 * @rxdb_ch: mailbox rx doorbell channel handle 99 * @pd_dev: power domain device 100 * @pd_dev_link: power domain device link 101 * @ipc_handle: System Control Unit ipc handle 102 * @rproc_work: work for processing virtio interrupts 103 * @pm_comp: completion primitive to sync for suspend response 104 * @num_domains: power domain number 105 * @flags: control flags 106 */ 107 struct imx_dsp_rproc { 108 struct regmap *regmap; 109 struct rproc *rproc; 110 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 111 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX]; 112 struct mbox_client cl; 113 struct mbox_client cl_rxdb; 114 struct mbox_chan *tx_ch; 115 struct mbox_chan *rx_ch; 116 struct mbox_chan *rxdb_ch; 117 struct device **pd_dev; 118 struct device_link **pd_dev_link; 119 struct imx_sc_ipc *ipc_handle; 120 struct work_struct rproc_work; 121 struct completion pm_comp; 122 int num_domains; 123 u32 flags; 124 }; 125 126 /** 127 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration 128 * @dcfg: imx_rproc_dcfg handler 129 * @reset: reset callback function 130 */ 131 struct imx_dsp_rproc_dcfg { 132 const struct imx_rproc_dcfg *dcfg; 133 int (*reset)(struct imx_dsp_rproc *priv); 134 }; 135 136 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = { 137 /* dev addr , sys addr , size , flags */ 138 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN }, 139 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN }, 140 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 141 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN }, 142 /* DDR (Data) */ 143 { 0x80000000, 0x80000000, 0x60000000, 0}, 144 }; 145 146 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = { 147 /* dev addr , sys addr , size , flags */ 148 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN }, 149 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN }, 150 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 151 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN }, 152 /* DDR (Data) */ 153 { 0x80000000, 0x80000000, 0x60000000, 0}, 154 }; 155 156 static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = { 157 /* dev addr , sys addr , size , flags */ 158 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN }, 159 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN }, 160 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 161 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN }, 162 /* DDR (Data) */ 163 { 0x40000000, 0x40000000, 0x80000000, 0}, 164 }; 165 166 static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = { 167 /* dev addr , sys addr , size , flags */ 168 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM}, 169 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN }, 170 /* DDR (Data) */ 171 { 0x0c000000, 0x80000000, 0x10000000, 0}, 172 { 0x30000000, 0x90000000, 0x10000000, 0}, 173 }; 174 175 /* Reset function for DSP on i.MX8MP */ 176 static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv) 177 { 178 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); 179 int pwrctl; 180 181 /* Put DSP into reset and stall */ 182 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 183 pwrctl |= IMX8M_PWRCTL_CORERESET; 184 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 185 186 /* Keep reset asserted for 10 cycles */ 187 usleep_range(1, 2); 188 189 regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2, 190 IMX8M_AudioDSP_REG2_RUNSTALL, 191 IMX8M_AudioDSP_REG2_RUNSTALL); 192 193 /* Take the DSP out of reset and keep stalled for FW loading */ 194 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 195 pwrctl &= ~IMX8M_PWRCTL_CORERESET; 196 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 197 198 iounmap(dap); 199 return 0; 200 } 201 202 /* Reset function for DSP on i.MX8ULP */ 203 static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv) 204 { 205 struct arm_smccc_res res; 206 207 /* Put DSP into reset and stall */ 208 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 209 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST); 210 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 211 IMX8ULP_SYSCTRL0_DSP_STALL, 212 IMX8ULP_SYSCTRL0_DSP_STALL); 213 214 /* Configure resources of DSP through TFA */ 215 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res); 216 217 /* Take the DSP out of reset and keep stalled for FW loading */ 218 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 219 IMX8ULP_SYSCTRL0_DSP_RST, 0); 220 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 221 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0); 222 223 return 0; 224 } 225 226 /* Specific configuration for i.MX8MP */ 227 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = { 228 .src_reg = IMX8M_AudioDSP_REG2, 229 .src_mask = IMX8M_AudioDSP_REG2_RUNSTALL, 230 .src_start = 0, 231 .src_stop = IMX8M_AudioDSP_REG2_RUNSTALL, 232 .att = imx_dsp_rproc_att_imx8mp, 233 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp), 234 .method = IMX_RPROC_MMIO, 235 }; 236 237 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = { 238 .dcfg = &dsp_rproc_cfg_imx8mp, 239 .reset = imx8mp_dsp_reset, 240 }; 241 242 /* Specific configuration for i.MX8ULP */ 243 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = { 244 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 245 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL, 246 .src_start = 0, 247 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL, 248 .att = imx_dsp_rproc_att_imx8ulp, 249 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp), 250 .method = IMX_RPROC_MMIO, 251 }; 252 253 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = { 254 .dcfg = &dsp_rproc_cfg_imx8ulp, 255 .reset = imx8ulp_dsp_reset, 256 }; 257 258 /* Specific configuration for i.MX8QXP */ 259 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = { 260 .att = imx_dsp_rproc_att_imx8qxp, 261 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp), 262 .method = IMX_RPROC_SCU_API, 263 }; 264 265 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = { 266 .dcfg = &dsp_rproc_cfg_imx8qxp, 267 }; 268 269 /* Specific configuration for i.MX8QM */ 270 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = { 271 .att = imx_dsp_rproc_att_imx8qm, 272 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm), 273 .method = IMX_RPROC_SCU_API, 274 }; 275 276 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = { 277 .dcfg = &dsp_rproc_cfg_imx8qm, 278 }; 279 280 static int imx_dsp_rproc_ready(struct rproc *rproc) 281 { 282 struct imx_dsp_rproc *priv = rproc->priv; 283 int i; 284 285 if (!priv->rxdb_ch) 286 return 0; 287 288 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) { 289 if (priv->flags & REMOTE_IS_READY) 290 return 0; 291 usleep_range(100, 200); 292 } 293 294 return -ETIMEDOUT; 295 } 296 297 /* 298 * Start function for rproc_ops 299 * 300 * There is a handshake for start procedure: when DSP starts, it 301 * will send a doorbell message to this driver, then the 302 * REMOTE_IS_READY flags is set, then driver will kick 303 * a message to DSP. 304 */ 305 static int imx_dsp_rproc_start(struct rproc *rproc) 306 { 307 struct imx_dsp_rproc *priv = rproc->priv; 308 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 309 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 310 struct device *dev = rproc->dev.parent; 311 int ret; 312 313 switch (dcfg->method) { 314 case IMX_RPROC_MMIO: 315 ret = regmap_update_bits(priv->regmap, 316 dcfg->src_reg, 317 dcfg->src_mask, 318 dcfg->src_start); 319 break; 320 case IMX_RPROC_SCU_API: 321 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 322 IMX_SC_R_DSP, 323 true, 324 rproc->bootaddr); 325 break; 326 default: 327 return -EOPNOTSUPP; 328 } 329 330 if (ret) 331 dev_err(dev, "Failed to enable remote core!\n"); 332 else 333 ret = imx_dsp_rproc_ready(rproc); 334 335 return ret; 336 } 337 338 /* 339 * Stop function for rproc_ops 340 * It clears the REMOTE_IS_READY flags 341 */ 342 static int imx_dsp_rproc_stop(struct rproc *rproc) 343 { 344 struct imx_dsp_rproc *priv = rproc->priv; 345 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 346 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 347 struct device *dev = rproc->dev.parent; 348 int ret = 0; 349 350 if (rproc->state == RPROC_CRASHED) { 351 priv->flags &= ~REMOTE_IS_READY; 352 return 0; 353 } 354 355 switch (dcfg->method) { 356 case IMX_RPROC_MMIO: 357 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, 358 dcfg->src_stop); 359 break; 360 case IMX_RPROC_SCU_API: 361 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 362 IMX_SC_R_DSP, 363 false, 364 rproc->bootaddr); 365 break; 366 default: 367 return -EOPNOTSUPP; 368 } 369 370 if (ret) 371 dev_err(dev, "Failed to stop remote core\n"); 372 else 373 priv->flags &= ~REMOTE_IS_READY; 374 375 return ret; 376 } 377 378 /** 379 * imx_dsp_rproc_sys_to_da() - internal memory translation helper 380 * @priv: private data pointer 381 * @sys: system address (DDR address) 382 * @len: length of the memory buffer 383 * @da: device address to translate 384 * 385 * Convert system address (DDR address) to device address (DSP) 386 * for there may be memory remap for device. 387 */ 388 static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys, 389 size_t len, u64 *da) 390 { 391 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 392 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 393 int i; 394 395 /* Parse address translation table */ 396 for (i = 0; i < dcfg->att_size; i++) { 397 const struct imx_rproc_att *att = &dcfg->att[i]; 398 399 if (sys >= att->sa && sys + len <= att->sa + att->size) { 400 unsigned int offset = sys - att->sa; 401 402 *da = att->da + offset; 403 return 0; 404 } 405 } 406 407 return -ENOENT; 408 } 409 410 /* Main virtqueue message work function 411 * 412 * This function is executed upon scheduling of the i.MX DSP remoteproc 413 * driver's workqueue. The workqueue is scheduled by the mailbox rx 414 * handler. 415 * 416 * This work function processes both the Tx and Rx virtqueue indices on 417 * every invocation. The rproc_vq_interrupt function can detect if there 418 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED), 419 * but there is no need to check for these return values. The index 0 420 * triggering will process all pending Rx buffers, and the index 1 triggering 421 * will process all newly available Tx buffers and will wakeup any potentially 422 * blocked senders. 423 * 424 * NOTE: 425 * The current logic is based on an inherent design assumption of supporting 426 * only 2 vrings, but this can be changed if needed. 427 */ 428 static void imx_dsp_rproc_vq_work(struct work_struct *work) 429 { 430 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc, 431 rproc_work); 432 struct rproc *rproc = priv->rproc; 433 434 mutex_lock(&rproc->lock); 435 436 if (rproc->state != RPROC_RUNNING) 437 goto unlock_mutex; 438 439 rproc_vq_interrupt(priv->rproc, 0); 440 rproc_vq_interrupt(priv->rproc, 1); 441 442 unlock_mutex: 443 mutex_unlock(&rproc->lock); 444 } 445 446 /** 447 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler 448 * @cl: mailbox client pointer used for requesting the mailbox channel 449 * @data: mailbox payload 450 * 451 * This handler is invoked by mailbox driver whenever a mailbox 452 * message is received. Usually, the SUSPEND and RESUME related messages 453 * are handled in this function, other messages are handled by remoteproc core 454 */ 455 static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data) 456 { 457 struct rproc *rproc = dev_get_drvdata(cl->dev); 458 struct imx_dsp_rproc *priv = rproc->priv; 459 struct device *dev = rproc->dev.parent; 460 u32 message = (u32)(*(u32 *)data); 461 462 dev_dbg(dev, "mbox msg: 0x%x\n", message); 463 464 switch (message) { 465 case RP_MBOX_SUSPEND_ACK: 466 complete(&priv->pm_comp); 467 break; 468 case RP_MBOX_RESUME_ACK: 469 complete(&priv->pm_comp); 470 break; 471 default: 472 schedule_work(&priv->rproc_work); 473 break; 474 } 475 } 476 477 /** 478 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler 479 * @cl: mailbox client pointer used for requesting the mailbox channel 480 * @data: mailbox payload 481 * 482 * For doorbell, there is no message specified, just set REMOTE_IS_READY 483 * flag. 484 */ 485 static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data) 486 { 487 struct rproc *rproc = dev_get_drvdata(cl->dev); 488 struct imx_dsp_rproc *priv = rproc->priv; 489 490 /* Remote is ready after firmware is loaded and running */ 491 priv->flags |= REMOTE_IS_READY; 492 } 493 494 /** 495 * imx_dsp_rproc_mbox_init() - request mailbox channels 496 * @priv: private data pointer 497 * 498 * Request three mailbox channels (tx, rx, rxdb). 499 */ 500 static int imx_dsp_rproc_mbox_init(struct imx_dsp_rproc *priv) 501 { 502 struct device *dev = priv->rproc->dev.parent; 503 struct mbox_client *cl; 504 int ret; 505 506 if (!of_get_property(dev->of_node, "mbox-names", NULL)) 507 return 0; 508 509 cl = &priv->cl; 510 cl->dev = dev; 511 cl->tx_block = true; 512 cl->tx_tout = 100; 513 cl->knows_txdone = false; 514 cl->rx_callback = imx_dsp_rproc_rx_tx_callback; 515 516 /* Channel for sending message */ 517 priv->tx_ch = mbox_request_channel_byname(cl, "tx"); 518 if (IS_ERR(priv->tx_ch)) { 519 ret = PTR_ERR(priv->tx_ch); 520 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n", 521 ret); 522 goto err_out; 523 } 524 525 /* Channel for receiving message */ 526 priv->rx_ch = mbox_request_channel_byname(cl, "rx"); 527 if (IS_ERR(priv->rx_ch)) { 528 ret = PTR_ERR(priv->rx_ch); 529 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n", 530 ret); 531 goto err_out; 532 } 533 534 cl = &priv->cl_rxdb; 535 cl->dev = dev; 536 cl->rx_callback = imx_dsp_rproc_rxdb_callback; 537 538 /* 539 * RX door bell is used to receive the ready signal from remote 540 * after firmware loaded. 541 */ 542 priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb"); 543 if (IS_ERR(priv->rxdb_ch)) { 544 ret = PTR_ERR(priv->rxdb_ch); 545 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n", 546 ret); 547 goto err_out; 548 } 549 550 return 0; 551 552 err_out: 553 if (!IS_ERR(priv->tx_ch)) 554 mbox_free_channel(priv->tx_ch); 555 if (!IS_ERR(priv->rx_ch)) 556 mbox_free_channel(priv->rx_ch); 557 if (!IS_ERR(priv->rxdb_ch)) 558 mbox_free_channel(priv->rxdb_ch); 559 560 return ret; 561 } 562 563 static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv) 564 { 565 mbox_free_channel(priv->tx_ch); 566 mbox_free_channel(priv->rx_ch); 567 mbox_free_channel(priv->rxdb_ch); 568 } 569 570 /** 571 * imx_dsp_rproc_add_carveout() - request mailbox channels 572 * @priv: private data pointer 573 * 574 * This function registers specified memory entry in @rproc carveouts list 575 * The carveouts can help to mapping the memory address for DSP. 576 */ 577 static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv) 578 { 579 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 580 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 581 struct rproc *rproc = priv->rproc; 582 struct device *dev = rproc->dev.parent; 583 struct device_node *np = dev->of_node; 584 struct of_phandle_iterator it; 585 struct rproc_mem_entry *mem; 586 struct reserved_mem *rmem; 587 void __iomem *cpu_addr; 588 int a; 589 u64 da; 590 591 /* Remap required addresses */ 592 for (a = 0; a < dcfg->att_size; a++) { 593 const struct imx_rproc_att *att = &dcfg->att[a]; 594 595 if (!(att->flags & ATT_OWN)) 596 continue; 597 598 if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da)) 599 return -EINVAL; 600 601 cpu_addr = devm_ioremap_wc(dev, att->sa, att->size); 602 if (!cpu_addr) { 603 dev_err(dev, "failed to map memory %p\n", &att->sa); 604 return -ENOMEM; 605 } 606 607 /* Register memory region */ 608 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)att->sa, 609 att->size, da, NULL, NULL, "dsp_mem"); 610 611 if (mem) 612 rproc_coredump_add_segment(rproc, da, att->size); 613 else 614 return -ENOMEM; 615 616 rproc_add_carveout(rproc, mem); 617 } 618 619 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); 620 while (of_phandle_iterator_next(&it) == 0) { 621 /* 622 * Ignore the first memory region which will be used vdev buffer. 623 * No need to do extra handlings, rproc_add_virtio_dev will handle it. 624 */ 625 if (!strcmp(it.node->name, "vdev0buffer")) 626 continue; 627 628 rmem = of_reserved_mem_lookup(it.node); 629 if (!rmem) { 630 dev_err(dev, "unable to acquire memory-region\n"); 631 return -EINVAL; 632 } 633 634 if (imx_dsp_rproc_sys_to_da(priv, rmem->base, rmem->size, &da)) 635 return -EINVAL; 636 637 cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size); 638 if (!cpu_addr) { 639 dev_err(dev, "failed to map memory %p\n", &rmem->base); 640 return -ENOMEM; 641 } 642 643 /* Register memory region */ 644 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)rmem->base, 645 rmem->size, da, NULL, NULL, it.node->name); 646 647 if (mem) 648 rproc_coredump_add_segment(rproc, da, rmem->size); 649 else 650 return -ENOMEM; 651 652 rproc_add_carveout(rproc, mem); 653 } 654 655 return 0; 656 } 657 658 /* Prepare function for rproc_ops */ 659 static int imx_dsp_rproc_prepare(struct rproc *rproc) 660 { 661 struct imx_dsp_rproc *priv = rproc->priv; 662 struct device *dev = rproc->dev.parent; 663 struct rproc_mem_entry *carveout; 664 int ret; 665 666 ret = imx_dsp_rproc_add_carveout(priv); 667 if (ret) { 668 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n"); 669 return ret; 670 } 671 672 pm_runtime_get_sync(dev); 673 674 /* 675 * Clear buffers after pm rumtime for internal ocram is not 676 * accessible if power and clock are not enabled. 677 */ 678 list_for_each_entry(carveout, &rproc->carveouts, node) { 679 if (carveout->va) 680 memset(carveout->va, 0, carveout->len); 681 } 682 683 return 0; 684 } 685 686 /* Unprepare function for rproc_ops */ 687 static int imx_dsp_rproc_unprepare(struct rproc *rproc) 688 { 689 pm_runtime_put_sync(rproc->dev.parent); 690 691 return 0; 692 } 693 694 /* Kick function for rproc_ops */ 695 static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid) 696 { 697 struct imx_dsp_rproc *priv = rproc->priv; 698 struct device *dev = rproc->dev.parent; 699 int err; 700 __u32 mmsg; 701 702 if (!priv->tx_ch) { 703 dev_err(dev, "No initialized mbox tx channel\n"); 704 return; 705 } 706 707 /* 708 * Send the index of the triggered virtqueue as the mu payload. 709 * Let remote processor know which virtqueue is used. 710 */ 711 mmsg = vqid; 712 713 err = mbox_send_message(priv->tx_ch, (void *)&mmsg); 714 if (err < 0) 715 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err); 716 } 717 718 static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) 719 { 720 if (rproc_elf_load_rsc_table(rproc, fw)) 721 dev_warn(&rproc->dev, "no resource table found for this firmware\n"); 722 723 return 0; 724 } 725 726 static const struct rproc_ops imx_dsp_rproc_ops = { 727 .prepare = imx_dsp_rproc_prepare, 728 .unprepare = imx_dsp_rproc_unprepare, 729 .start = imx_dsp_rproc_start, 730 .stop = imx_dsp_rproc_stop, 731 .kick = imx_dsp_rproc_kick, 732 .load = rproc_elf_load_segments, 733 .parse_fw = imx_dsp_rproc_parse_fw, 734 .sanity_check = rproc_elf_sanity_check, 735 .get_boot_addr = rproc_elf_get_boot_addr, 736 }; 737 738 /** 739 * imx_dsp_attach_pm_domains() - attach the power domains 740 * @priv: private data pointer 741 * 742 * On i.MX8QM and i.MX8QXP there is multiple power domains 743 * required, so need to link them. 744 */ 745 static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv) 746 { 747 struct device *dev = priv->rproc->dev.parent; 748 int ret, i; 749 750 priv->num_domains = of_count_phandle_with_args(dev->of_node, 751 "power-domains", 752 "#power-domain-cells"); 753 754 /* If only one domain, then no need to link the device */ 755 if (priv->num_domains <= 1) 756 return 0; 757 758 priv->pd_dev = devm_kmalloc_array(dev, priv->num_domains, 759 sizeof(*priv->pd_dev), 760 GFP_KERNEL); 761 if (!priv->pd_dev) 762 return -ENOMEM; 763 764 priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_domains, 765 sizeof(*priv->pd_dev_link), 766 GFP_KERNEL); 767 if (!priv->pd_dev_link) 768 return -ENOMEM; 769 770 for (i = 0; i < priv->num_domains; i++) { 771 priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); 772 if (IS_ERR(priv->pd_dev[i])) { 773 ret = PTR_ERR(priv->pd_dev[i]); 774 goto detach_pm; 775 } 776 777 /* 778 * device_link_add will check priv->pd_dev[i], if it is 779 * NULL, then will break. 780 */ 781 priv->pd_dev_link[i] = device_link_add(dev, 782 priv->pd_dev[i], 783 DL_FLAG_STATELESS | 784 DL_FLAG_PM_RUNTIME); 785 if (!priv->pd_dev_link[i]) { 786 dev_pm_domain_detach(priv->pd_dev[i], false); 787 ret = -EINVAL; 788 goto detach_pm; 789 } 790 } 791 792 return 0; 793 794 detach_pm: 795 while (--i >= 0) { 796 device_link_del(priv->pd_dev_link[i]); 797 dev_pm_domain_detach(priv->pd_dev[i], false); 798 } 799 800 return ret; 801 } 802 803 static int imx_dsp_detach_pm_domains(struct imx_dsp_rproc *priv) 804 { 805 int i; 806 807 if (priv->num_domains <= 1) 808 return 0; 809 810 for (i = 0; i < priv->num_domains; i++) { 811 device_link_del(priv->pd_dev_link[i]); 812 dev_pm_domain_detach(priv->pd_dev[i], false); 813 } 814 815 return 0; 816 } 817 818 /** 819 * imx_dsp_rproc_detect_mode() - detect DSP control mode 820 * @priv: private data pointer 821 * 822 * Different platform has different control method for DSP, which depends 823 * on how the DSP is integrated in platform. 824 * 825 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System 826 * Control Unit. 827 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system 828 * integration module. 829 */ 830 static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv) 831 { 832 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 833 struct device *dev = priv->rproc->dev.parent; 834 struct regmap *regmap; 835 int ret = 0; 836 837 switch (dsp_dcfg->dcfg->method) { 838 case IMX_RPROC_SCU_API: 839 ret = imx_scu_get_handle(&priv->ipc_handle); 840 if (ret) 841 return ret; 842 break; 843 case IMX_RPROC_MMIO: 844 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl"); 845 if (IS_ERR(regmap)) { 846 dev_err(dev, "failed to find syscon\n"); 847 return PTR_ERR(regmap); 848 } 849 850 priv->regmap = regmap; 851 break; 852 default: 853 ret = -EOPNOTSUPP; 854 break; 855 } 856 857 return ret; 858 } 859 860 static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = { 861 /* DSP clocks */ 862 "core", "ocram", "debug", "ipg", "mu", 863 }; 864 865 static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv) 866 { 867 struct device *dev = priv->rproc->dev.parent; 868 struct clk_bulk_data *clks = priv->clks; 869 int i; 870 871 for (i = 0; i < DSP_RPROC_CLK_MAX; i++) 872 clks[i].id = imx_dsp_clks_names[i]; 873 874 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks); 875 } 876 877 static int imx_dsp_rproc_probe(struct platform_device *pdev) 878 { 879 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 880 struct device *dev = &pdev->dev; 881 struct imx_dsp_rproc *priv; 882 struct rproc *rproc; 883 const char *fw_name; 884 int ret; 885 886 dsp_dcfg = of_device_get_match_data(dev); 887 if (!dsp_dcfg) 888 return -ENODEV; 889 890 ret = rproc_of_parse_firmware(dev, 0, &fw_name); 891 if (ret) { 892 dev_err(dev, "failed to parse firmware-name property, ret = %d\n", 893 ret); 894 return ret; 895 } 896 897 rproc = rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops, fw_name, 898 sizeof(*priv)); 899 if (!rproc) 900 return -ENOMEM; 901 902 priv = rproc->priv; 903 priv->rproc = rproc; 904 priv->dsp_dcfg = dsp_dcfg; 905 906 dev_set_drvdata(dev, rproc); 907 908 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work); 909 910 ret = imx_dsp_rproc_detect_mode(priv); 911 if (ret) { 912 dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n"); 913 goto err_put_rproc; 914 } 915 916 /* There are multiple power domains required by DSP on some platform */ 917 ret = imx_dsp_attach_pm_domains(priv); 918 if (ret) { 919 dev_err(dev, "failed on imx_dsp_attach_pm_domains\n"); 920 goto err_put_rproc; 921 } 922 /* Get clocks */ 923 ret = imx_dsp_rproc_clk_get(priv); 924 if (ret) { 925 dev_err(dev, "failed on imx_dsp_rproc_clk_get\n"); 926 goto err_detach_domains; 927 } 928 929 init_completion(&priv->pm_comp); 930 rproc->auto_boot = false; 931 ret = rproc_add(rproc); 932 if (ret) { 933 dev_err(dev, "rproc_add failed\n"); 934 goto err_detach_domains; 935 } 936 937 pm_runtime_enable(dev); 938 939 return 0; 940 941 err_detach_domains: 942 imx_dsp_detach_pm_domains(priv); 943 err_put_rproc: 944 rproc_free(rproc); 945 946 return ret; 947 } 948 949 static int imx_dsp_rproc_remove(struct platform_device *pdev) 950 { 951 struct rproc *rproc = platform_get_drvdata(pdev); 952 struct imx_dsp_rproc *priv = rproc->priv; 953 954 pm_runtime_disable(&pdev->dev); 955 rproc_del(rproc); 956 imx_dsp_detach_pm_domains(priv); 957 rproc_free(rproc); 958 959 return 0; 960 } 961 962 /* pm runtime functions */ 963 static int imx_dsp_runtime_resume(struct device *dev) 964 { 965 struct rproc *rproc = dev_get_drvdata(dev); 966 struct imx_dsp_rproc *priv = rproc->priv; 967 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 968 int ret; 969 970 /* 971 * There is power domain attached with mailbox, if setup mailbox 972 * in probe(), then the power of mailbox is always enabled, 973 * the power can't be saved. 974 * So move setup of mailbox to runtime resume. 975 */ 976 ret = imx_dsp_rproc_mbox_init(priv); 977 if (ret) { 978 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n"); 979 return ret; 980 } 981 982 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks); 983 if (ret) { 984 dev_err(dev, "failed on clk_bulk_prepare_enable\n"); 985 return ret; 986 } 987 988 /* Reset DSP if needed */ 989 if (dsp_dcfg->reset) 990 dsp_dcfg->reset(priv); 991 992 return 0; 993 } 994 995 static int imx_dsp_runtime_suspend(struct device *dev) 996 { 997 struct rproc *rproc = dev_get_drvdata(dev); 998 struct imx_dsp_rproc *priv = rproc->priv; 999 1000 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks); 1001 1002 imx_dsp_rproc_free_mbox(priv); 1003 1004 return 0; 1005 } 1006 1007 static void imx_dsp_load_firmware(const struct firmware *fw, void *context) 1008 { 1009 struct rproc *rproc = context; 1010 int ret; 1011 1012 /* 1013 * Same flow as start procedure. 1014 * Load the ELF segments to memory firstly. 1015 */ 1016 ret = rproc_load_segments(rproc, fw); 1017 if (ret) 1018 goto out; 1019 1020 /* Start the remote processor */ 1021 ret = rproc->ops->start(rproc); 1022 if (ret) 1023 goto out; 1024 1025 rproc->ops->kick(rproc, 0); 1026 1027 out: 1028 release_firmware(fw); 1029 } 1030 1031 static __maybe_unused int imx_dsp_suspend(struct device *dev) 1032 { 1033 struct rproc *rproc = dev_get_drvdata(dev); 1034 struct imx_dsp_rproc *priv = rproc->priv; 1035 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM; 1036 int ret; 1037 1038 if (rproc->state != RPROC_RUNNING) 1039 goto out; 1040 1041 reinit_completion(&priv->pm_comp); 1042 1043 /* Tell DSP that suspend is happening */ 1044 ret = mbox_send_message(priv->tx_ch, (void *)&mmsg); 1045 if (ret < 0) { 1046 dev_err(dev, "PM mbox_send_message failed: %d\n", ret); 1047 return ret; 1048 } 1049 1050 /* 1051 * DSP need to save the context at suspend. 1052 * Here waiting the response for DSP, then power can be disabled. 1053 */ 1054 if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100))) 1055 return -EBUSY; 1056 1057 out: 1058 /* 1059 * The power of DSP is disabled in suspend, so force pm runtime 1060 * to be suspend, then we can reenable the power and clocks at 1061 * resume stage. 1062 */ 1063 return pm_runtime_force_suspend(dev); 1064 } 1065 1066 static __maybe_unused int imx_dsp_resume(struct device *dev) 1067 { 1068 struct rproc *rproc = dev_get_drvdata(dev); 1069 int ret = 0; 1070 1071 ret = pm_runtime_force_resume(dev); 1072 if (ret) 1073 return ret; 1074 1075 if (rproc->state != RPROC_RUNNING) 1076 return 0; 1077 1078 /* 1079 * The power of DSP is disabled at suspend, the memory of dsp 1080 * is reset, the image segments are lost. So need to reload 1081 * firmware and restart the DSP if it is in running state. 1082 */ 1083 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 1084 rproc->firmware, dev, GFP_KERNEL, 1085 rproc, imx_dsp_load_firmware); 1086 if (ret < 0) { 1087 dev_err(dev, "load firmware failed: %d\n", ret); 1088 goto err; 1089 } 1090 1091 return 0; 1092 1093 err: 1094 pm_runtime_force_suspend(dev); 1095 1096 return ret; 1097 } 1098 1099 static const struct dev_pm_ops imx_dsp_rproc_pm_ops = { 1100 SET_SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume) 1101 SET_RUNTIME_PM_OPS(imx_dsp_runtime_suspend, 1102 imx_dsp_runtime_resume, NULL) 1103 }; 1104 1105 static const struct of_device_id imx_dsp_rproc_of_match[] = { 1106 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp }, 1107 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm }, 1108 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp }, 1109 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp }, 1110 {}, 1111 }; 1112 MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match); 1113 1114 static struct platform_driver imx_dsp_rproc_driver = { 1115 .probe = imx_dsp_rproc_probe, 1116 .remove = imx_dsp_rproc_remove, 1117 .driver = { 1118 .name = "imx-dsp-rproc", 1119 .of_match_table = imx_dsp_rproc_of_match, 1120 .pm = &imx_dsp_rproc_pm_ops, 1121 }, 1122 }; 1123 module_platform_driver(imx_dsp_rproc_driver); 1124 1125 MODULE_LICENSE("GPL v2"); 1126 MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver"); 1127 MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>"); 1128