1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * SLG51000 High PSRR, Multi-Output Regulators 4 * Copyright (C) 2019 Dialog Semiconductor 5 * 6 * Author: Eric Jeong <eric.jeong.opensource@diasemi.com> 7 */ 8 9 #ifndef __SLG51000_REGISTERS_H__ 10 #define __SLG51000_REGISTERS_H__ 11 12 /* Registers */ 13 14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105 15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106 16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107 17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109 18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c 19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d 20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e 21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111 22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112 23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115 24 #define SLG51000_SYSCTL_EVENT 0x1116 25 #define SLG51000_SYSCTL_STATUS 0x1117 26 #define SLG51000_SYSCTL_IRQ_MASK 0x1118 27 #define SLG51000_IO_GPIO1_CONF 0x1500 28 #define SLG51000_IO_GPIO2_CONF 0x1501 29 #define SLG51000_IO_GPIO3_CONF 0x1502 30 #define SLG51000_IO_GPIO4_CONF 0x1503 31 #define SLG51000_IO_GPIO5_CONF 0x1504 32 #define SLG51000_IO_GPIO6_CONF 0x1505 33 #define SLG51000_IO_GPIO_STATUS 0x1506 34 #define SLG51000_LUTARRAY_LUT_VAL_0 0x1600 35 #define SLG51000_LUTARRAY_LUT_VAL_1 0x1601 36 #define SLG51000_LUTARRAY_LUT_VAL_2 0x1602 37 #define SLG51000_LUTARRAY_LUT_VAL_3 0x1603 38 #define SLG51000_LUTARRAY_LUT_VAL_4 0x1604 39 #define SLG51000_LUTARRAY_LUT_VAL_5 0x1605 40 #define SLG51000_LUTARRAY_LUT_VAL_6 0x1606 41 #define SLG51000_LUTARRAY_LUT_VAL_7 0x1607 42 #define SLG51000_LUTARRAY_LUT_VAL_8 0x1608 43 #define SLG51000_LUTARRAY_LUT_VAL_9 0x1609 44 #define SLG51000_LUTARRAY_LUT_VAL_10 0x160a 45 #define SLG51000_LUTARRAY_LUT_VAL_11 0x160b 46 #define SLG51000_MUXARRAY_INPUT_SEL_0 0x1700 47 #define SLG51000_MUXARRAY_INPUT_SEL_1 0x1701 48 #define SLG51000_MUXARRAY_INPUT_SEL_2 0x1702 49 #define SLG51000_MUXARRAY_INPUT_SEL_3 0x1703 50 #define SLG51000_MUXARRAY_INPUT_SEL_4 0x1704 51 #define SLG51000_MUXARRAY_INPUT_SEL_5 0x1705 52 #define SLG51000_MUXARRAY_INPUT_SEL_6 0x1706 53 #define SLG51000_MUXARRAY_INPUT_SEL_7 0x1707 54 #define SLG51000_MUXARRAY_INPUT_SEL_8 0x1708 55 #define SLG51000_MUXARRAY_INPUT_SEL_9 0x1709 56 #define SLG51000_MUXARRAY_INPUT_SEL_10 0x170a 57 #define SLG51000_MUXARRAY_INPUT_SEL_11 0x170b 58 #define SLG51000_MUXARRAY_INPUT_SEL_12 0x170c 59 #define SLG51000_MUXARRAY_INPUT_SEL_13 0x170d 60 #define SLG51000_MUXARRAY_INPUT_SEL_14 0x170e 61 #define SLG51000_MUXARRAY_INPUT_SEL_15 0x170f 62 #define SLG51000_MUXARRAY_INPUT_SEL_16 0x1710 63 #define SLG51000_MUXARRAY_INPUT_SEL_17 0x1711 64 #define SLG51000_MUXARRAY_INPUT_SEL_18 0x1712 65 #define SLG51000_MUXARRAY_INPUT_SEL_19 0x1713 66 #define SLG51000_MUXARRAY_INPUT_SEL_20 0x1714 67 #define SLG51000_MUXARRAY_INPUT_SEL_21 0x1715 68 #define SLG51000_MUXARRAY_INPUT_SEL_22 0x1716 69 #define SLG51000_MUXARRAY_INPUT_SEL_23 0x1717 70 #define SLG51000_MUXARRAY_INPUT_SEL_24 0x1718 71 #define SLG51000_MUXARRAY_INPUT_SEL_25 0x1719 72 #define SLG51000_MUXARRAY_INPUT_SEL_26 0x171a 73 #define SLG51000_MUXARRAY_INPUT_SEL_27 0x171b 74 #define SLG51000_MUXARRAY_INPUT_SEL_28 0x171c 75 #define SLG51000_MUXARRAY_INPUT_SEL_29 0x171d 76 #define SLG51000_MUXARRAY_INPUT_SEL_30 0x171e 77 #define SLG51000_MUXARRAY_INPUT_SEL_31 0x171f 78 #define SLG51000_MUXARRAY_INPUT_SEL_32 0x1720 79 #define SLG51000_MUXARRAY_INPUT_SEL_33 0x1721 80 #define SLG51000_MUXARRAY_INPUT_SEL_34 0x1722 81 #define SLG51000_MUXARRAY_INPUT_SEL_35 0x1723 82 #define SLG51000_MUXARRAY_INPUT_SEL_36 0x1724 83 #define SLG51000_MUXARRAY_INPUT_SEL_37 0x1725 84 #define SLG51000_MUXARRAY_INPUT_SEL_38 0x1726 85 #define SLG51000_MUXARRAY_INPUT_SEL_39 0x1727 86 #define SLG51000_MUXARRAY_INPUT_SEL_40 0x1728 87 #define SLG51000_MUXARRAY_INPUT_SEL_41 0x1729 88 #define SLG51000_MUXARRAY_INPUT_SEL_42 0x172a 89 #define SLG51000_MUXARRAY_INPUT_SEL_43 0x172b 90 #define SLG51000_MUXARRAY_INPUT_SEL_44 0x172c 91 #define SLG51000_MUXARRAY_INPUT_SEL_45 0x172d 92 #define SLG51000_MUXARRAY_INPUT_SEL_46 0x172e 93 #define SLG51000_MUXARRAY_INPUT_SEL_47 0x172f 94 #define SLG51000_MUXARRAY_INPUT_SEL_48 0x1730 95 #define SLG51000_MUXARRAY_INPUT_SEL_49 0x1731 96 #define SLG51000_MUXARRAY_INPUT_SEL_50 0x1732 97 #define SLG51000_MUXARRAY_INPUT_SEL_51 0x1733 98 #define SLG51000_MUXARRAY_INPUT_SEL_52 0x1734 99 #define SLG51000_MUXARRAY_INPUT_SEL_53 0x1735 100 #define SLG51000_MUXARRAY_INPUT_SEL_54 0x1736 101 #define SLG51000_MUXARRAY_INPUT_SEL_55 0x1737 102 #define SLG51000_MUXARRAY_INPUT_SEL_56 0x1738 103 #define SLG51000_MUXARRAY_INPUT_SEL_57 0x1739 104 #define SLG51000_MUXARRAY_INPUT_SEL_58 0x173a 105 #define SLG51000_MUXARRAY_INPUT_SEL_59 0x173b 106 #define SLG51000_MUXARRAY_INPUT_SEL_60 0x173c 107 #define SLG51000_MUXARRAY_INPUT_SEL_61 0x173d 108 #define SLG51000_MUXARRAY_INPUT_SEL_62 0x173e 109 #define SLG51000_MUXARRAY_INPUT_SEL_63 0x173f 110 #define SLG51000_PWRSEQ_RESOURCE_EN_0 0x1900 111 #define SLG51000_PWRSEQ_RESOURCE_EN_1 0x1901 112 #define SLG51000_PWRSEQ_RESOURCE_EN_2 0x1902 113 #define SLG51000_PWRSEQ_RESOURCE_EN_3 0x1903 114 #define SLG51000_PWRSEQ_RESOURCE_EN_4 0x1904 115 #define SLG51000_PWRSEQ_RESOURCE_EN_5 0x1905 116 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906 117 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907 118 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908 119 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909 120 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a 121 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b 122 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c 123 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d 124 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e 125 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f 126 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910 127 #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911 128 #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912 129 #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913 130 #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914 131 #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_A 0x1915 132 #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_B 0x1916 133 #define SLG51000_LDO1_VSEL 0x2000 134 #define SLG51000_LDO1_MINV 0x2060 135 #define SLG51000_LDO1_MAXV 0x2061 136 #define SLG51000_LDO1_MISC1 0x2064 137 #define SLG51000_LDO1_VSEL_ACTUAL 0x2065 138 #define SLG51000_LDO1_EVENT 0x20c0 139 #define SLG51000_LDO1_STATUS 0x20c1 140 #define SLG51000_LDO1_IRQ_MASK 0x20c2 141 #define SLG51000_LDO2_VSEL 0x2200 142 #define SLG51000_LDO2_MINV 0x2260 143 #define SLG51000_LDO2_MAXV 0x2261 144 #define SLG51000_LDO2_MISC1 0x2264 145 #define SLG51000_LDO2_VSEL_ACTUAL 0x2265 146 #define SLG51000_LDO2_EVENT 0x22c0 147 #define SLG51000_LDO2_STATUS 0x22c1 148 #define SLG51000_LDO2_IRQ_MASK 0x22c2 149 #define SLG51000_LDO3_VSEL 0x2300 150 #define SLG51000_LDO3_MINV 0x2360 151 #define SLG51000_LDO3_MAXV 0x2361 152 #define SLG51000_LDO3_CONF1 0x2364 153 #define SLG51000_LDO3_CONF2 0x2365 154 #define SLG51000_LDO3_VSEL_ACTUAL 0x2366 155 #define SLG51000_LDO3_EVENT 0x23c0 156 #define SLG51000_LDO3_STATUS 0x23c1 157 #define SLG51000_LDO3_IRQ_MASK 0x23c2 158 #define SLG51000_LDO4_VSEL 0x2500 159 #define SLG51000_LDO4_MINV 0x2560 160 #define SLG51000_LDO4_MAXV 0x2561 161 #define SLG51000_LDO4_CONF1 0x2564 162 #define SLG51000_LDO4_CONF2 0x2565 163 #define SLG51000_LDO4_VSEL_ACTUAL 0x2566 164 #define SLG51000_LDO4_EVENT 0x25c0 165 #define SLG51000_LDO4_STATUS 0x25c1 166 #define SLG51000_LDO4_IRQ_MASK 0x25c2 167 #define SLG51000_LDO5_VSEL 0x2700 168 #define SLG51000_LDO5_MINV 0x2760 169 #define SLG51000_LDO5_MAXV 0x2761 170 #define SLG51000_LDO5_TRIM2 0x2763 171 #define SLG51000_LDO5_CONF1 0x2765 172 #define SLG51000_LDO5_CONF2 0x2766 173 #define SLG51000_LDO5_VSEL_ACTUAL 0x2767 174 #define SLG51000_LDO5_EVENT 0x27c0 175 #define SLG51000_LDO5_STATUS 0x27c1 176 #define SLG51000_LDO5_IRQ_MASK 0x27c2 177 #define SLG51000_LDO6_VSEL 0x2900 178 #define SLG51000_LDO6_MINV 0x2960 179 #define SLG51000_LDO6_MAXV 0x2961 180 #define SLG51000_LDO6_TRIM2 0x2963 181 #define SLG51000_LDO6_CONF1 0x2965 182 #define SLG51000_LDO6_CONF2 0x2966 183 #define SLG51000_LDO6_VSEL_ACTUAL 0x2967 184 #define SLG51000_LDO6_EVENT 0x29c0 185 #define SLG51000_LDO6_STATUS 0x29c1 186 #define SLG51000_LDO6_IRQ_MASK 0x29c2 187 #define SLG51000_LDO7_VSEL 0x3100 188 #define SLG51000_LDO7_MINV 0x3160 189 #define SLG51000_LDO7_MAXV 0x3161 190 #define SLG51000_LDO7_CONF1 0x3164 191 #define SLG51000_LDO7_CONF2 0x3165 192 #define SLG51000_LDO7_VSEL_ACTUAL 0x3166 193 #define SLG51000_LDO7_EVENT 0x31c0 194 #define SLG51000_LDO7_STATUS 0x31c1 195 #define SLG51000_LDO7_IRQ_MASK 0x31c2 196 #define SLG51000_OTP_EVENT 0x782b 197 #define SLG51000_OTP_IRQ_MASK 0x782d 198 #define SLG51000_OTP_LOCK_OTP_PROG 0x78fe 199 #define SLG51000_OTP_LOCK_CTRL 0x78ff 200 #define SLG51000_LOCK_GLOBAL_LOCK_CTRL1 0x8000 201 202 /* Register Bit Fields */ 203 204 /* SLG51000_SYSCTL_PATTERN_ID_BYTE0 = 0x1105 */ 205 #define SLG51000_PATTERN_ID_BYTE0_SHIFT 0 206 #define SLG51000_PATTERN_ID_BYTE0_MASK (0xff << 0) 207 208 /* SLG51000_SYSCTL_PATTERN_ID_BYTE1 = 0x1106 */ 209 #define SLG51000_PATTERN_ID_BYTE1_SHIFT 0 210 #define SLG51000_PATTERN_ID_BYTE1_MASK (0xff << 0) 211 212 /* SLG51000_SYSCTL_PATTERN_ID_BYTE2 = 0x1107 */ 213 #define SLG51000_PATTERN_ID_BYTE2_SHIFT 0 214 #define SLG51000_PATTERN_ID_BYTE2_MASK (0xff << 0) 215 216 /* SLG51000_SYSCTL_SYS_CONF_A = 0x1109 */ 217 #define SLG51000_I2C_ADDRESS_SHIFT 0 218 #define SLG51000_I2C_ADDRESS_MASK (0x7f << 0) 219 #define SLG51000_I2C_DISABLE_SHIFT 7 220 #define SLG51000_I2C_DISABLE_MASK (0x01 << 7) 221 222 /* SLG51000_SYSCTL_SYS_CONF_D = 0x110c */ 223 #define SLG51000_CS_T_DEB_SHIFT 6 224 #define SLG51000_CS_T_DEB_MASK (0x03 << 6) 225 #define SLG51000_I2C_CLR_MODE_SHIFT 5 226 #define SLG51000_I2C_CLR_MODE_MASK (0x01 << 5) 227 228 /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_A = 0x110d */ 229 #define SLG51000_RESOURCE_CTRL_SHIFT 0 230 #define SLG51000_RESOURCE_CTRL_MASK (0xff << 0) 231 232 /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_B = 0x110e */ 233 #define SLG51000_MATRIX_EVENT_SENSE_SHIFT 0 234 #define SLG51000_MATRIX_EVENT_SENSE_MASK (0x07 << 0) 235 236 /* SLG51000_SYSCTL_REFGEN_CONF_C = 0x1111 */ 237 #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2 238 #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2) 239 #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0 240 #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0) 241 242 /* SLG51000_SYSCTL_UVLO_CONF_A = 0x1112 */ 243 #define SLG51000_VMON_UVLO_SEL_THR_SHIFT 0 244 #define SLG51000_VMON_UVLO_SEL_THR_MASK (0x1f << 0) 245 246 /* SLG51000_SYSCTL_FAULT_LOG1 = 0x1115 */ 247 #define SLG51000_FLT_POR_SHIFT 5 248 #define SLG51000_FLT_POR_MASK (0x01 << 5) 249 #define SLG51000_FLT_RST_SHIFT 4 250 #define SLG51000_FLT_RST_MASK (0x01 << 4) 251 #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2 252 #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK (0x01 << 2) 253 #define SLG51000_FLT_OVER_TEMP_SHIFT 1 254 #define SLG51000_FLT_OVER_TEMP_MASK (0x01 << 1) 255 256 /* SLG51000_SYSCTL_EVENT = 0x1116 */ 257 #define SLG51000_EVT_MATRIX_SHIFT 1 258 #define SLG51000_EVT_MATRIX_MASK (0x01 << 1) 259 #define SLG51000_EVT_HIGH_TEMP_WARN_SHIFT 0 260 #define SLG51000_EVT_HIGH_TEMP_WARN_MASK (0x01 << 0) 261 262 /* SLG51000_SYSCTL_STATUS = 0x1117 */ 263 #define SLG51000_STA_MATRIX_SHIFT 1 264 #define SLG51000_STA_MATRIX_MASK (0x01 << 1) 265 #define SLG51000_STA_HIGH_TEMP_WARN_SHIFT 0 266 #define SLG51000_STA_HIGH_TEMP_WARN_MASK (0x01 << 0) 267 268 /* SLG51000_SYSCTL_IRQ_MASK = 0x1118 */ 269 #define SLG51000_IRQ_MATRIX_SHIFT 1 270 #define SLG51000_IRQ_MATRIX_MASK (0x01 << 1) 271 #define SLG51000_IRQ_HIGH_TEMP_WARN_SHIFT 0 272 #define SLG51000_IRQ_HIGH_TEMP_WARN_MASK (0x01 << 0) 273 274 /* SLG51000_IO_GPIO1_CONF ~ SLG51000_IO_GPIO5_CONF = 275 * 0x1500, 0x1501, 0x1502, 0x1503, 0x1504 276 */ 277 #define SLG51000_GPIO_DIR_SHIFT 7 278 #define SLG51000_GPIO_DIR_MASK (0x01 << 7) 279 #define SLG51000_GPIO_SENS_SHIFT 5 280 #define SLG51000_GPIO_SENS_MASK (0x03 << 5) 281 #define SLG51000_GPIO_INVERT_SHIFT 4 282 #define SLG51000_GPIO_INVERT_MASK (0x01 << 4) 283 #define SLG51000_GPIO_BYP_SHIFT 3 284 #define SLG51000_GPIO_BYP_MASK (0x01 << 3) 285 #define SLG51000_GPIO_T_DEB_SHIFT 1 286 #define SLG51000_GPIO_T_DEB_MASK (0x03 << 1) 287 #define SLG51000_GPIO_LEVEL_SHIFT 0 288 #define SLG51000_GPIO_LEVEL_MASK (0x01 << 0) 289 290 /* SLG51000_IO_GPIO6_CONF = 0x1505 */ 291 #define SLG51000_GPIO6_SENS_SHIFT 5 292 #define SLG51000_GPIO6_SENS_MASK (0x03 << 5) 293 #define SLG51000_GPIO6_INVERT_SHIFT 4 294 #define SLG51000_GPIO6_INVERT_MASK (0x01 << 4) 295 #define SLG51000_GPIO6_T_DEB_SHIFT 1 296 #define SLG51000_GPIO6_T_DEB_MASK (0x03 << 1) 297 #define SLG51000_GPIO6_LEVEL_SHIFT 0 298 #define SLG51000_GPIO6_LEVEL_MASK (0x01 << 0) 299 300 /* SLG51000_IO_GPIO_STATUS = 0x1506 */ 301 #define SLG51000_GPIO6_STATUS_SHIFT 5 302 #define SLG51000_GPIO6_STATUS_MASK (0x01 << 5) 303 #define SLG51000_GPIO5_STATUS_SHIFT 4 304 #define SLG51000_GPIO5_STATUS_MASK (0x01 << 4) 305 #define SLG51000_GPIO4_STATUS_SHIFT 3 306 #define SLG51000_GPIO4_STATUS_MASK (0x01 << 3) 307 #define SLG51000_GPIO3_STATUS_SHIFT 2 308 #define SLG51000_GPIO3_STATUS_MASK (0x01 << 2) 309 #define SLG51000_GPIO2_STATUS_SHIFT 1 310 #define SLG51000_GPIO2_STATUS_MASK (0x01 << 1) 311 #define SLG51000_GPIO1_STATUS_SHIFT 0 312 #define SLG51000_GPIO1_STATUS_MASK (0x01 << 0) 313 314 /* SLG51000_LUTARRAY_LUT_VAL_0 ~ SLG51000_LUTARRAY_LUT_VAL_11 315 * 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605, 316 * 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b 317 */ 318 #define SLG51000_LUT_VAL_SHIFT 0 319 #define SLG51000_LUT_VAL_MASK (0xff << 0) 320 321 /* SLG51000_MUXARRAY_INPUT_SEL_0 ~ SLG51000_MUXARRAY_INPUT_SEL_63 322 * 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705, 323 * 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b, 324 * 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711, 325 * 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717, 326 * 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d, 327 * 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723, 328 * 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729, 329 * 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f, 330 */ 331 #define SLG51000_INPUT_SEL_SHIFT 0 332 #define SLG51000_INPUT_SEL_MASK (0x3f << 0) 333 334 /* SLG51000_PWRSEQ_RESOURCE_EN_0 ~ SLG51000_PWRSEQ_RESOURCE_EN_5 335 * 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905 336 */ 337 #define SLG51000_RESOURCE_EN_DOWN0_SHIFT 4 338 #define SLG51000_RESOURCE_EN_DOWN0_MASK (0x07 << 4) 339 #define SLG51000_RESOURCE_EN_UP0_SHIFT 0 340 #define SLG51000_RESOURCE_EN_UP0_MASK (0x07 << 0) 341 342 /* SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 343 * 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910 344 */ 345 #define SLG51000_SLOT_TIME_MIN_UP_SHIFT 0 346 #define SLG51000_SLOT_TIME_MIN_UP_MASK (0xff << 0) 347 348 /* SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 349 * 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911 350 */ 351 #define SLG51000_SLOT_TIME_MIN_DOWN_SHIFT 0 352 #define SLG51000_SLOT_TIME_MIN_DOWN_MASK (0xff << 0) 353 354 /* SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 355 * 0x1912, 0x1913, 0x1914 356 */ 357 #define SLG51000_SLOT_TIME_MAX_DOWN1_SHIFT 6 358 #define SLG51000_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6) 359 #define SLG51000_SLOT_TIME_MAX_UP1_SHIFT 4 360 #define SLG51000_SLOT_TIME_MAX_UP1_MASK (0x03 << 4) 361 #define SLG51000_SLOT_TIME_MAX_DOWN0_SHIFT 2 362 #define SLG51000_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2) 363 #define SLG51000_SLOT_TIME_MAX_UP0_SHIFT 0 364 #define SLG51000_SLOT_TIME_MAX_UP0_MASK (0x03 << 0) 365 366 /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */ 367 #define SLG51000_TRIG_UP_SENSE_SHIFT 6 368 #define SLG51000_TRIG_UP_SENSE_MASK (0x01 << 6) 369 #define SLG51000_UP_EN_SENSE5_SHIFT 5 370 #define SLG51000_UP_EN_SENSE5_MASK (0x01 << 5) 371 #define SLG51000_UP_EN_SENSE4_SHIFT 4 372 #define SLG51000_UP_EN_SENSE4_MASK (0x01 << 4) 373 #define SLG51000_UP_EN_SENSE3_SHIFT 3 374 #define SLG51000_UP_EN_SENSE3_MASK (0x01 << 3) 375 #define SLG51000_UP_EN_SENSE2_SHIFT 2 376 #define SLG51000_UP_EN_SENSE2_MASK (0x01 << 2) 377 #define SLG51000_UP_EN_SENSE1_SHIFT 1 378 #define SLG51000_UP_EN_SENSE1_MASK (0x01 << 1) 379 #define SLG51000_UP_EN_SENSE0_SHIFT 0 380 #define SLG51000_UP_EN_SENSE0_MASK (0x01 << 0) 381 382 /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */ 383 #define SLG51000_CRASH_DETECT_SENSE_SHIFT 7 384 #define SLG51000_CRASH_DETECT_SENSE_MASK (0x01 << 7) 385 #define SLG51000_TRIG_DOWN_SENSE_SHIFT 6 386 #define SLG51000_TRIG_DOWN_SENSE_MASK (0x01 << 6) 387 #define SLG51000_DOWN_EN_SENSE5_SHIFT 5 388 #define SLG51000_DOWN_EN_SENSE5_MASK (0x01 << 5) 389 #define SLG51000_DOWN_EN_SENSE4_SHIFT 4 390 #define SLG51000_DOWN_EN_SENSE4_MASK (0x01 << 4) 391 #define SLG51000_DOWN_EN_SENSE3_SHIFT 3 392 #define SLG51000_DOWN_EN_SENSE3_MASK (0x01 << 3) 393 #define SLG51000_DOWN_EN_SENSE2_SHIFT 2 394 #define SLG51000_DOWN_EN_SENSE2_MASK (0x01 << 2) 395 #define SLG51000_DOWN_EN_SENSE1_SHIFT 1 396 #define SLG51000_DOWN_EN_SENSE1_MASK (0x01 << 1) 397 #define SLG51000_DOWN_EN_SENSE0_SHIFT 0 398 #define SLG51000_DOWN_EN_SENSE0_MASK (0x01 << 0) 399 400 /* SLG51000_LDO1_VSEL ~ SLG51000_LDO7_VSEL = 401 * 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100 402 */ 403 #define SLG51000_VSEL_SHIFT 0 404 #define SLG51000_VSEL_MASK (0xff << 0) 405 406 /* SLG51000_LDO1_MINV ~ SLG51000_LDO7_MINV = 407 * 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160 408 */ 409 #define SLG51000_MINV_SHIFT 0 410 #define SLG51000_MINV_MASK (0xff << 0) 411 412 /* SLG51000_LDO1_MAXV ~ SLG51000_LDO7_MAXV = 413 * 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161 414 */ 415 #define SLG51000_MAXV_SHIFT 0 416 #define SLG51000_MAXV_MASK (0xff << 0) 417 418 /* SLG51000_LDO1_MISC1 = 0x2064, SLG51000_LDO2_MISC1 = 0x2264 */ 419 #define SLG51000_SEL_VRANGE_SHIFT 0 420 #define SLG51000_SEL_VRANGE_MASK (0x01 << 0) 421 422 /* SLG51000_LDO1_VSEL_ACTUAL ~ SLG51000_LDO7_VSEL_ACTUAL = 423 * 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166 424 */ 425 #define SLG51000_VSEL_ACTUAL_SHIFT 0 426 #define SLG51000_VSEL_ACTUAL_MASK (0xff << 0) 427 428 /* SLG51000_LDO1_EVENT ~ SLG51000_LDO7_EVENT = 429 * 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0 430 */ 431 #define SLG51000_EVT_ILIM_FLAG_SHIFT 0 432 #define SLG51000_EVT_ILIM_FLAG_MASK (0x01 << 0) 433 #define SLG51000_EVT_VOUT_OK_FLAG_SHIFT 1 434 #define SLG51000_EVT_VOUT_OK_FLAG_MASK (0x01 << 1) 435 436 /* SLG51000_LDO1_STATUS ~ SLG51000_LDO7_STATUS = 437 * 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1 438 */ 439 #define SLG51000_STA_ILIM_FLAG_SHIFT 0 440 #define SLG51000_STA_ILIM_FLAG_MASK (0x01 << 0) 441 #define SLG51000_STA_VOUT_OK_FLAG_SHIFT 1 442 #define SLG51000_STA_VOUT_OK_FLAG_MASK (0x01 << 1) 443 444 /* SLG51000_LDO1_IRQ_MASK ~ SLG51000_LDO7_IRQ_MASK = 445 * 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2 446 */ 447 #define SLG51000_IRQ_ILIM_FLAG_SHIFT 0 448 #define SLG51000_IRQ_ILIM_FLAG_MASK (0x01 << 0) 449 450 /* SLG51000_LDO3_CONF1 ~ SLG51000_LDO7_CONF1 = 451 * 0x2364, 0x2564, 0x2765, 0x2965, 0x3164 452 */ 453 #define SLG51000_SEL_START_ILIM_SHIFT 0 454 #define SLG51000_SEL_START_ILIM_MASK (0x7f << 0) 455 456 /* SLG51000_LDO3_CONF2 ~ SLG51000_LDO7_CONF2 = 457 * 0x2365, 0x2565, 0x2766, 0x2966, 0x3165 458 */ 459 #define SLG51000_SEL_FUNC_ILIM_SHIFT 0 460 #define SLG51000_SEL_FUNC_ILIM_MASK (0x7f << 0) 461 462 /* SLG51000_LDO5_TRIM2 = 0x2763, SLG51000_LDO6_TRIM2 = 0x2963 */ 463 #define SLG51000_SEL_BYP_SLEW_RATE_SHIFT 2 464 #define SLG51000_SEL_BYP_SLEW_RATE_MASK (0x03 << 2) 465 #define SLG51000_SEL_BYP_VGATE_SHIFT 1 466 #define SLG51000_SEL_BYP_VGATE_MASK (0x01 << 1) 467 #define SLG51000_SEL_BYP_MODE_SHIFT 0 468 #define SLG51000_SEL_BYP_MODE_MASK (0x01 << 0) 469 470 /* SLG51000_OTP_EVENT = 0x782b */ 471 #define SLG51000_EVT_CRC_SHIFT 0 472 #define SLG51000_EVT_CRC_MASK (0x01 << 0) 473 474 /* SLG51000_OTP_IRQ_MASK = 0x782d */ 475 #define SLG51000_IRQ_CRC_SHIFT 0 476 #define SLG51000_IRQ_CRC_MASK (0x01 << 0) 477 478 /* SLG51000_OTP_LOCK_OTP_PROG = 0x78fe */ 479 #define SLG51000_LOCK_OTP_PROG_SHIFT 0 480 #define SLG51000_LOCK_OTP_PROG_MASK (0x01 << 0) 481 482 /* SLG51000_OTP_LOCK_CTRL = 0x78ff */ 483 #define SLG51000_LOCK_DFT_SHIFT 1 484 #define SLG51000_LOCK_DFT_MASK (0x01 << 1) 485 #define SLG51000_LOCK_RWT_SHIFT 0 486 #define SLG51000_LOCK_RWT_MASK (0x01 << 0) 487 488 /* SLG51000_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */ 489 #define SLG51000_LDO7_LOCK_SHIFT 7 490 #define SLG51000_LDO7_LOCK_MASK (0x01 << 7) 491 #define SLG51000_LDO6_LOCK_SHIFT 6 492 #define SLG51000_LDO6_LOCK_MASK (0x01 << 6) 493 #define SLG51000_LDO5_LOCK_SHIFT 5 494 #define SLG51000_LDO5_LOCK_MASK (0x01 << 5) 495 #define SLG51000_LDO4_LOCK_SHIFT 4 496 #define SLG51000_LDO4_LOCK_MASK (0x01 << 4) 497 #define SLG51000_LDO3_LOCK_SHIFT 3 498 #define SLG51000_LDO3_LOCK_MASK (0x01 << 3) 499 #define SLG51000_LDO2_LOCK_SHIFT 2 500 #define SLG51000_LDO2_LOCK_MASK (0x01 << 2) 501 #define SLG51000_LDO1_LOCK_SHIFT 1 502 #define SLG51000_LDO1_LOCK_MASK (0x01 << 1) 503 504 #endif /* __SLG51000_REGISTERS_H__ */ 505 506