1433c9bb7SErick Chen // SPDX-License-Identifier: GPL-2.0
2433c9bb7SErick Chen /*
3433c9bb7SErick Chen * Copyright (C) 2017 Spreadtrum Communications Inc.
4433c9bb7SErick Chen */
5433c9bb7SErick Chen
6433c9bb7SErick Chen #include <linux/module.h>
7433c9bb7SErick Chen #include <linux/of.h>
8433c9bb7SErick Chen #include <linux/platform_device.h>
9433c9bb7SErick Chen #include <linux/regmap.h>
10433c9bb7SErick Chen #include <linux/regulator/driver.h>
11433c9bb7SErick Chen #include <linux/regulator/of_regulator.h>
12433c9bb7SErick Chen
13433c9bb7SErick Chen /*
14433c9bb7SErick Chen * SC2731 regulator lock register
15433c9bb7SErick Chen */
16fa32f7a3SAxel Lin #define SC2731_PWR_WR_PROT 0xf0c
17fa32f7a3SAxel Lin #define SC2731_WR_UNLOCK_VALUE 0x6e7f
18433c9bb7SErick Chen
19433c9bb7SErick Chen /*
20433c9bb7SErick Chen * SC2731 enable register
21433c9bb7SErick Chen */
22433c9bb7SErick Chen #define SC2731_POWER_PD_SW 0xc28
23433c9bb7SErick Chen #define SC2731_LDO_CAMA0_PD 0xcfc
24433c9bb7SErick Chen #define SC2731_LDO_CAMA1_PD 0xd04
25433c9bb7SErick Chen #define SC2731_LDO_CAMMOT_PD 0xd0c
26433c9bb7SErick Chen #define SC2731_LDO_VLDO_PD 0xd6c
27433c9bb7SErick Chen #define SC2731_LDO_EMMCCORE_PD 0xd2c
28433c9bb7SErick Chen #define SC2731_LDO_SDCORE_PD 0xd74
29433c9bb7SErick Chen #define SC2731_LDO_SDIO_PD 0xd70
30433c9bb7SErick Chen #define SC2731_LDO_WIFIPA_PD 0xd4c
31433c9bb7SErick Chen #define SC2731_LDO_USB33_PD 0xd5c
32433c9bb7SErick Chen #define SC2731_LDO_CAMD0_PD 0xd7c
33433c9bb7SErick Chen #define SC2731_LDO_CAMD1_PD 0xd84
34433c9bb7SErick Chen #define SC2731_LDO_CON_PD 0xd8c
35433c9bb7SErick Chen #define SC2731_LDO_CAMIO_PD 0xd94
36433c9bb7SErick Chen #define SC2731_LDO_SRAM_PD 0xd78
37433c9bb7SErick Chen
38433c9bb7SErick Chen /*
39433c9bb7SErick Chen * SC2731 enable mask
40433c9bb7SErick Chen */
41433c9bb7SErick Chen #define SC2731_DCDC_CPU0_PD_MASK BIT(4)
42433c9bb7SErick Chen #define SC2731_DCDC_CPU1_PD_MASK BIT(3)
43433c9bb7SErick Chen #define SC2731_DCDC_RF_PD_MASK BIT(11)
44433c9bb7SErick Chen #define SC2731_LDO_CAMA0_PD_MASK BIT(0)
45433c9bb7SErick Chen #define SC2731_LDO_CAMA1_PD_MASK BIT(0)
46433c9bb7SErick Chen #define SC2731_LDO_CAMMOT_PD_MASK BIT(0)
47433c9bb7SErick Chen #define SC2731_LDO_VLDO_PD_MASK BIT(0)
48433c9bb7SErick Chen #define SC2731_LDO_EMMCCORE_PD_MASK BIT(0)
49433c9bb7SErick Chen #define SC2731_LDO_SDCORE_PD_MASK BIT(0)
50433c9bb7SErick Chen #define SC2731_LDO_SDIO_PD_MASK BIT(0)
51433c9bb7SErick Chen #define SC2731_LDO_WIFIPA_PD_MASK BIT(0)
52433c9bb7SErick Chen #define SC2731_LDO_USB33_PD_MASK BIT(0)
53433c9bb7SErick Chen #define SC2731_LDO_CAMD0_PD_MASK BIT(0)
54433c9bb7SErick Chen #define SC2731_LDO_CAMD1_PD_MASK BIT(0)
55433c9bb7SErick Chen #define SC2731_LDO_CON_PD_MASK BIT(0)
56433c9bb7SErick Chen #define SC2731_LDO_CAMIO_PD_MASK BIT(0)
57433c9bb7SErick Chen #define SC2731_LDO_SRAM_PD_MASK BIT(0)
58433c9bb7SErick Chen
59433c9bb7SErick Chen /*
60433c9bb7SErick Chen * SC2731 vsel register
61433c9bb7SErick Chen */
62433c9bb7SErick Chen #define SC2731_DCDC_CPU0_VOL 0xc54
63433c9bb7SErick Chen #define SC2731_DCDC_CPU1_VOL 0xc64
64433c9bb7SErick Chen #define SC2731_DCDC_RF_VOL 0xcb8
65433c9bb7SErick Chen #define SC2731_LDO_CAMA0_VOL 0xd00
66433c9bb7SErick Chen #define SC2731_LDO_CAMA1_VOL 0xd08
67433c9bb7SErick Chen #define SC2731_LDO_CAMMOT_VOL 0xd10
68433c9bb7SErick Chen #define SC2731_LDO_VLDO_VOL 0xd28
69433c9bb7SErick Chen #define SC2731_LDO_EMMCCORE_VOL 0xd30
70433c9bb7SErick Chen #define SC2731_LDO_SDCORE_VOL 0xd38
71433c9bb7SErick Chen #define SC2731_LDO_SDIO_VOL 0xd40
72433c9bb7SErick Chen #define SC2731_LDO_WIFIPA_VOL 0xd50
73433c9bb7SErick Chen #define SC2731_LDO_USB33_VOL 0xd60
74433c9bb7SErick Chen #define SC2731_LDO_CAMD0_VOL 0xd80
75433c9bb7SErick Chen #define SC2731_LDO_CAMD1_VOL 0xd88
76433c9bb7SErick Chen #define SC2731_LDO_CON_VOL 0xd90
77433c9bb7SErick Chen #define SC2731_LDO_CAMIO_VOL 0xd98
78433c9bb7SErick Chen #define SC2731_LDO_SRAM_VOL 0xdB0
79433c9bb7SErick Chen
80433c9bb7SErick Chen /*
81433c9bb7SErick Chen * SC2731 vsel register mask
82433c9bb7SErick Chen */
83433c9bb7SErick Chen #define SC2731_DCDC_CPU0_VOL_MASK GENMASK(8, 0)
84433c9bb7SErick Chen #define SC2731_DCDC_CPU1_VOL_MASK GENMASK(8, 0)
85433c9bb7SErick Chen #define SC2731_DCDC_RF_VOL_MASK GENMASK(8, 0)
86433c9bb7SErick Chen #define SC2731_LDO_CAMA0_VOL_MASK GENMASK(7, 0)
87433c9bb7SErick Chen #define SC2731_LDO_CAMA1_VOL_MASK GENMASK(7, 0)
88433c9bb7SErick Chen #define SC2731_LDO_CAMMOT_VOL_MASK GENMASK(7, 0)
89433c9bb7SErick Chen #define SC2731_LDO_VLDO_VOL_MASK GENMASK(7, 0)
90433c9bb7SErick Chen #define SC2731_LDO_EMMCCORE_VOL_MASK GENMASK(7, 0)
91433c9bb7SErick Chen #define SC2731_LDO_SDCORE_VOL_MASK GENMASK(7, 0)
92433c9bb7SErick Chen #define SC2731_LDO_SDIO_VOL_MASK GENMASK(7, 0)
93433c9bb7SErick Chen #define SC2731_LDO_WIFIPA_VOL_MASK GENMASK(7, 0)
94433c9bb7SErick Chen #define SC2731_LDO_USB33_VOL_MASK GENMASK(7, 0)
95433c9bb7SErick Chen #define SC2731_LDO_CAMD0_VOL_MASK GENMASK(6, 0)
96433c9bb7SErick Chen #define SC2731_LDO_CAMD1_VOL_MASK GENMASK(6, 0)
97433c9bb7SErick Chen #define SC2731_LDO_CON_VOL_MASK GENMASK(6, 0)
98433c9bb7SErick Chen #define SC2731_LDO_CAMIO_VOL_MASK GENMASK(6, 0)
99433c9bb7SErick Chen #define SC2731_LDO_SRAM_VOL_MASK GENMASK(6, 0)
100433c9bb7SErick Chen
101433c9bb7SErick Chen enum sc2731_regulator_id {
102433c9bb7SErick Chen SC2731_BUCK_CPU0,
103433c9bb7SErick Chen SC2731_BUCK_CPU1,
104433c9bb7SErick Chen SC2731_BUCK_RF,
105433c9bb7SErick Chen SC2731_LDO_CAMA0,
106433c9bb7SErick Chen SC2731_LDO_CAMA1,
107433c9bb7SErick Chen SC2731_LDO_CAMMOT,
108433c9bb7SErick Chen SC2731_LDO_VLDO,
109433c9bb7SErick Chen SC2731_LDO_EMMCCORE,
110433c9bb7SErick Chen SC2731_LDO_SDCORE,
111433c9bb7SErick Chen SC2731_LDO_SDIO,
112433c9bb7SErick Chen SC2731_LDO_WIFIPA,
113433c9bb7SErick Chen SC2731_LDO_USB33,
114433c9bb7SErick Chen SC2731_LDO_CAMD0,
115433c9bb7SErick Chen SC2731_LDO_CAMD1,
116433c9bb7SErick Chen SC2731_LDO_CON,
117433c9bb7SErick Chen SC2731_LDO_CAMIO,
118433c9bb7SErick Chen SC2731_LDO_SRAM,
119433c9bb7SErick Chen };
120433c9bb7SErick Chen
121433c9bb7SErick Chen static const struct regulator_ops sc2731_regu_linear_ops = {
122433c9bb7SErick Chen .enable = regulator_enable_regmap,
123433c9bb7SErick Chen .disable = regulator_disable_regmap,
124433c9bb7SErick Chen .is_enabled = regulator_is_enabled_regmap,
125433c9bb7SErick Chen .list_voltage = regulator_list_voltage_linear,
126433c9bb7SErick Chen .get_voltage_sel = regulator_get_voltage_sel_regmap,
127433c9bb7SErick Chen .set_voltage_sel = regulator_set_voltage_sel_regmap,
128433c9bb7SErick Chen };
129433c9bb7SErick Chen
130433c9bb7SErick Chen #define SC2731_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask, \
131433c9bb7SErick Chen vstep, vmin, vmax) { \
132433c9bb7SErick Chen .name = #_id, \
133433c9bb7SErick Chen .of_match = of_match_ptr(#_id), \
134433c9bb7SErick Chen .ops = &sc2731_regu_linear_ops, \
135433c9bb7SErick Chen .type = REGULATOR_VOLTAGE, \
136433c9bb7SErick Chen .id = SC2731_##_id, \
137433c9bb7SErick Chen .owner = THIS_MODULE, \
138433c9bb7SErick Chen .min_uV = vmin, \
139433c9bb7SErick Chen .n_voltages = ((vmax) - (vmin)) / (vstep) + 1, \
140433c9bb7SErick Chen .uV_step = vstep, \
141433c9bb7SErick Chen .enable_is_inverted = true, \
142433c9bb7SErick Chen .enable_val = 0, \
143433c9bb7SErick Chen .enable_reg = en_reg, \
144433c9bb7SErick Chen .enable_mask = en_mask, \
145433c9bb7SErick Chen .vsel_reg = vreg, \
146433c9bb7SErick Chen .vsel_mask = vmask, \
147433c9bb7SErick Chen }
148433c9bb7SErick Chen
149883ce242SAxel Lin static const struct regulator_desc regulators[] = {
150433c9bb7SErick Chen SC2731_REGU_LINEAR(BUCK_CPU0, SC2731_POWER_PD_SW,
151433c9bb7SErick Chen SC2731_DCDC_CPU0_PD_MASK, SC2731_DCDC_CPU0_VOL,
152433c9bb7SErick Chen SC2731_DCDC_CPU0_VOL_MASK, 3125, 400000, 1996875),
153433c9bb7SErick Chen SC2731_REGU_LINEAR(BUCK_CPU1, SC2731_POWER_PD_SW,
154433c9bb7SErick Chen SC2731_DCDC_CPU1_PD_MASK, SC2731_DCDC_CPU1_VOL,
155433c9bb7SErick Chen SC2731_DCDC_CPU1_VOL_MASK, 3125, 400000, 1996875),
156433c9bb7SErick Chen SC2731_REGU_LINEAR(BUCK_RF, SC2731_POWER_PD_SW, SC2731_DCDC_RF_PD_MASK,
157433c9bb7SErick Chen SC2731_DCDC_RF_VOL, SC2731_DCDC_RF_VOL_MASK,
158433c9bb7SErick Chen 3125, 600000, 2196875),
159433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CAMA0, SC2731_LDO_CAMA0_PD,
160433c9bb7SErick Chen SC2731_LDO_CAMA0_PD_MASK, SC2731_LDO_CAMA0_VOL,
161433c9bb7SErick Chen SC2731_LDO_CAMA0_VOL_MASK, 10000, 1200000, 3750000),
162433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CAMA1, SC2731_LDO_CAMA1_PD,
163433c9bb7SErick Chen SC2731_LDO_CAMA1_PD_MASK, SC2731_LDO_CAMA1_VOL,
164433c9bb7SErick Chen SC2731_LDO_CAMA1_VOL_MASK, 10000, 1200000, 3750000),
165433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CAMMOT, SC2731_LDO_CAMMOT_PD,
166433c9bb7SErick Chen SC2731_LDO_CAMMOT_PD_MASK, SC2731_LDO_CAMMOT_VOL,
167433c9bb7SErick Chen SC2731_LDO_CAMMOT_VOL_MASK, 10000, 1200000, 3750000),
168433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_VLDO, SC2731_LDO_VLDO_PD,
169433c9bb7SErick Chen SC2731_LDO_VLDO_PD_MASK, SC2731_LDO_VLDO_VOL,
170433c9bb7SErick Chen SC2731_LDO_VLDO_VOL_MASK, 10000, 1200000, 3750000),
171433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_EMMCCORE, SC2731_LDO_EMMCCORE_PD,
172433c9bb7SErick Chen SC2731_LDO_EMMCCORE_PD_MASK, SC2731_LDO_EMMCCORE_VOL,
173433c9bb7SErick Chen SC2731_LDO_EMMCCORE_VOL_MASK, 10000, 1200000,
174433c9bb7SErick Chen 3750000),
175433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_SDCORE, SC2731_LDO_SDCORE_PD,
176433c9bb7SErick Chen SC2731_LDO_SDCORE_PD_MASK, SC2731_LDO_SDCORE_VOL,
177433c9bb7SErick Chen SC2731_LDO_SDCORE_VOL_MASK, 10000, 1200000, 3750000),
178433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_SDIO, SC2731_LDO_SDIO_PD,
179433c9bb7SErick Chen SC2731_LDO_SDIO_PD_MASK, SC2731_LDO_SDIO_VOL,
180433c9bb7SErick Chen SC2731_LDO_SDIO_VOL_MASK, 10000, 1200000, 3750000),
181433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_WIFIPA, SC2731_LDO_WIFIPA_PD,
182433c9bb7SErick Chen SC2731_LDO_WIFIPA_PD_MASK, SC2731_LDO_WIFIPA_VOL,
183433c9bb7SErick Chen SC2731_LDO_WIFIPA_VOL_MASK, 10000, 1200000, 3750000),
184433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_USB33, SC2731_LDO_USB33_PD,
185433c9bb7SErick Chen SC2731_LDO_USB33_PD_MASK, SC2731_LDO_USB33_VOL,
186433c9bb7SErick Chen SC2731_LDO_USB33_VOL_MASK, 10000, 1200000, 3750000),
187433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CAMD0, SC2731_LDO_CAMD0_PD,
188433c9bb7SErick Chen SC2731_LDO_CAMD0_PD_MASK, SC2731_LDO_CAMD0_VOL,
189433c9bb7SErick Chen SC2731_LDO_CAMD0_VOL_MASK, 6250, 1000000, 1793750),
190433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CAMD1, SC2731_LDO_CAMD1_PD,
191433c9bb7SErick Chen SC2731_LDO_CAMD1_PD_MASK, SC2731_LDO_CAMD1_VOL,
192433c9bb7SErick Chen SC2731_LDO_CAMD1_VOL_MASK, 6250, 1000000, 1793750),
193433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CON, SC2731_LDO_CON_PD,
194433c9bb7SErick Chen SC2731_LDO_CON_PD_MASK, SC2731_LDO_CON_VOL,
195433c9bb7SErick Chen SC2731_LDO_CON_VOL_MASK, 6250, 1000000, 1793750),
196433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_CAMIO, SC2731_LDO_CAMIO_PD,
197433c9bb7SErick Chen SC2731_LDO_CAMIO_PD_MASK, SC2731_LDO_CAMIO_VOL,
198433c9bb7SErick Chen SC2731_LDO_CAMIO_VOL_MASK, 6250, 1000000, 1793750),
199433c9bb7SErick Chen SC2731_REGU_LINEAR(LDO_SRAM, SC2731_LDO_SRAM_PD,
200433c9bb7SErick Chen SC2731_LDO_SRAM_PD_MASK, SC2731_LDO_SRAM_VOL,
201433c9bb7SErick Chen SC2731_LDO_SRAM_VOL_MASK, 6250, 1000000, 1793750),
202433c9bb7SErick Chen };
203433c9bb7SErick Chen
sc2731_regulator_unlock(struct regmap * regmap)204433c9bb7SErick Chen static int sc2731_regulator_unlock(struct regmap *regmap)
205433c9bb7SErick Chen {
206fa32f7a3SAxel Lin return regmap_write(regmap, SC2731_PWR_WR_PROT,
207fa32f7a3SAxel Lin SC2731_WR_UNLOCK_VALUE);
208433c9bb7SErick Chen }
209433c9bb7SErick Chen
sc2731_regulator_probe(struct platform_device * pdev)210433c9bb7SErick Chen static int sc2731_regulator_probe(struct platform_device *pdev)
211433c9bb7SErick Chen {
212433c9bb7SErick Chen int i, ret;
213433c9bb7SErick Chen struct regmap *regmap;
214433c9bb7SErick Chen struct regulator_config config = { };
215433c9bb7SErick Chen struct regulator_dev *rdev;
216433c9bb7SErick Chen
217433c9bb7SErick Chen regmap = dev_get_regmap(pdev->dev.parent, NULL);
218433c9bb7SErick Chen if (!regmap) {
219433c9bb7SErick Chen dev_err(&pdev->dev, "failed to get regmap.\n");
220433c9bb7SErick Chen return -ENODEV;
221433c9bb7SErick Chen }
222433c9bb7SErick Chen
223433c9bb7SErick Chen ret = sc2731_regulator_unlock(regmap);
224433c9bb7SErick Chen if (ret) {
225433c9bb7SErick Chen dev_err(&pdev->dev, "failed to release regulator lock\n");
226433c9bb7SErick Chen return ret;
227433c9bb7SErick Chen }
228433c9bb7SErick Chen
229433c9bb7SErick Chen config.dev = &pdev->dev;
230433c9bb7SErick Chen config.regmap = regmap;
231433c9bb7SErick Chen
232433c9bb7SErick Chen for (i = 0; i < ARRAY_SIZE(regulators); i++) {
233433c9bb7SErick Chen rdev = devm_regulator_register(&pdev->dev, ®ulators[i],
234433c9bb7SErick Chen &config);
235433c9bb7SErick Chen if (IS_ERR(rdev)) {
236433c9bb7SErick Chen dev_err(&pdev->dev, "failed to register regulator %s\n",
237433c9bb7SErick Chen regulators[i].name);
238433c9bb7SErick Chen return PTR_ERR(rdev);
239433c9bb7SErick Chen }
240433c9bb7SErick Chen }
241433c9bb7SErick Chen
242433c9bb7SErick Chen return 0;
243433c9bb7SErick Chen }
244433c9bb7SErick Chen
245433c9bb7SErick Chen static struct platform_driver sc2731_regulator_driver = {
246433c9bb7SErick Chen .driver = {
247433c9bb7SErick Chen .name = "sc27xx-regulator",
248*ed6962ccSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
249433c9bb7SErick Chen },
250433c9bb7SErick Chen .probe = sc2731_regulator_probe,
251433c9bb7SErick Chen };
252433c9bb7SErick Chen
253433c9bb7SErick Chen module_platform_driver(sc2731_regulator_driver);
254433c9bb7SErick Chen
255433c9bb7SErick Chen MODULE_AUTHOR("Chen Junhui <erick.chen@spreadtrum.com>");
256433c9bb7SErick Chen MODULE_DESCRIPTION("Spreadtrum SC2731 regulator driver");
257433c9bb7SErick Chen MODULE_LICENSE("GPL v2");
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