1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/delay.h> 8 #include <linux/devm-helpers.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/interrupt.h> 12 #include <linux/bitops.h> 13 #include <linux/slab.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/ktime.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regmap.h> 20 #include <linux/list.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/io.h> 23 24 /* Pin control enable input pins. */ 25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01 27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02 28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04 29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08 30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10 31 32 /* Pin control high power mode input pins. */ 33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00 34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01 35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02 36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04 37 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08 38 #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10 39 #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20 40 41 /* 42 * Used with enable parameters to specify that hardware default register values 43 * should be left unaltered. 44 */ 45 #define SPMI_REGULATOR_USE_HW_DEFAULT 2 46 47 /* Soft start strength of a voltage switch type regulator */ 48 enum spmi_vs_soft_start_str { 49 SPMI_VS_SOFT_START_STR_0P05_UA = 0, 50 SPMI_VS_SOFT_START_STR_0P25_UA, 51 SPMI_VS_SOFT_START_STR_0P55_UA, 52 SPMI_VS_SOFT_START_STR_0P75_UA, 53 SPMI_VS_SOFT_START_STR_HW_DEFAULT, 54 }; 55 56 /** 57 * struct spmi_regulator_init_data - spmi-regulator initialization data 58 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be 59 * used to enable the regulator, if any 60 * Value should be an ORing of 61 * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If 62 * the bit specified by 63 * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is 64 * set, then pin control enable hardware registers 65 * will not be modified. 66 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be 67 * used to force the regulator into high power 68 * mode, if any 69 * Value should be an ORing of 70 * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If 71 * the bit specified by 72 * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is 73 * set, then pin control mode hardware registers 74 * will not be modified. 75 * @vs_soft_start_strength: This parameter sets the soft start strength for 76 * voltage switch type regulators. Its value 77 * should be one of SPMI_VS_SOFT_START_STR_*. If 78 * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT, 79 * then the soft start strength will be left at its 80 * default hardware value. 81 */ 82 struct spmi_regulator_init_data { 83 unsigned pin_ctrl_enable; 84 unsigned pin_ctrl_hpm; 85 enum spmi_vs_soft_start_str vs_soft_start_strength; 86 }; 87 88 /* These types correspond to unique register layouts. */ 89 enum spmi_regulator_logical_type { 90 SPMI_REGULATOR_LOGICAL_TYPE_SMPS, 91 SPMI_REGULATOR_LOGICAL_TYPE_LDO, 92 SPMI_REGULATOR_LOGICAL_TYPE_VS, 93 SPMI_REGULATOR_LOGICAL_TYPE_BOOST, 94 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS, 95 SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP, 96 SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO, 97 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, 98 SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, 99 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, 100 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, 101 SPMI_REGULATOR_LOGICAL_TYPE_HFS430, 102 }; 103 104 enum spmi_regulator_type { 105 SPMI_REGULATOR_TYPE_BUCK = 0x03, 106 SPMI_REGULATOR_TYPE_LDO = 0x04, 107 SPMI_REGULATOR_TYPE_VS = 0x05, 108 SPMI_REGULATOR_TYPE_BOOST = 0x1b, 109 SPMI_REGULATOR_TYPE_FTS = 0x1c, 110 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f, 111 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21, 112 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22, 113 }; 114 115 enum spmi_regulator_subtype { 116 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08, 117 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09, 118 SPMI_REGULATOR_SUBTYPE_N50 = 0x01, 119 SPMI_REGULATOR_SUBTYPE_N150 = 0x02, 120 SPMI_REGULATOR_SUBTYPE_N300 = 0x03, 121 SPMI_REGULATOR_SUBTYPE_N600 = 0x04, 122 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05, 123 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06, 124 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07, 125 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14, 126 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15, 127 SPMI_REGULATOR_SUBTYPE_P50 = 0x08, 128 SPMI_REGULATOR_SUBTYPE_P150 = 0x09, 129 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a, 130 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b, 131 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c, 132 SPMI_REGULATOR_SUBTYPE_LN = 0x10, 133 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28, 134 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29, 135 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a, 136 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b, 137 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c, 138 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d, 139 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30, 140 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31, 141 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32, 142 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b, 143 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c, 144 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42, 145 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43, 146 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46, 147 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47, 148 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49, 149 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d, 150 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f, 151 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01, 152 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02, 153 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08, 154 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09, 155 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10, 156 SPMI_REGULATOR_SUBTYPE_OTG = 0x11, 157 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, 158 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, 159 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, 160 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a, 161 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, 162 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, 163 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, 164 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, 165 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, 166 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, 167 }; 168 169 enum spmi_common_regulator_registers { 170 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01, 171 SPMI_COMMON_REG_TYPE = 0x04, 172 SPMI_COMMON_REG_SUBTYPE = 0x05, 173 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40, 174 SPMI_COMMON_REG_VOLTAGE_SET = 0x41, 175 SPMI_COMMON_REG_MODE = 0x45, 176 SPMI_COMMON_REG_ENABLE = 0x46, 177 SPMI_COMMON_REG_PULL_DOWN = 0x48, 178 SPMI_COMMON_REG_SOFT_START = 0x4c, 179 SPMI_COMMON_REG_STEP_CTRL = 0x61, 180 }; 181 182 /* 183 * Second common register layout used by newer devices starting with ftsmps426 184 * Note that some of the registers from the first common layout remain 185 * unchanged and their definition is not duplicated. 186 */ 187 enum spmi_ftsmps426_regulator_registers { 188 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40, 189 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41, 190 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68, 191 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, 192 }; 193 194 enum spmi_vs_registers { 195 SPMI_VS_REG_OCP = 0x4a, 196 SPMI_VS_REG_SOFT_START = 0x4c, 197 }; 198 199 enum spmi_boost_registers { 200 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a, 201 }; 202 203 enum spmi_boost_byp_registers { 204 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, 205 }; 206 207 enum spmi_saw3_registers { 208 SAW3_SECURE = 0x00, 209 SAW3_ID = 0x04, 210 SAW3_SPM_STS = 0x0C, 211 SAW3_AVS_STS = 0x10, 212 SAW3_PMIC_STS = 0x14, 213 SAW3_RST = 0x18, 214 SAW3_VCTL = 0x1C, 215 SAW3_AVS_CTL = 0x20, 216 SAW3_AVS_LIMIT = 0x24, 217 SAW3_AVS_DLY = 0x28, 218 SAW3_AVS_HYSTERESIS = 0x2C, 219 SAW3_SPM_STS2 = 0x38, 220 SAW3_SPM_PMIC_DATA_3 = 0x4C, 221 SAW3_VERSION = 0xFD0, 222 }; 223 224 /* Used for indexing into ctrl_reg. These are offets from 0x40 */ 225 enum spmi_common_control_register_index { 226 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, 227 SPMI_COMMON_IDX_VOLTAGE_SET = 1, 228 SPMI_COMMON_IDX_MODE = 5, 229 SPMI_COMMON_IDX_ENABLE = 6, 230 }; 231 232 /* Common regulator control register layout */ 233 #define SPMI_COMMON_ENABLE_MASK 0x80 234 #define SPMI_COMMON_ENABLE 0x80 235 #define SPMI_COMMON_DISABLE 0x00 236 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08 237 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04 238 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02 239 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01 240 #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f 241 242 /* Common regulator mode register layout */ 243 #define SPMI_COMMON_MODE_HPM_MASK 0x80 244 #define SPMI_COMMON_MODE_AUTO_MASK 0x40 245 #define SPMI_COMMON_MODE_BYPASS_MASK 0x20 246 #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10 247 #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08 248 #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04 249 #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02 250 #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 251 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f 252 253 #define SPMI_FTSMPS426_MODE_BYPASS_MASK 3 254 #define SPMI_FTSMPS426_MODE_RETENTION_MASK 4 255 #define SPMI_FTSMPS426_MODE_LPM_MASK 5 256 #define SPMI_FTSMPS426_MODE_AUTO_MASK 6 257 #define SPMI_FTSMPS426_MODE_HPM_MASK 7 258 259 #define SPMI_FTSMPS426_MODE_MASK 0x07 260 261 /* Common regulator pull down control register layout */ 262 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 263 264 /* LDO regulator current limit control register layout */ 265 #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80 266 267 /* LDO regulator soft start control register layout */ 268 #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80 269 270 /* VS regulator over current protection control register layout */ 271 #define SPMI_VS_OCP_OVERRIDE 0x01 272 #define SPMI_VS_OCP_NO_OVERRIDE 0x00 273 274 /* VS regulator soft start control register layout */ 275 #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80 276 #define SPMI_VS_SOFT_START_SEL_MASK 0x03 277 278 /* Boost regulator current limit control register layout */ 279 #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80 280 #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07 281 282 #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10 283 #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30 284 #define SPMI_VS_OCP_FALL_DELAY_US 90 285 #define SPMI_VS_OCP_FAULT_DELAY_US 20000 286 287 #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18 288 #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3 289 #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 290 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 291 292 /* Clock rate in kHz of the FTSMPS regulator reference clock. */ 293 #define SPMI_FTSMPS_CLOCK_RATE 19200 294 295 /* Minimum voltage stepper delay for each step. */ 296 #define SPMI_FTSMPS_STEP_DELAY 8 297 #define SPMI_DEFAULT_STEP_DELAY 20 298 299 /* 300 * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to 301 * adjust the step rate in order to account for oscillator variance. 302 */ 303 #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 304 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 305 306 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 307 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 308 309 /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */ 310 #define SPMI_FTSMPS426_CLOCK_RATE 4800 311 312 #define SPMI_HFS430_CLOCK_RATE 1600 313 314 /* Minimum voltage stepper delay for each step. */ 315 #define SPMI_FTSMPS426_STEP_DELAY 2 316 317 /* 318 * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is 319 * used to adjust the step rate in order to account for oscillator variance. 320 */ 321 #define SPMI_FTSMPS426_STEP_MARGIN_NUM 10 322 #define SPMI_FTSMPS426_STEP_MARGIN_DEN 11 323 324 325 /* VSET value to decide the range of ULT SMPS */ 326 #define ULT_SMPS_RANGE_SPLIT 0x60 327 328 /** 329 * struct spmi_voltage_range - regulator set point voltage mapping description 330 * @min_uV: Minimum programmable output voltage resulting from 331 * set point register value 0x00 332 * @max_uV: Maximum programmable output voltage 333 * @step_uV: Output voltage increase resulting from the set point 334 * register value increasing by 1 335 * @set_point_min_uV: Minimum allowed voltage 336 * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order 337 * to pick which range should be used in the case of 338 * overlapping set points. 339 * @n_voltages: Number of preferred voltage set points present in this 340 * range 341 * @range_sel: Voltage range register value corresponding to this range 342 * 343 * The following relationships must be true for the values used in this struct: 344 * (max_uV - min_uV) % step_uV == 0 345 * (set_point_min_uV - min_uV) % step_uV == 0* 346 * (set_point_max_uV - min_uV) % step_uV == 0* 347 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1 348 * 349 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to 350 * specify that the voltage range has meaning, but is not preferred. 351 */ 352 struct spmi_voltage_range { 353 int min_uV; 354 int max_uV; 355 int step_uV; 356 int set_point_min_uV; 357 int set_point_max_uV; 358 unsigned n_voltages; 359 u8 range_sel; 360 }; 361 362 /* 363 * The ranges specified in the spmi_voltage_set_points struct must be listed 364 * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV. 365 */ 366 struct spmi_voltage_set_points { 367 struct spmi_voltage_range *range; 368 int count; 369 unsigned n_voltages; 370 }; 371 372 struct spmi_regulator { 373 struct regulator_desc desc; 374 struct device *dev; 375 struct delayed_work ocp_work; 376 struct regmap *regmap; 377 struct spmi_voltage_set_points *set_points; 378 enum spmi_regulator_logical_type logical_type; 379 int ocp_irq; 380 int ocp_count; 381 int ocp_max_retries; 382 int ocp_retry_delay_ms; 383 int hpm_min_load; 384 int slew_rate; 385 ktime_t vs_enable_time; 386 u16 base; 387 struct list_head node; 388 }; 389 390 struct spmi_regulator_mapping { 391 enum spmi_regulator_type type; 392 enum spmi_regulator_subtype subtype; 393 enum spmi_regulator_logical_type logical_type; 394 u32 revision_min; 395 u32 revision_max; 396 const struct regulator_ops *ops; 397 struct spmi_voltage_set_points *set_points; 398 int hpm_min_load; 399 }; 400 401 struct spmi_regulator_data { 402 const char *name; 403 u16 base; 404 const char *supply; 405 const char *ocp; 406 u16 force_type; 407 }; 408 409 #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \ 410 _logical_type, _ops_val, _set_points_val, _hpm_min_load) \ 411 { \ 412 .type = SPMI_REGULATOR_TYPE_##_type, \ 413 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ 414 .revision_min = _dig_major_min, \ 415 .revision_max = _dig_major_max, \ 416 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \ 417 .ops = &spmi_##_ops_val##_ops, \ 418 .set_points = &_set_points_val##_set_points, \ 419 .hpm_min_load = _hpm_min_load, \ 420 } 421 422 #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \ 423 { \ 424 .type = SPMI_REGULATOR_TYPE_VS, \ 425 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ 426 .revision_min = _dig_major_min, \ 427 .revision_max = _dig_major_max, \ 428 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \ 429 .ops = &spmi_vs_ops, \ 430 } 431 432 #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \ 433 _set_point_max_uV, _max_uV, _step_uV) \ 434 { \ 435 .min_uV = _min_uV, \ 436 .max_uV = _max_uV, \ 437 .set_point_min_uV = _set_point_min_uV, \ 438 .set_point_max_uV = _set_point_max_uV, \ 439 .step_uV = _step_uV, \ 440 .range_sel = _range_sel, \ 441 } 442 443 #define DEFINE_SPMI_SET_POINTS(name) \ 444 struct spmi_voltage_set_points name##_set_points = { \ 445 .range = name##_ranges, \ 446 .count = ARRAY_SIZE(name##_ranges), \ 447 } 448 449 /* 450 * These tables contain the physically available PMIC regulator voltage setpoint 451 * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed 452 * to ensure that the setpoints available to software are monotonically 453 * increasing and unique. The set_voltage callback functions expect these 454 * properties to hold. 455 */ 456 static struct spmi_voltage_range pldo_ranges[] = { 457 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), 458 SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000), 459 SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000), 460 }; 461 462 static struct spmi_voltage_range nldo1_ranges[] = { 463 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), 464 }; 465 466 static struct spmi_voltage_range nldo2_ranges[] = { 467 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500), 468 SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250), 469 SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500), 470 }; 471 472 static struct spmi_voltage_range nldo3_ranges[] = { 473 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), 474 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500), 475 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500), 476 }; 477 478 static struct spmi_voltage_range ln_ldo_ranges[] = { 479 SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000), 480 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000), 481 }; 482 483 static struct spmi_voltage_range smps_ranges[] = { 484 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), 485 SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), 486 }; 487 488 static struct spmi_voltage_range ftsmps_ranges[] = { 489 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), 490 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), 491 }; 492 493 static struct spmi_voltage_range ftsmps2p5_ranges[] = { 494 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000), 495 SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), 496 }; 497 498 static struct spmi_voltage_range ftsmps426_ranges[] = { 499 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000), 500 }; 501 502 static struct spmi_voltage_range boost_ranges[] = { 503 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), 504 }; 505 506 static struct spmi_voltage_range boost_byp_ranges[] = { 507 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000), 508 }; 509 510 static struct spmi_voltage_range ult_lo_smps_ranges[] = { 511 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), 512 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000), 513 }; 514 515 static struct spmi_voltage_range ult_ho_smps_ranges[] = { 516 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000), 517 }; 518 519 static struct spmi_voltage_range ult_nldo_ranges[] = { 520 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), 521 }; 522 523 static struct spmi_voltage_range ult_pldo_ranges[] = { 524 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), 525 }; 526 527 static struct spmi_voltage_range pldo660_ranges[] = { 528 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000), 529 }; 530 531 static struct spmi_voltage_range nldo660_ranges[] = { 532 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), 533 }; 534 535 static struct spmi_voltage_range ht_lvpldo_ranges[] = { 536 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000), 537 }; 538 539 static struct spmi_voltage_range ht_nldo_ranges[] = { 540 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000), 541 }; 542 543 static struct spmi_voltage_range hfs430_ranges[] = { 544 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), 545 }; 546 547 static DEFINE_SPMI_SET_POINTS(pldo); 548 static DEFINE_SPMI_SET_POINTS(nldo1); 549 static DEFINE_SPMI_SET_POINTS(nldo2); 550 static DEFINE_SPMI_SET_POINTS(nldo3); 551 static DEFINE_SPMI_SET_POINTS(ln_ldo); 552 static DEFINE_SPMI_SET_POINTS(smps); 553 static DEFINE_SPMI_SET_POINTS(ftsmps); 554 static DEFINE_SPMI_SET_POINTS(ftsmps2p5); 555 static DEFINE_SPMI_SET_POINTS(ftsmps426); 556 static DEFINE_SPMI_SET_POINTS(boost); 557 static DEFINE_SPMI_SET_POINTS(boost_byp); 558 static DEFINE_SPMI_SET_POINTS(ult_lo_smps); 559 static DEFINE_SPMI_SET_POINTS(ult_ho_smps); 560 static DEFINE_SPMI_SET_POINTS(ult_nldo); 561 static DEFINE_SPMI_SET_POINTS(ult_pldo); 562 static DEFINE_SPMI_SET_POINTS(pldo660); 563 static DEFINE_SPMI_SET_POINTS(nldo660); 564 static DEFINE_SPMI_SET_POINTS(ht_lvpldo); 565 static DEFINE_SPMI_SET_POINTS(ht_nldo); 566 static DEFINE_SPMI_SET_POINTS(hfs430); 567 568 static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, 569 int len) 570 { 571 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); 572 } 573 574 static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr, 575 u8 *buf, int len) 576 { 577 return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); 578 } 579 580 static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, 581 u8 mask) 582 { 583 return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); 584 } 585 586 static int spmi_regulator_vs_enable(struct regulator_dev *rdev) 587 { 588 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 589 590 if (vreg->ocp_irq) { 591 vreg->ocp_count = 0; 592 vreg->vs_enable_time = ktime_get(); 593 } 594 595 return regulator_enable_regmap(rdev); 596 } 597 598 static int spmi_regulator_vs_ocp(struct regulator_dev *rdev) 599 { 600 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 601 u8 reg = SPMI_VS_OCP_OVERRIDE; 602 603 return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1); 604 } 605 606 static int spmi_regulator_select_voltage(struct spmi_regulator *vreg, 607 int min_uV, int max_uV) 608 { 609 const struct spmi_voltage_range *range; 610 int uV = min_uV; 611 int lim_min_uV, lim_max_uV, i, range_id, range_max_uV; 612 int selector, voltage_sel; 613 614 /* Check if request voltage is outside of physically settable range. */ 615 lim_min_uV = vreg->set_points->range[0].set_point_min_uV; 616 lim_max_uV = 617 vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV; 618 619 if (uV < lim_min_uV && max_uV >= lim_min_uV) 620 uV = lim_min_uV; 621 622 if (uV < lim_min_uV || uV > lim_max_uV) { 623 dev_err(vreg->dev, 624 "request v=[%d, %d] is outside possible v=[%d, %d]\n", 625 min_uV, max_uV, lim_min_uV, lim_max_uV); 626 return -EINVAL; 627 } 628 629 /* Find the range which uV is inside of. */ 630 for (i = vreg->set_points->count - 1; i > 0; i--) { 631 range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV; 632 if (uV > range_max_uV && range_max_uV > 0) 633 break; 634 } 635 636 range_id = i; 637 range = &vreg->set_points->range[range_id]; 638 639 /* 640 * Force uV to be an allowed set point by applying a ceiling function to 641 * the uV value. 642 */ 643 voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); 644 uV = voltage_sel * range->step_uV + range->min_uV; 645 646 if (uV > max_uV) { 647 dev_err(vreg->dev, 648 "request v=[%d, %d] cannot be met by any set point; " 649 "next set point: %d\n", 650 min_uV, max_uV, uV); 651 return -EINVAL; 652 } 653 654 selector = 0; 655 for (i = 0; i < range_id; i++) 656 selector += vreg->set_points->range[i].n_voltages; 657 selector += (uV - range->set_point_min_uV) / range->step_uV; 658 659 return selector; 660 } 661 662 static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg, 663 unsigned selector, u8 *range_sel, 664 u8 *voltage_sel) 665 { 666 const struct spmi_voltage_range *range, *end; 667 unsigned offset; 668 669 range = vreg->set_points->range; 670 end = range + vreg->set_points->count; 671 672 for (; range < end; range++) { 673 if (selector < range->n_voltages) { 674 /* 675 * hardware selectors between set point min and real 676 * min are invalid so we ignore them 677 */ 678 offset = range->set_point_min_uV - range->min_uV; 679 offset /= range->step_uV; 680 *voltage_sel = selector + offset; 681 *range_sel = range->range_sel; 682 return 0; 683 } 684 685 selector -= range->n_voltages; 686 } 687 688 return -EINVAL; 689 } 690 691 static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel, 692 const struct spmi_voltage_range *range) 693 { 694 unsigned sw_sel = 0; 695 unsigned offset, max_hw_sel; 696 const struct spmi_voltage_range *r = vreg->set_points->range; 697 const struct spmi_voltage_range *end = r + vreg->set_points->count; 698 699 for (; r < end; r++) { 700 if (r == range && range->n_voltages) { 701 /* 702 * hardware selectors between set point min and real 703 * min and between set point max and real max are 704 * invalid so we return an error if they're 705 * programmed into the hardware 706 */ 707 offset = range->set_point_min_uV - range->min_uV; 708 offset /= range->step_uV; 709 if (hw_sel < offset) 710 return -EINVAL; 711 712 max_hw_sel = range->set_point_max_uV - range->min_uV; 713 max_hw_sel /= range->step_uV; 714 if (hw_sel > max_hw_sel) 715 return -EINVAL; 716 717 return sw_sel + hw_sel - offset; 718 } 719 sw_sel += r->n_voltages; 720 } 721 722 return -EINVAL; 723 } 724 725 static const struct spmi_voltage_range * 726 spmi_regulator_find_range(struct spmi_regulator *vreg) 727 { 728 u8 range_sel; 729 const struct spmi_voltage_range *range, *end; 730 731 range = vreg->set_points->range; 732 end = range + vreg->set_points->count; 733 734 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1); 735 736 for (; range < end; range++) 737 if (range->range_sel == range_sel) 738 return range; 739 740 return NULL; 741 } 742 743 static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, 744 int min_uV, int max_uV) 745 { 746 const struct spmi_voltage_range *range; 747 int uV = min_uV; 748 int i, selector; 749 750 range = spmi_regulator_find_range(vreg); 751 if (!range) 752 goto different_range; 753 754 if (uV < range->min_uV && max_uV >= range->min_uV) 755 uV = range->min_uV; 756 757 if (uV < range->min_uV || uV > range->max_uV) { 758 /* Current range doesn't support the requested voltage. */ 759 goto different_range; 760 } 761 762 /* 763 * Force uV to be an allowed set point by applying a ceiling function to 764 * the uV value. 765 */ 766 uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); 767 uV = uV * range->step_uV + range->min_uV; 768 769 if (uV > max_uV) { 770 /* 771 * No set point in the current voltage range is within the 772 * requested min_uV to max_uV range. 773 */ 774 goto different_range; 775 } 776 777 selector = 0; 778 for (i = 0; i < vreg->set_points->count; i++) { 779 if (uV >= vreg->set_points->range[i].set_point_min_uV 780 && uV <= vreg->set_points->range[i].set_point_max_uV) { 781 selector += 782 (uV - vreg->set_points->range[i].set_point_min_uV) 783 / vreg->set_points->range[i].step_uV; 784 break; 785 } 786 787 selector += vreg->set_points->range[i].n_voltages; 788 } 789 790 if (selector >= vreg->set_points->n_voltages) 791 goto different_range; 792 793 return selector; 794 795 different_range: 796 return spmi_regulator_select_voltage(vreg, min_uV, max_uV); 797 } 798 799 static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev, 800 int min_uV, int max_uV) 801 { 802 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 803 804 /* 805 * Favor staying in the current voltage range if possible. This avoids 806 * voltage spikes that occur when changing the voltage range. 807 */ 808 return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV); 809 } 810 811 static int 812 spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector) 813 { 814 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 815 int ret; 816 u8 buf[2]; 817 u8 range_sel, voltage_sel; 818 819 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 820 if (ret) 821 return ret; 822 823 buf[0] = range_sel; 824 buf[1] = voltage_sel; 825 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); 826 } 827 828 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, 829 unsigned selector); 830 831 static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev, 832 unsigned selector) 833 { 834 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 835 u8 buf[2]; 836 int mV; 837 838 mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000; 839 840 buf[0] = mV & 0xff; 841 buf[1] = mV >> 8; 842 return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); 843 } 844 845 static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, 846 unsigned int old_selector, unsigned int new_selector) 847 { 848 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 849 int diff_uV; 850 851 diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) - 852 spmi_regulator_common_list_voltage(rdev, old_selector)); 853 854 return DIV_ROUND_UP(diff_uV, vreg->slew_rate); 855 } 856 857 static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) 858 { 859 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 860 const struct spmi_voltage_range *range; 861 u8 voltage_sel; 862 863 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); 864 865 range = spmi_regulator_find_range(vreg); 866 if (!range) 867 return -EINVAL; 868 869 return spmi_hw_selector_to_sw(vreg, voltage_sel, range); 870 } 871 872 static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev) 873 { 874 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 875 const struct spmi_voltage_range *range; 876 u8 buf[2]; 877 int uV; 878 879 spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); 880 881 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; 882 range = vreg->set_points->range; 883 884 return (uV - range->set_point_min_uV) / range->step_uV; 885 } 886 887 static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev, 888 int min_uV, int max_uV) 889 { 890 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 891 892 return spmi_regulator_select_voltage(vreg, min_uV, max_uV); 893 } 894 895 static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev, 896 unsigned selector) 897 { 898 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 899 u8 sel = selector; 900 901 /* 902 * Certain types of regulators do not have a range select register so 903 * only voltage set register needs to be written. 904 */ 905 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1); 906 } 907 908 static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev) 909 { 910 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 911 u8 selector; 912 int ret; 913 914 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1); 915 if (ret) 916 return ret; 917 918 return selector; 919 } 920 921 static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev, 922 unsigned selector) 923 { 924 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 925 int ret; 926 u8 range_sel, voltage_sel; 927 928 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 929 if (ret) 930 return ret; 931 932 /* 933 * Calculate VSET based on range 934 * In case of range 0: voltage_sel is a 7 bit value, can be written 935 * witout any modification. 936 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to 937 * [011]. 938 */ 939 if (range_sel == 1) 940 voltage_sel |= ULT_SMPS_RANGE_SPLIT; 941 942 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET, 943 voltage_sel, 0xff); 944 } 945 946 static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) 947 { 948 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 949 const struct spmi_voltage_range *range; 950 u8 voltage_sel; 951 952 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); 953 954 range = spmi_regulator_find_range(vreg); 955 if (!range) 956 return -EINVAL; 957 958 if (range->range_sel == 1) 959 voltage_sel &= ~ULT_SMPS_RANGE_SPLIT; 960 961 return spmi_hw_selector_to_sw(vreg, voltage_sel, range); 962 } 963 964 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, 965 unsigned selector) 966 { 967 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 968 int uV = 0; 969 int i; 970 971 if (selector >= vreg->set_points->n_voltages) 972 return 0; 973 974 for (i = 0; i < vreg->set_points->count; i++) { 975 if (selector < vreg->set_points->range[i].n_voltages) { 976 uV = selector * vreg->set_points->range[i].step_uV 977 + vreg->set_points->range[i].set_point_min_uV; 978 break; 979 } 980 981 selector -= vreg->set_points->range[i].n_voltages; 982 } 983 984 return uV; 985 } 986 987 static int 988 spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable) 989 { 990 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 991 u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; 992 u8 val = 0; 993 994 if (enable) 995 val = mask; 996 997 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 998 } 999 1000 static int 1001 spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable) 1002 { 1003 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1004 u8 val; 1005 int ret; 1006 1007 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); 1008 *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; 1009 1010 return ret; 1011 } 1012 1013 static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) 1014 { 1015 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1016 u8 reg; 1017 1018 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1019 1020 reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; 1021 1022 switch (reg) { 1023 case SPMI_COMMON_MODE_HPM_MASK: 1024 return REGULATOR_MODE_NORMAL; 1025 case SPMI_COMMON_MODE_AUTO_MASK: 1026 return REGULATOR_MODE_FAST; 1027 default: 1028 return REGULATOR_MODE_IDLE; 1029 } 1030 } 1031 1032 static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev) 1033 { 1034 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1035 u8 reg; 1036 1037 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1038 1039 switch (reg) { 1040 case SPMI_FTSMPS426_MODE_HPM_MASK: 1041 return REGULATOR_MODE_NORMAL; 1042 case SPMI_FTSMPS426_MODE_AUTO_MASK: 1043 return REGULATOR_MODE_FAST; 1044 default: 1045 return REGULATOR_MODE_IDLE; 1046 } 1047 } 1048 1049 static int 1050 spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) 1051 { 1052 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1053 u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; 1054 u8 val; 1055 1056 switch (mode) { 1057 case REGULATOR_MODE_NORMAL: 1058 val = SPMI_COMMON_MODE_HPM_MASK; 1059 break; 1060 case REGULATOR_MODE_FAST: 1061 val = SPMI_COMMON_MODE_AUTO_MASK; 1062 break; 1063 default: 1064 val = 0; 1065 break; 1066 } 1067 1068 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1069 } 1070 1071 static int 1072 spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode) 1073 { 1074 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1075 u8 mask = SPMI_FTSMPS426_MODE_MASK; 1076 u8 val; 1077 1078 switch (mode) { 1079 case REGULATOR_MODE_NORMAL: 1080 val = SPMI_FTSMPS426_MODE_HPM_MASK; 1081 break; 1082 case REGULATOR_MODE_FAST: 1083 val = SPMI_FTSMPS426_MODE_AUTO_MASK; 1084 break; 1085 case REGULATOR_MODE_IDLE: 1086 val = SPMI_FTSMPS426_MODE_LPM_MASK; 1087 break; 1088 default: 1089 return -EINVAL; 1090 } 1091 1092 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1093 } 1094 1095 static int 1096 spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) 1097 { 1098 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1099 unsigned int mode; 1100 1101 if (load_uA >= vreg->hpm_min_load) 1102 mode = REGULATOR_MODE_NORMAL; 1103 else 1104 mode = REGULATOR_MODE_IDLE; 1105 1106 return spmi_regulator_common_set_mode(rdev, mode); 1107 } 1108 1109 static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) 1110 { 1111 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1112 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; 1113 1114 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, 1115 mask, mask); 1116 } 1117 1118 static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) 1119 { 1120 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1121 unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; 1122 1123 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START, 1124 mask, mask); 1125 } 1126 1127 static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA) 1128 { 1129 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1130 enum spmi_regulator_logical_type type = vreg->logical_type; 1131 unsigned int current_reg; 1132 u8 reg; 1133 u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | 1134 SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; 1135 int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500; 1136 1137 if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST) 1138 current_reg = SPMI_BOOST_REG_CURRENT_LIMIT; 1139 else 1140 current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT; 1141 1142 if (ilim_uA > max || ilim_uA <= 0) 1143 return -EINVAL; 1144 1145 reg = (ilim_uA - 1) / 500; 1146 reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; 1147 1148 return spmi_vreg_update_bits(vreg, current_reg, reg, mask); 1149 } 1150 1151 static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg) 1152 { 1153 int ret; 1154 1155 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, 1156 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); 1157 1158 vreg->vs_enable_time = ktime_get(); 1159 1160 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, 1161 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); 1162 1163 return ret; 1164 } 1165 1166 static void spmi_regulator_vs_ocp_work(struct work_struct *work) 1167 { 1168 struct delayed_work *dwork = to_delayed_work(work); 1169 struct spmi_regulator *vreg 1170 = container_of(dwork, struct spmi_regulator, ocp_work); 1171 1172 spmi_regulator_vs_clear_ocp(vreg); 1173 } 1174 1175 static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) 1176 { 1177 struct spmi_regulator *vreg = data; 1178 ktime_t ocp_irq_time; 1179 s64 ocp_trigger_delay_us; 1180 1181 ocp_irq_time = ktime_get(); 1182 ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time, 1183 vreg->vs_enable_time); 1184 1185 /* 1186 * Reset the OCP count if there is a large delay between switch enable 1187 * and when OCP triggers. This is indicative of a hotplug event as 1188 * opposed to a fault. 1189 */ 1190 if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US) 1191 vreg->ocp_count = 0; 1192 1193 /* Wait for switch output to settle back to 0 V after OCP triggered. */ 1194 udelay(SPMI_VS_OCP_FALL_DELAY_US); 1195 1196 vreg->ocp_count++; 1197 1198 if (vreg->ocp_count == 1) { 1199 /* Immediately clear the over current condition. */ 1200 spmi_regulator_vs_clear_ocp(vreg); 1201 } else if (vreg->ocp_count <= vreg->ocp_max_retries) { 1202 /* Schedule the over current clear task to run later. */ 1203 schedule_delayed_work(&vreg->ocp_work, 1204 msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1); 1205 } else { 1206 dev_err(vreg->dev, 1207 "OCP triggered %d times; no further retries\n", 1208 vreg->ocp_count); 1209 } 1210 1211 return IRQ_HANDLED; 1212 } 1213 1214 #define SAW3_VCTL_DATA_MASK 0xFF 1215 #define SAW3_VCTL_CLEAR_MASK 0x700FF 1216 #define SAW3_AVS_CTL_EN_MASK 0x1 1217 #define SAW3_AVS_CTL_TGGL_MASK 0x8000000 1218 #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 1219 1220 static struct regmap *saw_regmap; 1221 1222 static void spmi_saw_set_vdd(void *data) 1223 { 1224 u32 vctl, data3, avs_ctl, pmic_sts; 1225 bool avs_enabled = false; 1226 unsigned long timeout; 1227 u8 voltage_sel = *(u8 *)data; 1228 1229 regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl); 1230 regmap_read(saw_regmap, SAW3_VCTL, &vctl); 1231 regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3); 1232 1233 /* select the band */ 1234 vctl &= ~SAW3_VCTL_CLEAR_MASK; 1235 vctl |= (u32)voltage_sel; 1236 1237 data3 &= ~SAW3_VCTL_CLEAR_MASK; 1238 data3 |= (u32)voltage_sel; 1239 1240 /* If AVS is enabled, switch it off during the voltage change */ 1241 avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl; 1242 if (avs_enabled) { 1243 avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK; 1244 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); 1245 } 1246 1247 regmap_write(saw_regmap, SAW3_RST, 1); 1248 regmap_write(saw_regmap, SAW3_VCTL, vctl); 1249 regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3); 1250 1251 timeout = jiffies + usecs_to_jiffies(100); 1252 do { 1253 regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts); 1254 pmic_sts &= SAW3_VCTL_DATA_MASK; 1255 if (pmic_sts == (u32)voltage_sel) 1256 break; 1257 1258 cpu_relax(); 1259 1260 } while (time_before(jiffies, timeout)); 1261 1262 /* After successful voltage change, switch the AVS back on */ 1263 if (avs_enabled) { 1264 pmic_sts &= 0x3f; 1265 avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK; 1266 avs_ctl |= ((pmic_sts - 4) << 10); 1267 avs_ctl |= (pmic_sts << 17); 1268 avs_ctl |= SAW3_AVS_CTL_TGGL_MASK; 1269 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); 1270 } 1271 } 1272 1273 static int 1274 spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector) 1275 { 1276 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1277 int ret; 1278 u8 range_sel, voltage_sel; 1279 1280 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 1281 if (ret) 1282 return ret; 1283 1284 if (0 != range_sel) { 1285 dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \ 1286 range_sel, voltage_sel); 1287 return -EINVAL; 1288 } 1289 1290 /* Always do the SAW register writes on the first CPU */ 1291 return smp_call_function_single(0, spmi_saw_set_vdd, \ 1292 &voltage_sel, true); 1293 } 1294 1295 static struct regulator_ops spmi_saw_ops = {}; 1296 1297 static const struct regulator_ops spmi_smps_ops = { 1298 .enable = regulator_enable_regmap, 1299 .disable = regulator_disable_regmap, 1300 .is_enabled = regulator_is_enabled_regmap, 1301 .set_voltage_sel = spmi_regulator_common_set_voltage, 1302 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1303 .get_voltage_sel = spmi_regulator_common_get_voltage, 1304 .map_voltage = spmi_regulator_common_map_voltage, 1305 .list_voltage = spmi_regulator_common_list_voltage, 1306 .set_mode = spmi_regulator_common_set_mode, 1307 .get_mode = spmi_regulator_common_get_mode, 1308 .set_load = spmi_regulator_common_set_load, 1309 .set_pull_down = spmi_regulator_common_set_pull_down, 1310 }; 1311 1312 static const struct regulator_ops spmi_ldo_ops = { 1313 .enable = regulator_enable_regmap, 1314 .disable = regulator_disable_regmap, 1315 .is_enabled = regulator_is_enabled_regmap, 1316 .set_voltage_sel = spmi_regulator_common_set_voltage, 1317 .get_voltage_sel = spmi_regulator_common_get_voltage, 1318 .map_voltage = spmi_regulator_common_map_voltage, 1319 .list_voltage = spmi_regulator_common_list_voltage, 1320 .set_mode = spmi_regulator_common_set_mode, 1321 .get_mode = spmi_regulator_common_get_mode, 1322 .set_load = spmi_regulator_common_set_load, 1323 .set_bypass = spmi_regulator_common_set_bypass, 1324 .get_bypass = spmi_regulator_common_get_bypass, 1325 .set_pull_down = spmi_regulator_common_set_pull_down, 1326 .set_soft_start = spmi_regulator_common_set_soft_start, 1327 }; 1328 1329 static const struct regulator_ops spmi_ln_ldo_ops = { 1330 .enable = regulator_enable_regmap, 1331 .disable = regulator_disable_regmap, 1332 .is_enabled = regulator_is_enabled_regmap, 1333 .set_voltage_sel = spmi_regulator_common_set_voltage, 1334 .get_voltage_sel = spmi_regulator_common_get_voltage, 1335 .map_voltage = spmi_regulator_common_map_voltage, 1336 .list_voltage = spmi_regulator_common_list_voltage, 1337 .set_bypass = spmi_regulator_common_set_bypass, 1338 .get_bypass = spmi_regulator_common_get_bypass, 1339 }; 1340 1341 static const struct regulator_ops spmi_vs_ops = { 1342 .enable = spmi_regulator_vs_enable, 1343 .disable = regulator_disable_regmap, 1344 .is_enabled = regulator_is_enabled_regmap, 1345 .set_pull_down = spmi_regulator_common_set_pull_down, 1346 .set_soft_start = spmi_regulator_common_set_soft_start, 1347 .set_over_current_protection = spmi_regulator_vs_ocp, 1348 .set_mode = spmi_regulator_common_set_mode, 1349 .get_mode = spmi_regulator_common_get_mode, 1350 }; 1351 1352 static const struct regulator_ops spmi_boost_ops = { 1353 .enable = regulator_enable_regmap, 1354 .disable = regulator_disable_regmap, 1355 .is_enabled = regulator_is_enabled_regmap, 1356 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1357 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1358 .map_voltage = spmi_regulator_single_map_voltage, 1359 .list_voltage = spmi_regulator_common_list_voltage, 1360 .set_input_current_limit = spmi_regulator_set_ilim, 1361 }; 1362 1363 static const struct regulator_ops spmi_ftsmps_ops = { 1364 .enable = regulator_enable_regmap, 1365 .disable = regulator_disable_regmap, 1366 .is_enabled = regulator_is_enabled_regmap, 1367 .set_voltage_sel = spmi_regulator_common_set_voltage, 1368 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1369 .get_voltage_sel = spmi_regulator_common_get_voltage, 1370 .map_voltage = spmi_regulator_common_map_voltage, 1371 .list_voltage = spmi_regulator_common_list_voltage, 1372 .set_mode = spmi_regulator_common_set_mode, 1373 .get_mode = spmi_regulator_common_get_mode, 1374 .set_load = spmi_regulator_common_set_load, 1375 .set_pull_down = spmi_regulator_common_set_pull_down, 1376 }; 1377 1378 static const struct regulator_ops spmi_ult_lo_smps_ops = { 1379 .enable = regulator_enable_regmap, 1380 .disable = regulator_disable_regmap, 1381 .is_enabled = regulator_is_enabled_regmap, 1382 .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage, 1383 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1384 .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage, 1385 .list_voltage = spmi_regulator_common_list_voltage, 1386 .set_mode = spmi_regulator_common_set_mode, 1387 .get_mode = spmi_regulator_common_get_mode, 1388 .set_load = spmi_regulator_common_set_load, 1389 .set_pull_down = spmi_regulator_common_set_pull_down, 1390 }; 1391 1392 static const struct regulator_ops spmi_ult_ho_smps_ops = { 1393 .enable = regulator_enable_regmap, 1394 .disable = regulator_disable_regmap, 1395 .is_enabled = regulator_is_enabled_regmap, 1396 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1397 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1398 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1399 .map_voltage = spmi_regulator_single_map_voltage, 1400 .list_voltage = spmi_regulator_common_list_voltage, 1401 .set_mode = spmi_regulator_common_set_mode, 1402 .get_mode = spmi_regulator_common_get_mode, 1403 .set_load = spmi_regulator_common_set_load, 1404 .set_pull_down = spmi_regulator_common_set_pull_down, 1405 }; 1406 1407 static const struct regulator_ops spmi_ult_ldo_ops = { 1408 .enable = regulator_enable_regmap, 1409 .disable = regulator_disable_regmap, 1410 .is_enabled = regulator_is_enabled_regmap, 1411 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1412 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1413 .map_voltage = spmi_regulator_single_map_voltage, 1414 .list_voltage = spmi_regulator_common_list_voltage, 1415 .set_mode = spmi_regulator_common_set_mode, 1416 .get_mode = spmi_regulator_common_get_mode, 1417 .set_load = spmi_regulator_common_set_load, 1418 .set_bypass = spmi_regulator_common_set_bypass, 1419 .get_bypass = spmi_regulator_common_get_bypass, 1420 .set_pull_down = spmi_regulator_common_set_pull_down, 1421 .set_soft_start = spmi_regulator_common_set_soft_start, 1422 }; 1423 1424 static const struct regulator_ops spmi_ftsmps426_ops = { 1425 .enable = regulator_enable_regmap, 1426 .disable = regulator_disable_regmap, 1427 .is_enabled = regulator_is_enabled_regmap, 1428 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1429 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1430 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1431 .map_voltage = spmi_regulator_single_map_voltage, 1432 .list_voltage = spmi_regulator_common_list_voltage, 1433 .set_mode = spmi_regulator_ftsmps426_set_mode, 1434 .get_mode = spmi_regulator_ftsmps426_get_mode, 1435 .set_load = spmi_regulator_common_set_load, 1436 .set_pull_down = spmi_regulator_common_set_pull_down, 1437 }; 1438 1439 static const struct regulator_ops spmi_hfs430_ops = { 1440 .enable = regulator_enable_regmap, 1441 .disable = regulator_disable_regmap, 1442 .is_enabled = regulator_is_enabled_regmap, 1443 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1444 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1445 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1446 .map_voltage = spmi_regulator_single_map_voltage, 1447 .list_voltage = spmi_regulator_common_list_voltage, 1448 .set_mode = spmi_regulator_ftsmps426_set_mode, 1449 .get_mode = spmi_regulator_ftsmps426_get_mode, 1450 }; 1451 1452 /* Maximum possible digital major revision value */ 1453 #define INF 0xFF 1454 1455 static const struct spmi_regulator_mapping supported_regulators[] = { 1456 /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ 1457 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), 1458 SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), 1459 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), 1460 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), 1461 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), 1462 SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000), 1463 SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000), 1464 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000), 1465 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000), 1466 SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000), 1467 SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000), 1468 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000), 1469 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000), 1470 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000), 1471 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000), 1472 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000), 1473 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0), 1474 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000), 1475 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000), 1476 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), 1477 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), 1478 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), 1479 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426, 1480 ht_nldo, 30000), 1481 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426, 1482 ht_nldo, 30000), 1483 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426, 1484 ht_nldo, 30000), 1485 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426, 1486 ht_lvpldo, 10000), 1487 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426, 1488 ht_lvpldo, 10000), 1489 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426, 1490 nldo660, 10000), 1491 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426, 1492 nldo660, 10000), 1493 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426, 1494 pldo660, 10000), 1495 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426, 1496 pldo660, 10000), 1497 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426, 1498 pldo660, 10000), 1499 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426, 1500 ht_lvpldo, 10000), 1501 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426, 1502 ht_lvpldo, 10000), 1503 SPMI_VREG_VS(LV100, 0, INF), 1504 SPMI_VREG_VS(LV300, 0, INF), 1505 SPMI_VREG_VS(MV300, 0, INF), 1506 SPMI_VREG_VS(MV500, 0, INF), 1507 SPMI_VREG_VS(HDMI, 0, INF), 1508 SPMI_VREG_VS(OTG, 0, INF), 1509 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), 1510 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), 1511 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), 1512 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000), 1513 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), 1514 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1515 ult_lo_smps, 100000), 1516 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1517 ult_lo_smps, 100000), 1518 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1519 ult_lo_smps, 100000), 1520 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps, 1521 ult_ho_smps, 100000), 1522 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1523 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1524 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1525 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1526 SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1527 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1528 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1529 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1530 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1531 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1532 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1533 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), 1534 }; 1535 1536 static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) 1537 { 1538 unsigned int n; 1539 struct spmi_voltage_range *range = points->range; 1540 1541 for (; range < points->range + points->count; range++) { 1542 n = 0; 1543 if (range->set_point_max_uV) { 1544 n = range->set_point_max_uV - range->set_point_min_uV; 1545 n = (n / range->step_uV) + 1; 1546 } 1547 range->n_voltages = n; 1548 points->n_voltages += n; 1549 } 1550 } 1551 1552 static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) 1553 { 1554 const struct spmi_regulator_mapping *mapping; 1555 int ret, i; 1556 u32 dig_major_rev; 1557 u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1]; 1558 u8 type, subtype; 1559 1560 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version, 1561 ARRAY_SIZE(version)); 1562 if (ret) { 1563 dev_dbg(vreg->dev, "could not read version registers\n"); 1564 return ret; 1565 } 1566 dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV 1567 - SPMI_COMMON_REG_DIG_MAJOR_REV]; 1568 1569 if (!force_type) { 1570 type = version[SPMI_COMMON_REG_TYPE - 1571 SPMI_COMMON_REG_DIG_MAJOR_REV]; 1572 subtype = version[SPMI_COMMON_REG_SUBTYPE - 1573 SPMI_COMMON_REG_DIG_MAJOR_REV]; 1574 } else { 1575 type = force_type >> 8; 1576 subtype = force_type; 1577 } 1578 1579 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { 1580 mapping = &supported_regulators[i]; 1581 if (mapping->type == type && mapping->subtype == subtype 1582 && mapping->revision_min <= dig_major_rev 1583 && mapping->revision_max >= dig_major_rev) 1584 goto found; 1585 } 1586 1587 dev_err(vreg->dev, 1588 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", 1589 vreg->desc.name, type, subtype, dig_major_rev); 1590 1591 return -ENODEV; 1592 1593 found: 1594 vreg->logical_type = mapping->logical_type; 1595 vreg->set_points = mapping->set_points; 1596 vreg->hpm_min_load = mapping->hpm_min_load; 1597 vreg->desc.ops = mapping->ops; 1598 1599 if (mapping->set_points) { 1600 if (!mapping->set_points->n_voltages) 1601 spmi_calculate_num_voltages(mapping->set_points); 1602 vreg->desc.n_voltages = mapping->set_points->n_voltages; 1603 } 1604 1605 return 0; 1606 } 1607 1608 static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) 1609 { 1610 int ret; 1611 u8 reg = 0; 1612 int step, delay, slew_rate, step_delay; 1613 const struct spmi_voltage_range *range; 1614 1615 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); 1616 if (ret) { 1617 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1618 return ret; 1619 } 1620 1621 range = spmi_regulator_find_range(vreg); 1622 if (!range) 1623 return -EINVAL; 1624 1625 switch (vreg->logical_type) { 1626 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: 1627 step_delay = SPMI_FTSMPS_STEP_DELAY; 1628 break; 1629 default: 1630 step_delay = SPMI_DEFAULT_STEP_DELAY; 1631 break; 1632 } 1633 1634 step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; 1635 step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT; 1636 1637 delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; 1638 delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT; 1639 1640 /* slew_rate has units of uV/us */ 1641 slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step); 1642 slew_rate /= 1000 * (step_delay << delay); 1643 slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM; 1644 slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN; 1645 1646 /* Ensure that the slew rate is greater than 0 */ 1647 vreg->slew_rate = max(slew_rate, 1); 1648 1649 return ret; 1650 } 1651 1652 static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg, 1653 int clock_rate) 1654 { 1655 int ret; 1656 u8 reg = 0; 1657 int delay, slew_rate; 1658 const struct spmi_voltage_range *range = &vreg->set_points->range[0]; 1659 1660 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); 1661 if (ret) { 1662 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1663 return ret; 1664 } 1665 1666 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; 1667 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; 1668 1669 /* slew_rate has units of uV/us */ 1670 slew_rate = clock_rate * range->step_uV; 1671 slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay); 1672 slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM; 1673 slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN; 1674 1675 /* Ensure that the slew rate is greater than 0 */ 1676 vreg->slew_rate = max(slew_rate, 1); 1677 1678 return ret; 1679 } 1680 1681 static int spmi_regulator_init_registers(struct spmi_regulator *vreg, 1682 const struct spmi_regulator_init_data *data) 1683 { 1684 int ret; 1685 enum spmi_regulator_logical_type type; 1686 u8 ctrl_reg[8], reg, mask; 1687 1688 type = vreg->logical_type; 1689 1690 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1691 if (ret) 1692 return ret; 1693 1694 /* Set up enable pin control. */ 1695 if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) { 1696 switch (type) { 1697 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1698 case SPMI_REGULATOR_LOGICAL_TYPE_LDO: 1699 case SPMI_REGULATOR_LOGICAL_TYPE_VS: 1700 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= 1701 ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; 1702 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= 1703 data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; 1704 break; 1705 default: 1706 break; 1707 } 1708 } 1709 1710 /* Set up mode pin control. */ 1711 if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { 1712 switch (type) { 1713 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1714 case SPMI_REGULATOR_LOGICAL_TYPE_LDO: 1715 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1716 ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK; 1717 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1718 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK; 1719 break; 1720 case SPMI_REGULATOR_LOGICAL_TYPE_VS: 1721 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: 1722 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: 1723 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO: 1724 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1725 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; 1726 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1727 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; 1728 break; 1729 default: 1730 break; 1731 } 1732 } 1733 1734 /* Write back any control register values that were modified. */ 1735 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1736 if (ret) 1737 return ret; 1738 1739 /* Set soft start strength and over current protection for VS. */ 1740 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) { 1741 if (data->vs_soft_start_strength 1742 != SPMI_VS_SOFT_START_STR_HW_DEFAULT) { 1743 reg = data->vs_soft_start_strength 1744 & SPMI_VS_SOFT_START_SEL_MASK; 1745 mask = SPMI_VS_SOFT_START_SEL_MASK; 1746 return spmi_vreg_update_bits(vreg, 1747 SPMI_VS_REG_SOFT_START, 1748 reg, mask); 1749 } 1750 } 1751 1752 return 0; 1753 } 1754 1755 static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg, 1756 struct device_node *node, struct spmi_regulator_init_data *data) 1757 { 1758 /* 1759 * Initialize configuration parameters to use hardware default in case 1760 * no value is specified via device tree. 1761 */ 1762 data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT; 1763 data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT; 1764 data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT; 1765 1766 /* These bindings are optional, so it is okay if they aren't found. */ 1767 of_property_read_u32(node, "qcom,ocp-max-retries", 1768 &vreg->ocp_max_retries); 1769 of_property_read_u32(node, "qcom,ocp-retry-delay", 1770 &vreg->ocp_retry_delay_ms); 1771 of_property_read_u32(node, "qcom,pin-ctrl-enable", 1772 &data->pin_ctrl_enable); 1773 of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm); 1774 of_property_read_u32(node, "qcom,vs-soft-start-strength", 1775 &data->vs_soft_start_strength); 1776 } 1777 1778 static unsigned int spmi_regulator_of_map_mode(unsigned int mode) 1779 { 1780 if (mode == 1) 1781 return REGULATOR_MODE_NORMAL; 1782 if (mode == 2) 1783 return REGULATOR_MODE_FAST; 1784 1785 return REGULATOR_MODE_IDLE; 1786 } 1787 1788 static int spmi_regulator_of_parse(struct device_node *node, 1789 const struct regulator_desc *desc, 1790 struct regulator_config *config) 1791 { 1792 struct spmi_regulator_init_data data = { }; 1793 struct spmi_regulator *vreg = config->driver_data; 1794 struct device *dev = config->dev; 1795 int ret; 1796 1797 spmi_regulator_get_dt_config(vreg, node, &data); 1798 1799 if (!vreg->ocp_max_retries) 1800 vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES; 1801 if (!vreg->ocp_retry_delay_ms) 1802 vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS; 1803 1804 ret = spmi_regulator_init_registers(vreg, &data); 1805 if (ret) { 1806 dev_err(dev, "common initialization failed, ret=%d\n", ret); 1807 return ret; 1808 } 1809 1810 switch (vreg->logical_type) { 1811 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: 1812 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: 1813 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: 1814 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1815 ret = spmi_regulator_init_slew_rate(vreg); 1816 if (ret) 1817 return ret; 1818 break; 1819 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426: 1820 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, 1821 SPMI_FTSMPS426_CLOCK_RATE); 1822 if (ret) 1823 return ret; 1824 break; 1825 case SPMI_REGULATOR_LOGICAL_TYPE_HFS430: 1826 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, 1827 SPMI_HFS430_CLOCK_RATE); 1828 if (ret) 1829 return ret; 1830 break; 1831 default: 1832 break; 1833 } 1834 1835 if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS) 1836 vreg->ocp_irq = 0; 1837 1838 if (vreg->ocp_irq) { 1839 ret = devm_request_irq(dev, vreg->ocp_irq, 1840 spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp", 1841 vreg); 1842 if (ret < 0) { 1843 dev_err(dev, "failed to request irq %d, ret=%d\n", 1844 vreg->ocp_irq, ret); 1845 return ret; 1846 } 1847 1848 ret = devm_delayed_work_autocancel(dev, &vreg->ocp_work, 1849 spmi_regulator_vs_ocp_work); 1850 if (ret) 1851 return ret; 1852 } 1853 1854 return 0; 1855 } 1856 1857 static const struct spmi_regulator_data pm8941_regulators[] = { 1858 { "s1", 0x1400, "vdd_s1", }, 1859 { "s2", 0x1700, "vdd_s2", }, 1860 { "s3", 0x1a00, "vdd_s3", }, 1861 { "s4", 0xa000, }, 1862 { "l1", 0x4000, "vdd_l1_l3", }, 1863 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, 1864 { "l3", 0x4200, "vdd_l1_l3", }, 1865 { "l4", 0x4300, "vdd_l4_l11", }, 1866 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, 1867 { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, 1868 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, 1869 { "l8", 0x4700, "vdd_l8_l16_l18_19", }, 1870 { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, 1871 { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, 1872 { "l11", 0x4a00, "vdd_l4_l11", }, 1873 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, 1874 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, 1875 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, 1876 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, 1877 { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, 1878 { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, 1879 { "l18", 0x5100, "vdd_l8_l16_l18_19", }, 1880 { "l19", 0x5200, "vdd_l8_l16_l18_19", }, 1881 { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, 1882 { "l21", 0x5400, "vdd_l21", }, 1883 { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, 1884 { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, 1885 { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, 1886 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, 1887 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, 1888 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, 1889 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, 1890 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, 1891 { } 1892 }; 1893 1894 static const struct spmi_regulator_data pm8841_regulators[] = { 1895 { "s1", 0x1400, "vdd_s1", }, 1896 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 }, 1897 { "s3", 0x1a00, "vdd_s3", }, 1898 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 }, 1899 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 }, 1900 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 }, 1901 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 }, 1902 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 }, 1903 { } 1904 }; 1905 1906 static const struct spmi_regulator_data pm8916_regulators[] = { 1907 { "s1", 0x1400, "vdd_s1", }, 1908 { "s2", 0x1700, "vdd_s2", }, 1909 { "s3", 0x1a00, "vdd_s3", }, 1910 { "s4", 0x1d00, "vdd_s4", }, 1911 { "l1", 0x4000, "vdd_l1_l3", }, 1912 { "l2", 0x4100, "vdd_l2", }, 1913 { "l3", 0x4200, "vdd_l1_l3", }, 1914 { "l4", 0x4300, "vdd_l4_l5_l6", }, 1915 { "l5", 0x4400, "vdd_l4_l5_l6", }, 1916 { "l6", 0x4500, "vdd_l4_l5_l6", }, 1917 { "l7", 0x4600, "vdd_l7", }, 1918 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", }, 1919 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", }, 1920 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", }, 1921 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", }, 1922 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", }, 1923 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", }, 1924 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", }, 1925 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", }, 1926 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, 1927 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, 1928 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, 1929 { } 1930 }; 1931 1932 static const struct spmi_regulator_data pm8950_regulators[] = { 1933 { "s1", 0x1400, "vdd_s1", }, 1934 { "s2", 0x1700, "vdd_s2", }, 1935 { "s3", 0x1a00, "vdd_s3", }, 1936 { "s4", 0x1d00, "vdd_s4", }, 1937 { "s5", 0x2000, "vdd_s5", }, 1938 { "s6", 0x2300, "vdd_s6", }, 1939 { "l1", 0x4000, "vdd_l1_l19", }, 1940 { "l2", 0x4100, "vdd_l2_l23", }, 1941 { "l3", 0x4200, "vdd_l3", }, 1942 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", }, 1943 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", }, 1944 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", }, 1945 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", }, 1946 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", }, 1947 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", }, 1948 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", }, 1949 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", }, 1950 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", }, 1951 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", }, 1952 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", }, 1953 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", }, 1954 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", }, 1955 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", }, 1956 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", }, 1957 { "l19", 0x5200, "vdd_l1_l19", }, 1958 { "l20", 0x5300, "vdd_l20", }, 1959 { "l21", 0x5400, "vdd_l21", }, 1960 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", }, 1961 { "l23", 0x5600, "vdd_l2_l23", }, 1962 { } 1963 }; 1964 1965 static const struct spmi_regulator_data pm8994_regulators[] = { 1966 { "s1", 0x1400, "vdd_s1", }, 1967 { "s2", 0x1700, "vdd_s2", }, 1968 { "s3", 0x1a00, "vdd_s3", }, 1969 { "s4", 0x1d00, "vdd_s4", }, 1970 { "s5", 0x2000, "vdd_s5", }, 1971 { "s6", 0x2300, "vdd_s6", }, 1972 { "s7", 0x2600, "vdd_s7", }, 1973 { "s8", 0x2900, "vdd_s8", }, 1974 { "s9", 0x2c00, "vdd_s9", }, 1975 { "s10", 0x2f00, "vdd_s10", }, 1976 { "s11", 0x3200, "vdd_s11", }, 1977 { "s12", 0x3500, "vdd_s12", }, 1978 { "l1", 0x4000, "vdd_l1", }, 1979 { "l2", 0x4100, "vdd_l2_l26_l28", }, 1980 { "l3", 0x4200, "vdd_l3_l11", }, 1981 { "l4", 0x4300, "vdd_l4_l27_l31", }, 1982 { "l5", 0x4400, "vdd_l5_l7", }, 1983 { "l6", 0x4500, "vdd_l6_l12_l32", }, 1984 { "l7", 0x4600, "vdd_l5_l7", }, 1985 { "l8", 0x4700, "vdd_l8_l16_l30", }, 1986 { "l9", 0x4800, "vdd_l9_l10_l18_l22", }, 1987 { "l10", 0x4900, "vdd_l9_l10_l18_l22", }, 1988 { "l11", 0x4a00, "vdd_l3_l11", }, 1989 { "l12", 0x4b00, "vdd_l6_l12_l32", }, 1990 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", }, 1991 { "l14", 0x4d00, "vdd_l14_l15", }, 1992 { "l15", 0x4e00, "vdd_l14_l15", }, 1993 { "l16", 0x4f00, "vdd_l8_l16_l30", }, 1994 { "l17", 0x5000, "vdd_l17_l29", }, 1995 { "l18", 0x5100, "vdd_l9_l10_l18_l22", }, 1996 { "l19", 0x5200, "vdd_l13_l19_l23_l24", }, 1997 { "l20", 0x5300, "vdd_l20_l21", }, 1998 { "l21", 0x5400, "vdd_l20_l21", }, 1999 { "l22", 0x5500, "vdd_l9_l10_l18_l22", }, 2000 { "l23", 0x5600, "vdd_l13_l19_l23_l24", }, 2001 { "l24", 0x5700, "vdd_l13_l19_l23_l24", }, 2002 { "l25", 0x5800, "vdd_l25", }, 2003 { "l26", 0x5900, "vdd_l2_l26_l28", }, 2004 { "l27", 0x5a00, "vdd_l4_l27_l31", }, 2005 { "l28", 0x5b00, "vdd_l2_l26_l28", }, 2006 { "l29", 0x5c00, "vdd_l17_l29", }, 2007 { "l30", 0x5d00, "vdd_l8_l16_l30", }, 2008 { "l31", 0x5e00, "vdd_l4_l27_l31", }, 2009 { "l32", 0x5f00, "vdd_l6_l12_l32", }, 2010 { "lvs1", 0x8000, "vdd_lvs_1_2", }, 2011 { "lvs2", 0x8100, "vdd_lvs_1_2", }, 2012 { } 2013 }; 2014 2015 static const struct spmi_regulator_data pmi8994_regulators[] = { 2016 { "s1", 0x1400, "vdd_s1", }, 2017 { "s2", 0x1700, "vdd_s2", }, 2018 { "s3", 0x1a00, "vdd_s3", }, 2019 { "l1", 0x4000, "vdd_l1", }, 2020 { } 2021 }; 2022 2023 static const struct spmi_regulator_data pm660_regulators[] = { 2024 { "s1", 0x1400, "vdd_s1", }, 2025 { "s2", 0x1700, "vdd_s2", }, 2026 { "s3", 0x1a00, "vdd_s3", }, 2027 { "s4", 0x1d00, "vdd_s3", }, 2028 { "s5", 0x2000, "vdd_s5", }, 2029 { "s6", 0x2300, "vdd_s6", }, 2030 { "l1", 0x4000, "vdd_l1_l6_l7", }, 2031 { "l2", 0x4100, "vdd_l2_l3", }, 2032 { "l3", 0x4200, "vdd_l2_l3", }, 2033 /* l4 is unaccessible on PM660 */ 2034 { "l5", 0x4400, "vdd_l5", }, 2035 { "l6", 0x4500, "vdd_l1_l6_l7", }, 2036 { "l7", 0x4600, "vdd_l1_l6_l7", }, 2037 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2038 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2039 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2040 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2041 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2042 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2043 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2044 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, 2045 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, 2046 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, 2047 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, 2048 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, 2049 { } 2050 }; 2051 2052 static const struct spmi_regulator_data pm660l_regulators[] = { 2053 { "s1", 0x1400, "vdd_s1", }, 2054 { "s2", 0x1700, "vdd_s2", }, 2055 { "s3", 0x1a00, "vdd_s3", }, 2056 { "s4", 0x1d00, "vdd_s4", }, 2057 { "s5", 0x2000, "vdd_s5", }, 2058 { "l1", 0x4000, "vdd_l1_l9_l10", }, 2059 { "l2", 0x4100, "vdd_l2", }, 2060 { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, 2061 { "l4", 0x4300, "vdd_l4_l6", }, 2062 { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, 2063 { "l6", 0x4500, "vdd_l4_l6", }, 2064 { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, 2065 { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, 2066 { "l9", 0x4800, "vdd_l1_l9_l10", }, 2067 { "l10", 0x4900, "vdd_l1_l9_l10", }, 2068 { } 2069 }; 2070 2071 2072 static const struct spmi_regulator_data pm8004_regulators[] = { 2073 { "s2", 0x1700, "vdd_s2", }, 2074 { "s5", 0x2000, "vdd_s5", }, 2075 { } 2076 }; 2077 2078 static const struct spmi_regulator_data pm8005_regulators[] = { 2079 { "s1", 0x1400, "vdd_s1", }, 2080 { "s2", 0x1700, "vdd_s2", }, 2081 { "s3", 0x1a00, "vdd_s3", }, 2082 { "s4", 0x1d00, "vdd_s4", }, 2083 { } 2084 }; 2085 2086 static const struct spmi_regulator_data pms405_regulators[] = { 2087 { "s3", 0x1a00, "vdd_s3"}, 2088 { } 2089 }; 2090 2091 static const struct of_device_id qcom_spmi_regulator_match[] = { 2092 { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, 2093 { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, 2094 { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, 2095 { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, 2096 { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, 2097 { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators }, 2098 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, 2099 { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, 2100 { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, 2101 { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, 2102 { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, 2103 { } 2104 }; 2105 MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); 2106 2107 static int qcom_spmi_regulator_probe(struct platform_device *pdev) 2108 { 2109 const struct spmi_regulator_data *reg; 2110 const struct spmi_voltage_range *range; 2111 const struct of_device_id *match; 2112 struct regulator_config config = { }; 2113 struct regulator_dev *rdev; 2114 struct spmi_regulator *vreg; 2115 struct regmap *regmap; 2116 const char *name; 2117 struct device *dev = &pdev->dev; 2118 struct device_node *node = pdev->dev.of_node; 2119 struct device_node *syscon, *reg_node; 2120 struct property *reg_prop; 2121 int ret, lenp; 2122 struct list_head *vreg_list; 2123 2124 vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); 2125 if (!vreg_list) 2126 return -ENOMEM; 2127 INIT_LIST_HEAD(vreg_list); 2128 platform_set_drvdata(pdev, vreg_list); 2129 2130 regmap = dev_get_regmap(dev->parent, NULL); 2131 if (!regmap) 2132 return -ENODEV; 2133 2134 match = of_match_device(qcom_spmi_regulator_match, &pdev->dev); 2135 if (!match) 2136 return -ENODEV; 2137 2138 if (of_find_property(node, "qcom,saw-reg", &lenp)) { 2139 syscon = of_parse_phandle(node, "qcom,saw-reg", 0); 2140 saw_regmap = syscon_node_to_regmap(syscon); 2141 of_node_put(syscon); 2142 if (IS_ERR(saw_regmap)) 2143 dev_err(dev, "ERROR reading SAW regmap\n"); 2144 } 2145 2146 for (reg = match->data; reg->name; reg++) { 2147 2148 if (saw_regmap) { 2149 reg_node = of_get_child_by_name(node, reg->name); 2150 reg_prop = of_find_property(reg_node, "qcom,saw-slave", 2151 &lenp); 2152 of_node_put(reg_node); 2153 if (reg_prop) 2154 continue; 2155 } 2156 2157 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); 2158 if (!vreg) 2159 return -ENOMEM; 2160 2161 vreg->dev = dev; 2162 vreg->base = reg->base; 2163 vreg->regmap = regmap; 2164 if (reg->ocp) { 2165 vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); 2166 if (vreg->ocp_irq < 0) 2167 return vreg->ocp_irq; 2168 } 2169 vreg->desc.id = -1; 2170 vreg->desc.owner = THIS_MODULE; 2171 vreg->desc.type = REGULATOR_VOLTAGE; 2172 vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; 2173 vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK; 2174 vreg->desc.enable_val = SPMI_COMMON_ENABLE; 2175 vreg->desc.name = name = reg->name; 2176 vreg->desc.supply_name = reg->supply; 2177 vreg->desc.of_match = reg->name; 2178 vreg->desc.of_parse_cb = spmi_regulator_of_parse; 2179 vreg->desc.of_map_mode = spmi_regulator_of_map_mode; 2180 2181 ret = spmi_regulator_match(vreg, reg->force_type); 2182 if (ret) 2183 continue; 2184 2185 if (saw_regmap) { 2186 reg_node = of_get_child_by_name(node, reg->name); 2187 reg_prop = of_find_property(reg_node, "qcom,saw-leader", 2188 &lenp); 2189 of_node_put(reg_node); 2190 if (reg_prop) { 2191 spmi_saw_ops = *(vreg->desc.ops); 2192 spmi_saw_ops.set_voltage_sel = 2193 spmi_regulator_saw_set_voltage; 2194 vreg->desc.ops = &spmi_saw_ops; 2195 } 2196 } 2197 2198 if (vreg->set_points && vreg->set_points->count == 1) { 2199 /* since there is only one range */ 2200 range = vreg->set_points->range; 2201 vreg->desc.uV_step = range->step_uV; 2202 } 2203 2204 config.dev = dev; 2205 config.driver_data = vreg; 2206 config.regmap = regmap; 2207 rdev = devm_regulator_register(dev, &vreg->desc, &config); 2208 if (IS_ERR(rdev)) { 2209 dev_err(dev, "failed to register %s\n", name); 2210 return PTR_ERR(rdev); 2211 } 2212 2213 INIT_LIST_HEAD(&vreg->node); 2214 list_add(&vreg->node, vreg_list); 2215 } 2216 2217 return 0; 2218 } 2219 2220 static struct platform_driver qcom_spmi_regulator_driver = { 2221 .driver = { 2222 .name = "qcom-spmi-regulator", 2223 .of_match_table = qcom_spmi_regulator_match, 2224 }, 2225 .probe = qcom_spmi_regulator_probe, 2226 }; 2227 module_platform_driver(qcom_spmi_regulator_driver); 2228 2229 MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver"); 2230 MODULE_LICENSE("GPL v2"); 2231 MODULE_ALIAS("platform:qcom-spmi-regulator"); 2232