1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/interrupt.h> 11 #include <linux/bitops.h> 12 #include <linux/slab.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ktime.h> 17 #include <linux/regulator/driver.h> 18 #include <linux/regmap.h> 19 #include <linux/list.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/io.h> 22 23 /* Pin control enable input pins. */ 24 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01 26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02 27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04 28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08 29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10 30 31 /* Pin control high power mode input pins. */ 32 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00 33 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01 34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02 35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04 36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08 37 #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10 38 #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20 39 40 /* 41 * Used with enable parameters to specify that hardware default register values 42 * should be left unaltered. 43 */ 44 #define SPMI_REGULATOR_USE_HW_DEFAULT 2 45 46 /* Soft start strength of a voltage switch type regulator */ 47 enum spmi_vs_soft_start_str { 48 SPMI_VS_SOFT_START_STR_0P05_UA = 0, 49 SPMI_VS_SOFT_START_STR_0P25_UA, 50 SPMI_VS_SOFT_START_STR_0P55_UA, 51 SPMI_VS_SOFT_START_STR_0P75_UA, 52 SPMI_VS_SOFT_START_STR_HW_DEFAULT, 53 }; 54 55 /** 56 * struct spmi_regulator_init_data - spmi-regulator initialization data 57 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be 58 * used to enable the regulator, if any 59 * Value should be an ORing of 60 * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If 61 * the bit specified by 62 * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is 63 * set, then pin control enable hardware registers 64 * will not be modified. 65 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be 66 * used to force the regulator into high power 67 * mode, if any 68 * Value should be an ORing of 69 * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If 70 * the bit specified by 71 * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is 72 * set, then pin control mode hardware registers 73 * will not be modified. 74 * @vs_soft_start_strength: This parameter sets the soft start strength for 75 * voltage switch type regulators. Its value 76 * should be one of SPMI_VS_SOFT_START_STR_*. If 77 * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT, 78 * then the soft start strength will be left at its 79 * default hardware value. 80 */ 81 struct spmi_regulator_init_data { 82 unsigned pin_ctrl_enable; 83 unsigned pin_ctrl_hpm; 84 enum spmi_vs_soft_start_str vs_soft_start_strength; 85 }; 86 87 /* These types correspond to unique register layouts. */ 88 enum spmi_regulator_logical_type { 89 SPMI_REGULATOR_LOGICAL_TYPE_SMPS, 90 SPMI_REGULATOR_LOGICAL_TYPE_LDO, 91 SPMI_REGULATOR_LOGICAL_TYPE_VS, 92 SPMI_REGULATOR_LOGICAL_TYPE_BOOST, 93 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS, 94 SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP, 95 SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO, 96 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, 97 SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, 98 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, 99 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, 100 SPMI_REGULATOR_LOGICAL_TYPE_HFS430, 101 }; 102 103 enum spmi_regulator_type { 104 SPMI_REGULATOR_TYPE_BUCK = 0x03, 105 SPMI_REGULATOR_TYPE_LDO = 0x04, 106 SPMI_REGULATOR_TYPE_VS = 0x05, 107 SPMI_REGULATOR_TYPE_BOOST = 0x1b, 108 SPMI_REGULATOR_TYPE_FTS = 0x1c, 109 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f, 110 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21, 111 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22, 112 }; 113 114 enum spmi_regulator_subtype { 115 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08, 116 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09, 117 SPMI_REGULATOR_SUBTYPE_N50 = 0x01, 118 SPMI_REGULATOR_SUBTYPE_N150 = 0x02, 119 SPMI_REGULATOR_SUBTYPE_N300 = 0x03, 120 SPMI_REGULATOR_SUBTYPE_N600 = 0x04, 121 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05, 122 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06, 123 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07, 124 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14, 125 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15, 126 SPMI_REGULATOR_SUBTYPE_P50 = 0x08, 127 SPMI_REGULATOR_SUBTYPE_P150 = 0x09, 128 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a, 129 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b, 130 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c, 131 SPMI_REGULATOR_SUBTYPE_LN = 0x10, 132 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28, 133 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29, 134 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a, 135 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b, 136 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c, 137 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d, 138 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30, 139 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31, 140 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32, 141 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b, 142 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c, 143 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42, 144 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43, 145 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46, 146 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47, 147 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49, 148 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d, 149 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f, 150 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01, 151 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02, 152 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08, 153 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09, 154 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10, 155 SPMI_REGULATOR_SUBTYPE_OTG = 0x11, 156 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, 157 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, 158 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, 159 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a, 160 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, 161 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, 162 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, 163 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, 164 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, 165 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, 166 }; 167 168 enum spmi_common_regulator_registers { 169 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01, 170 SPMI_COMMON_REG_TYPE = 0x04, 171 SPMI_COMMON_REG_SUBTYPE = 0x05, 172 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40, 173 SPMI_COMMON_REG_VOLTAGE_SET = 0x41, 174 SPMI_COMMON_REG_MODE = 0x45, 175 SPMI_COMMON_REG_ENABLE = 0x46, 176 SPMI_COMMON_REG_PULL_DOWN = 0x48, 177 SPMI_COMMON_REG_SOFT_START = 0x4c, 178 SPMI_COMMON_REG_STEP_CTRL = 0x61, 179 }; 180 181 /* 182 * Second common register layout used by newer devices starting with ftsmps426 183 * Note that some of the registers from the first common layout remain 184 * unchanged and their definition is not duplicated. 185 */ 186 enum spmi_ftsmps426_regulator_registers { 187 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40, 188 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41, 189 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68, 190 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, 191 }; 192 193 enum spmi_vs_registers { 194 SPMI_VS_REG_OCP = 0x4a, 195 SPMI_VS_REG_SOFT_START = 0x4c, 196 }; 197 198 enum spmi_boost_registers { 199 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a, 200 }; 201 202 enum spmi_boost_byp_registers { 203 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, 204 }; 205 206 enum spmi_saw3_registers { 207 SAW3_SECURE = 0x00, 208 SAW3_ID = 0x04, 209 SAW3_SPM_STS = 0x0C, 210 SAW3_AVS_STS = 0x10, 211 SAW3_PMIC_STS = 0x14, 212 SAW3_RST = 0x18, 213 SAW3_VCTL = 0x1C, 214 SAW3_AVS_CTL = 0x20, 215 SAW3_AVS_LIMIT = 0x24, 216 SAW3_AVS_DLY = 0x28, 217 SAW3_AVS_HYSTERESIS = 0x2C, 218 SAW3_SPM_STS2 = 0x38, 219 SAW3_SPM_PMIC_DATA_3 = 0x4C, 220 SAW3_VERSION = 0xFD0, 221 }; 222 223 /* Used for indexing into ctrl_reg. These are offets from 0x40 */ 224 enum spmi_common_control_register_index { 225 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, 226 SPMI_COMMON_IDX_VOLTAGE_SET = 1, 227 SPMI_COMMON_IDX_MODE = 5, 228 SPMI_COMMON_IDX_ENABLE = 6, 229 }; 230 231 /* Common regulator control register layout */ 232 #define SPMI_COMMON_ENABLE_MASK 0x80 233 #define SPMI_COMMON_ENABLE 0x80 234 #define SPMI_COMMON_DISABLE 0x00 235 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08 236 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04 237 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02 238 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01 239 #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f 240 241 /* Common regulator mode register layout */ 242 #define SPMI_COMMON_MODE_HPM_MASK 0x80 243 #define SPMI_COMMON_MODE_AUTO_MASK 0x40 244 #define SPMI_COMMON_MODE_BYPASS_MASK 0x20 245 #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10 246 #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08 247 #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04 248 #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02 249 #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 250 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f 251 252 #define SPMI_FTSMPS426_MODE_BYPASS_MASK 3 253 #define SPMI_FTSMPS426_MODE_RETENTION_MASK 4 254 #define SPMI_FTSMPS426_MODE_LPM_MASK 5 255 #define SPMI_FTSMPS426_MODE_AUTO_MASK 6 256 #define SPMI_FTSMPS426_MODE_HPM_MASK 7 257 258 #define SPMI_FTSMPS426_MODE_MASK 0x07 259 260 /* Common regulator pull down control register layout */ 261 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 262 263 /* LDO regulator current limit control register layout */ 264 #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80 265 266 /* LDO regulator soft start control register layout */ 267 #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80 268 269 /* VS regulator over current protection control register layout */ 270 #define SPMI_VS_OCP_OVERRIDE 0x01 271 #define SPMI_VS_OCP_NO_OVERRIDE 0x00 272 273 /* VS regulator soft start control register layout */ 274 #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80 275 #define SPMI_VS_SOFT_START_SEL_MASK 0x03 276 277 /* Boost regulator current limit control register layout */ 278 #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80 279 #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07 280 281 #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10 282 #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30 283 #define SPMI_VS_OCP_FALL_DELAY_US 90 284 #define SPMI_VS_OCP_FAULT_DELAY_US 20000 285 286 #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18 287 #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3 288 #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 289 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 290 291 /* Clock rate in kHz of the FTSMPS regulator reference clock. */ 292 #define SPMI_FTSMPS_CLOCK_RATE 19200 293 294 /* Minimum voltage stepper delay for each step. */ 295 #define SPMI_FTSMPS_STEP_DELAY 8 296 #define SPMI_DEFAULT_STEP_DELAY 20 297 298 /* 299 * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to 300 * adjust the step rate in order to account for oscillator variance. 301 */ 302 #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 303 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 304 305 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 306 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 307 308 /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */ 309 #define SPMI_FTSMPS426_CLOCK_RATE 4800 310 311 #define SPMI_HFS430_CLOCK_RATE 1600 312 313 /* Minimum voltage stepper delay for each step. */ 314 #define SPMI_FTSMPS426_STEP_DELAY 2 315 316 /* 317 * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is 318 * used to adjust the step rate in order to account for oscillator variance. 319 */ 320 #define SPMI_FTSMPS426_STEP_MARGIN_NUM 10 321 #define SPMI_FTSMPS426_STEP_MARGIN_DEN 11 322 323 324 /* VSET value to decide the range of ULT SMPS */ 325 #define ULT_SMPS_RANGE_SPLIT 0x60 326 327 /** 328 * struct spmi_voltage_range - regulator set point voltage mapping description 329 * @min_uV: Minimum programmable output voltage resulting from 330 * set point register value 0x00 331 * @max_uV: Maximum programmable output voltage 332 * @step_uV: Output voltage increase resulting from the set point 333 * register value increasing by 1 334 * @set_point_min_uV: Minimum allowed voltage 335 * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order 336 * to pick which range should be used in the case of 337 * overlapping set points. 338 * @n_voltages: Number of preferred voltage set points present in this 339 * range 340 * @range_sel: Voltage range register value corresponding to this range 341 * 342 * The following relationships must be true for the values used in this struct: 343 * (max_uV - min_uV) % step_uV == 0 344 * (set_point_min_uV - min_uV) % step_uV == 0* 345 * (set_point_max_uV - min_uV) % step_uV == 0* 346 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1 347 * 348 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to 349 * specify that the voltage range has meaning, but is not preferred. 350 */ 351 struct spmi_voltage_range { 352 int min_uV; 353 int max_uV; 354 int step_uV; 355 int set_point_min_uV; 356 int set_point_max_uV; 357 unsigned n_voltages; 358 u8 range_sel; 359 }; 360 361 /* 362 * The ranges specified in the spmi_voltage_set_points struct must be listed 363 * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV. 364 */ 365 struct spmi_voltage_set_points { 366 struct spmi_voltage_range *range; 367 int count; 368 unsigned n_voltages; 369 }; 370 371 struct spmi_regulator { 372 struct regulator_desc desc; 373 struct device *dev; 374 struct delayed_work ocp_work; 375 struct regmap *regmap; 376 struct spmi_voltage_set_points *set_points; 377 enum spmi_regulator_logical_type logical_type; 378 int ocp_irq; 379 int ocp_count; 380 int ocp_max_retries; 381 int ocp_retry_delay_ms; 382 int hpm_min_load; 383 int slew_rate; 384 ktime_t vs_enable_time; 385 u16 base; 386 struct list_head node; 387 }; 388 389 struct spmi_regulator_mapping { 390 enum spmi_regulator_type type; 391 enum spmi_regulator_subtype subtype; 392 enum spmi_regulator_logical_type logical_type; 393 u32 revision_min; 394 u32 revision_max; 395 const struct regulator_ops *ops; 396 struct spmi_voltage_set_points *set_points; 397 int hpm_min_load; 398 }; 399 400 struct spmi_regulator_data { 401 const char *name; 402 u16 base; 403 const char *supply; 404 const char *ocp; 405 u16 force_type; 406 }; 407 408 #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \ 409 _logical_type, _ops_val, _set_points_val, _hpm_min_load) \ 410 { \ 411 .type = SPMI_REGULATOR_TYPE_##_type, \ 412 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ 413 .revision_min = _dig_major_min, \ 414 .revision_max = _dig_major_max, \ 415 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \ 416 .ops = &spmi_##_ops_val##_ops, \ 417 .set_points = &_set_points_val##_set_points, \ 418 .hpm_min_load = _hpm_min_load, \ 419 } 420 421 #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \ 422 { \ 423 .type = SPMI_REGULATOR_TYPE_VS, \ 424 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ 425 .revision_min = _dig_major_min, \ 426 .revision_max = _dig_major_max, \ 427 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \ 428 .ops = &spmi_vs_ops, \ 429 } 430 431 #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \ 432 _set_point_max_uV, _max_uV, _step_uV) \ 433 { \ 434 .min_uV = _min_uV, \ 435 .max_uV = _max_uV, \ 436 .set_point_min_uV = _set_point_min_uV, \ 437 .set_point_max_uV = _set_point_max_uV, \ 438 .step_uV = _step_uV, \ 439 .range_sel = _range_sel, \ 440 } 441 442 #define DEFINE_SPMI_SET_POINTS(name) \ 443 struct spmi_voltage_set_points name##_set_points = { \ 444 .range = name##_ranges, \ 445 .count = ARRAY_SIZE(name##_ranges), \ 446 } 447 448 /* 449 * These tables contain the physically available PMIC regulator voltage setpoint 450 * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed 451 * to ensure that the setpoints available to software are monotonically 452 * increasing and unique. The set_voltage callback functions expect these 453 * properties to hold. 454 */ 455 static struct spmi_voltage_range pldo_ranges[] = { 456 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), 457 SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000), 458 SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000), 459 }; 460 461 static struct spmi_voltage_range nldo1_ranges[] = { 462 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), 463 }; 464 465 static struct spmi_voltage_range nldo2_ranges[] = { 466 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500), 467 SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250), 468 SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500), 469 }; 470 471 static struct spmi_voltage_range nldo3_ranges[] = { 472 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), 473 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500), 474 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500), 475 }; 476 477 static struct spmi_voltage_range ln_ldo_ranges[] = { 478 SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000), 479 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000), 480 }; 481 482 static struct spmi_voltage_range smps_ranges[] = { 483 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), 484 SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), 485 }; 486 487 static struct spmi_voltage_range ftsmps_ranges[] = { 488 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), 489 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), 490 }; 491 492 static struct spmi_voltage_range ftsmps2p5_ranges[] = { 493 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000), 494 SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), 495 }; 496 497 static struct spmi_voltage_range ftsmps426_ranges[] = { 498 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000), 499 }; 500 501 static struct spmi_voltage_range boost_ranges[] = { 502 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), 503 }; 504 505 static struct spmi_voltage_range boost_byp_ranges[] = { 506 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000), 507 }; 508 509 static struct spmi_voltage_range ult_lo_smps_ranges[] = { 510 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), 511 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000), 512 }; 513 514 static struct spmi_voltage_range ult_ho_smps_ranges[] = { 515 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000), 516 }; 517 518 static struct spmi_voltage_range ult_nldo_ranges[] = { 519 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), 520 }; 521 522 static struct spmi_voltage_range ult_pldo_ranges[] = { 523 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), 524 }; 525 526 static struct spmi_voltage_range pldo660_ranges[] = { 527 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000), 528 }; 529 530 static struct spmi_voltage_range nldo660_ranges[] = { 531 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), 532 }; 533 534 static struct spmi_voltage_range ht_lvpldo_ranges[] = { 535 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000), 536 }; 537 538 static struct spmi_voltage_range ht_nldo_ranges[] = { 539 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000), 540 }; 541 542 static struct spmi_voltage_range hfs430_ranges[] = { 543 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), 544 }; 545 546 static DEFINE_SPMI_SET_POINTS(pldo); 547 static DEFINE_SPMI_SET_POINTS(nldo1); 548 static DEFINE_SPMI_SET_POINTS(nldo2); 549 static DEFINE_SPMI_SET_POINTS(nldo3); 550 static DEFINE_SPMI_SET_POINTS(ln_ldo); 551 static DEFINE_SPMI_SET_POINTS(smps); 552 static DEFINE_SPMI_SET_POINTS(ftsmps); 553 static DEFINE_SPMI_SET_POINTS(ftsmps2p5); 554 static DEFINE_SPMI_SET_POINTS(ftsmps426); 555 static DEFINE_SPMI_SET_POINTS(boost); 556 static DEFINE_SPMI_SET_POINTS(boost_byp); 557 static DEFINE_SPMI_SET_POINTS(ult_lo_smps); 558 static DEFINE_SPMI_SET_POINTS(ult_ho_smps); 559 static DEFINE_SPMI_SET_POINTS(ult_nldo); 560 static DEFINE_SPMI_SET_POINTS(ult_pldo); 561 static DEFINE_SPMI_SET_POINTS(pldo660); 562 static DEFINE_SPMI_SET_POINTS(nldo660); 563 static DEFINE_SPMI_SET_POINTS(ht_lvpldo); 564 static DEFINE_SPMI_SET_POINTS(ht_nldo); 565 static DEFINE_SPMI_SET_POINTS(hfs430); 566 567 static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, 568 int len) 569 { 570 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); 571 } 572 573 static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr, 574 u8 *buf, int len) 575 { 576 return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); 577 } 578 579 static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, 580 u8 mask) 581 { 582 return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); 583 } 584 585 static int spmi_regulator_vs_enable(struct regulator_dev *rdev) 586 { 587 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 588 589 if (vreg->ocp_irq) { 590 vreg->ocp_count = 0; 591 vreg->vs_enable_time = ktime_get(); 592 } 593 594 return regulator_enable_regmap(rdev); 595 } 596 597 static int spmi_regulator_vs_ocp(struct regulator_dev *rdev) 598 { 599 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 600 u8 reg = SPMI_VS_OCP_OVERRIDE; 601 602 return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1); 603 } 604 605 static int spmi_regulator_select_voltage(struct spmi_regulator *vreg, 606 int min_uV, int max_uV) 607 { 608 const struct spmi_voltage_range *range; 609 int uV = min_uV; 610 int lim_min_uV, lim_max_uV, i, range_id, range_max_uV; 611 int selector, voltage_sel; 612 613 /* Check if request voltage is outside of physically settable range. */ 614 lim_min_uV = vreg->set_points->range[0].set_point_min_uV; 615 lim_max_uV = 616 vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV; 617 618 if (uV < lim_min_uV && max_uV >= lim_min_uV) 619 uV = lim_min_uV; 620 621 if (uV < lim_min_uV || uV > lim_max_uV) { 622 dev_err(vreg->dev, 623 "request v=[%d, %d] is outside possible v=[%d, %d]\n", 624 min_uV, max_uV, lim_min_uV, lim_max_uV); 625 return -EINVAL; 626 } 627 628 /* Find the range which uV is inside of. */ 629 for (i = vreg->set_points->count - 1; i > 0; i--) { 630 range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV; 631 if (uV > range_max_uV && range_max_uV > 0) 632 break; 633 } 634 635 range_id = i; 636 range = &vreg->set_points->range[range_id]; 637 638 /* 639 * Force uV to be an allowed set point by applying a ceiling function to 640 * the uV value. 641 */ 642 voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); 643 uV = voltage_sel * range->step_uV + range->min_uV; 644 645 if (uV > max_uV) { 646 dev_err(vreg->dev, 647 "request v=[%d, %d] cannot be met by any set point; " 648 "next set point: %d\n", 649 min_uV, max_uV, uV); 650 return -EINVAL; 651 } 652 653 selector = 0; 654 for (i = 0; i < range_id; i++) 655 selector += vreg->set_points->range[i].n_voltages; 656 selector += (uV - range->set_point_min_uV) / range->step_uV; 657 658 return selector; 659 } 660 661 static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg, 662 unsigned selector, u8 *range_sel, 663 u8 *voltage_sel) 664 { 665 const struct spmi_voltage_range *range, *end; 666 unsigned offset; 667 668 range = vreg->set_points->range; 669 end = range + vreg->set_points->count; 670 671 for (; range < end; range++) { 672 if (selector < range->n_voltages) { 673 /* 674 * hardware selectors between set point min and real 675 * min are invalid so we ignore them 676 */ 677 offset = range->set_point_min_uV - range->min_uV; 678 offset /= range->step_uV; 679 *voltage_sel = selector + offset; 680 *range_sel = range->range_sel; 681 return 0; 682 } 683 684 selector -= range->n_voltages; 685 } 686 687 return -EINVAL; 688 } 689 690 static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel, 691 const struct spmi_voltage_range *range) 692 { 693 unsigned sw_sel = 0; 694 unsigned offset, max_hw_sel; 695 const struct spmi_voltage_range *r = vreg->set_points->range; 696 const struct spmi_voltage_range *end = r + vreg->set_points->count; 697 698 for (; r < end; r++) { 699 if (r == range && range->n_voltages) { 700 /* 701 * hardware selectors between set point min and real 702 * min and between set point max and real max are 703 * invalid so we return an error if they're 704 * programmed into the hardware 705 */ 706 offset = range->set_point_min_uV - range->min_uV; 707 offset /= range->step_uV; 708 if (hw_sel < offset) 709 return -EINVAL; 710 711 max_hw_sel = range->set_point_max_uV - range->min_uV; 712 max_hw_sel /= range->step_uV; 713 if (hw_sel > max_hw_sel) 714 return -EINVAL; 715 716 return sw_sel + hw_sel - offset; 717 } 718 sw_sel += r->n_voltages; 719 } 720 721 return -EINVAL; 722 } 723 724 static const struct spmi_voltage_range * 725 spmi_regulator_find_range(struct spmi_regulator *vreg) 726 { 727 u8 range_sel; 728 const struct spmi_voltage_range *range, *end; 729 730 range = vreg->set_points->range; 731 end = range + vreg->set_points->count; 732 733 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1); 734 735 for (; range < end; range++) 736 if (range->range_sel == range_sel) 737 return range; 738 739 return NULL; 740 } 741 742 static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, 743 int min_uV, int max_uV) 744 { 745 const struct spmi_voltage_range *range; 746 int uV = min_uV; 747 int i, selector; 748 749 range = spmi_regulator_find_range(vreg); 750 if (!range) 751 goto different_range; 752 753 if (uV < range->min_uV && max_uV >= range->min_uV) 754 uV = range->min_uV; 755 756 if (uV < range->min_uV || uV > range->max_uV) { 757 /* Current range doesn't support the requested voltage. */ 758 goto different_range; 759 } 760 761 /* 762 * Force uV to be an allowed set point by applying a ceiling function to 763 * the uV value. 764 */ 765 uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); 766 uV = uV * range->step_uV + range->min_uV; 767 768 if (uV > max_uV) { 769 /* 770 * No set point in the current voltage range is within the 771 * requested min_uV to max_uV range. 772 */ 773 goto different_range; 774 } 775 776 selector = 0; 777 for (i = 0; i < vreg->set_points->count; i++) { 778 if (uV >= vreg->set_points->range[i].set_point_min_uV 779 && uV <= vreg->set_points->range[i].set_point_max_uV) { 780 selector += 781 (uV - vreg->set_points->range[i].set_point_min_uV) 782 / vreg->set_points->range[i].step_uV; 783 break; 784 } 785 786 selector += vreg->set_points->range[i].n_voltages; 787 } 788 789 if (selector >= vreg->set_points->n_voltages) 790 goto different_range; 791 792 return selector; 793 794 different_range: 795 return spmi_regulator_select_voltage(vreg, min_uV, max_uV); 796 } 797 798 static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev, 799 int min_uV, int max_uV) 800 { 801 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 802 803 /* 804 * Favor staying in the current voltage range if possible. This avoids 805 * voltage spikes that occur when changing the voltage range. 806 */ 807 return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV); 808 } 809 810 static int 811 spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector) 812 { 813 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 814 int ret; 815 u8 buf[2]; 816 u8 range_sel, voltage_sel; 817 818 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 819 if (ret) 820 return ret; 821 822 buf[0] = range_sel; 823 buf[1] = voltage_sel; 824 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); 825 } 826 827 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, 828 unsigned selector); 829 830 static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev, 831 unsigned selector) 832 { 833 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 834 u8 buf[2]; 835 int mV; 836 837 mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000; 838 839 buf[0] = mV & 0xff; 840 buf[1] = mV >> 8; 841 return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); 842 } 843 844 static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, 845 unsigned int old_selector, unsigned int new_selector) 846 { 847 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 848 int diff_uV; 849 850 diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) - 851 spmi_regulator_common_list_voltage(rdev, old_selector)); 852 853 return DIV_ROUND_UP(diff_uV, vreg->slew_rate); 854 } 855 856 static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) 857 { 858 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 859 const struct spmi_voltage_range *range; 860 u8 voltage_sel; 861 862 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); 863 864 range = spmi_regulator_find_range(vreg); 865 if (!range) 866 return -EINVAL; 867 868 return spmi_hw_selector_to_sw(vreg, voltage_sel, range); 869 } 870 871 static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev) 872 { 873 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 874 const struct spmi_voltage_range *range; 875 u8 buf[2]; 876 int uV; 877 878 spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); 879 880 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; 881 range = vreg->set_points->range; 882 883 return (uV - range->set_point_min_uV) / range->step_uV; 884 } 885 886 static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev, 887 int min_uV, int max_uV) 888 { 889 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 890 891 return spmi_regulator_select_voltage(vreg, min_uV, max_uV); 892 } 893 894 static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev, 895 unsigned selector) 896 { 897 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 898 u8 sel = selector; 899 900 /* 901 * Certain types of regulators do not have a range select register so 902 * only voltage set register needs to be written. 903 */ 904 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1); 905 } 906 907 static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev) 908 { 909 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 910 u8 selector; 911 int ret; 912 913 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1); 914 if (ret) 915 return ret; 916 917 return selector; 918 } 919 920 static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev, 921 unsigned selector) 922 { 923 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 924 int ret; 925 u8 range_sel, voltage_sel; 926 927 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 928 if (ret) 929 return ret; 930 931 /* 932 * Calculate VSET based on range 933 * In case of range 0: voltage_sel is a 7 bit value, can be written 934 * witout any modification. 935 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to 936 * [011]. 937 */ 938 if (range_sel == 1) 939 voltage_sel |= ULT_SMPS_RANGE_SPLIT; 940 941 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET, 942 voltage_sel, 0xff); 943 } 944 945 static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) 946 { 947 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 948 const struct spmi_voltage_range *range; 949 u8 voltage_sel; 950 951 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); 952 953 range = spmi_regulator_find_range(vreg); 954 if (!range) 955 return -EINVAL; 956 957 if (range->range_sel == 1) 958 voltage_sel &= ~ULT_SMPS_RANGE_SPLIT; 959 960 return spmi_hw_selector_to_sw(vreg, voltage_sel, range); 961 } 962 963 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, 964 unsigned selector) 965 { 966 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 967 int uV = 0; 968 int i; 969 970 if (selector >= vreg->set_points->n_voltages) 971 return 0; 972 973 for (i = 0; i < vreg->set_points->count; i++) { 974 if (selector < vreg->set_points->range[i].n_voltages) { 975 uV = selector * vreg->set_points->range[i].step_uV 976 + vreg->set_points->range[i].set_point_min_uV; 977 break; 978 } 979 980 selector -= vreg->set_points->range[i].n_voltages; 981 } 982 983 return uV; 984 } 985 986 static int 987 spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable) 988 { 989 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 990 u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; 991 u8 val = 0; 992 993 if (enable) 994 val = mask; 995 996 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 997 } 998 999 static int 1000 spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable) 1001 { 1002 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1003 u8 val; 1004 int ret; 1005 1006 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); 1007 *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; 1008 1009 return ret; 1010 } 1011 1012 static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) 1013 { 1014 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1015 u8 reg; 1016 1017 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1018 1019 reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; 1020 1021 switch (reg) { 1022 case SPMI_COMMON_MODE_HPM_MASK: 1023 return REGULATOR_MODE_NORMAL; 1024 case SPMI_COMMON_MODE_AUTO_MASK: 1025 return REGULATOR_MODE_FAST; 1026 default: 1027 return REGULATOR_MODE_IDLE; 1028 } 1029 } 1030 1031 static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev) 1032 { 1033 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1034 u8 reg; 1035 1036 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); 1037 1038 switch (reg) { 1039 case SPMI_FTSMPS426_MODE_HPM_MASK: 1040 return REGULATOR_MODE_NORMAL; 1041 case SPMI_FTSMPS426_MODE_AUTO_MASK: 1042 return REGULATOR_MODE_FAST; 1043 default: 1044 return REGULATOR_MODE_IDLE; 1045 } 1046 } 1047 1048 static int 1049 spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) 1050 { 1051 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1052 u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; 1053 u8 val; 1054 1055 switch (mode) { 1056 case REGULATOR_MODE_NORMAL: 1057 val = SPMI_COMMON_MODE_HPM_MASK; 1058 break; 1059 case REGULATOR_MODE_FAST: 1060 val = SPMI_COMMON_MODE_AUTO_MASK; 1061 break; 1062 default: 1063 val = 0; 1064 break; 1065 } 1066 1067 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1068 } 1069 1070 static int 1071 spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode) 1072 { 1073 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1074 u8 mask = SPMI_FTSMPS426_MODE_MASK; 1075 u8 val; 1076 1077 switch (mode) { 1078 case REGULATOR_MODE_NORMAL: 1079 val = SPMI_FTSMPS426_MODE_HPM_MASK; 1080 break; 1081 case REGULATOR_MODE_FAST: 1082 val = SPMI_FTSMPS426_MODE_AUTO_MASK; 1083 break; 1084 case REGULATOR_MODE_IDLE: 1085 val = SPMI_FTSMPS426_MODE_LPM_MASK; 1086 break; 1087 default: 1088 return -EINVAL; 1089 } 1090 1091 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); 1092 } 1093 1094 static int 1095 spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) 1096 { 1097 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1098 unsigned int mode; 1099 1100 if (load_uA >= vreg->hpm_min_load) 1101 mode = REGULATOR_MODE_NORMAL; 1102 else 1103 mode = REGULATOR_MODE_IDLE; 1104 1105 return spmi_regulator_common_set_mode(rdev, mode); 1106 } 1107 1108 static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) 1109 { 1110 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1111 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; 1112 1113 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, 1114 mask, mask); 1115 } 1116 1117 static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) 1118 { 1119 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1120 unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; 1121 1122 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START, 1123 mask, mask); 1124 } 1125 1126 static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA) 1127 { 1128 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1129 enum spmi_regulator_logical_type type = vreg->logical_type; 1130 unsigned int current_reg; 1131 u8 reg; 1132 u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | 1133 SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; 1134 int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500; 1135 1136 if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST) 1137 current_reg = SPMI_BOOST_REG_CURRENT_LIMIT; 1138 else 1139 current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT; 1140 1141 if (ilim_uA > max || ilim_uA <= 0) 1142 return -EINVAL; 1143 1144 reg = (ilim_uA - 1) / 500; 1145 reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; 1146 1147 return spmi_vreg_update_bits(vreg, current_reg, reg, mask); 1148 } 1149 1150 static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg) 1151 { 1152 int ret; 1153 1154 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, 1155 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); 1156 1157 vreg->vs_enable_time = ktime_get(); 1158 1159 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, 1160 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); 1161 1162 return ret; 1163 } 1164 1165 static void spmi_regulator_vs_ocp_work(struct work_struct *work) 1166 { 1167 struct delayed_work *dwork = to_delayed_work(work); 1168 struct spmi_regulator *vreg 1169 = container_of(dwork, struct spmi_regulator, ocp_work); 1170 1171 spmi_regulator_vs_clear_ocp(vreg); 1172 } 1173 1174 static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) 1175 { 1176 struct spmi_regulator *vreg = data; 1177 ktime_t ocp_irq_time; 1178 s64 ocp_trigger_delay_us; 1179 1180 ocp_irq_time = ktime_get(); 1181 ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time, 1182 vreg->vs_enable_time); 1183 1184 /* 1185 * Reset the OCP count if there is a large delay between switch enable 1186 * and when OCP triggers. This is indicative of a hotplug event as 1187 * opposed to a fault. 1188 */ 1189 if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US) 1190 vreg->ocp_count = 0; 1191 1192 /* Wait for switch output to settle back to 0 V after OCP triggered. */ 1193 udelay(SPMI_VS_OCP_FALL_DELAY_US); 1194 1195 vreg->ocp_count++; 1196 1197 if (vreg->ocp_count == 1) { 1198 /* Immediately clear the over current condition. */ 1199 spmi_regulator_vs_clear_ocp(vreg); 1200 } else if (vreg->ocp_count <= vreg->ocp_max_retries) { 1201 /* Schedule the over current clear task to run later. */ 1202 schedule_delayed_work(&vreg->ocp_work, 1203 msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1); 1204 } else { 1205 dev_err(vreg->dev, 1206 "OCP triggered %d times; no further retries\n", 1207 vreg->ocp_count); 1208 } 1209 1210 return IRQ_HANDLED; 1211 } 1212 1213 #define SAW3_VCTL_DATA_MASK 0xFF 1214 #define SAW3_VCTL_CLEAR_MASK 0x700FF 1215 #define SAW3_AVS_CTL_EN_MASK 0x1 1216 #define SAW3_AVS_CTL_TGGL_MASK 0x8000000 1217 #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 1218 1219 static struct regmap *saw_regmap; 1220 1221 static void spmi_saw_set_vdd(void *data) 1222 { 1223 u32 vctl, data3, avs_ctl, pmic_sts; 1224 bool avs_enabled = false; 1225 unsigned long timeout; 1226 u8 voltage_sel = *(u8 *)data; 1227 1228 regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl); 1229 regmap_read(saw_regmap, SAW3_VCTL, &vctl); 1230 regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3); 1231 1232 /* select the band */ 1233 vctl &= ~SAW3_VCTL_CLEAR_MASK; 1234 vctl |= (u32)voltage_sel; 1235 1236 data3 &= ~SAW3_VCTL_CLEAR_MASK; 1237 data3 |= (u32)voltage_sel; 1238 1239 /* If AVS is enabled, switch it off during the voltage change */ 1240 avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl; 1241 if (avs_enabled) { 1242 avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK; 1243 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); 1244 } 1245 1246 regmap_write(saw_regmap, SAW3_RST, 1); 1247 regmap_write(saw_regmap, SAW3_VCTL, vctl); 1248 regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3); 1249 1250 timeout = jiffies + usecs_to_jiffies(100); 1251 do { 1252 regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts); 1253 pmic_sts &= SAW3_VCTL_DATA_MASK; 1254 if (pmic_sts == (u32)voltage_sel) 1255 break; 1256 1257 cpu_relax(); 1258 1259 } while (time_before(jiffies, timeout)); 1260 1261 /* After successful voltage change, switch the AVS back on */ 1262 if (avs_enabled) { 1263 pmic_sts &= 0x3f; 1264 avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK; 1265 avs_ctl |= ((pmic_sts - 4) << 10); 1266 avs_ctl |= (pmic_sts << 17); 1267 avs_ctl |= SAW3_AVS_CTL_TGGL_MASK; 1268 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); 1269 } 1270 } 1271 1272 static int 1273 spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector) 1274 { 1275 struct spmi_regulator *vreg = rdev_get_drvdata(rdev); 1276 int ret; 1277 u8 range_sel, voltage_sel; 1278 1279 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); 1280 if (ret) 1281 return ret; 1282 1283 if (0 != range_sel) { 1284 dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \ 1285 range_sel, voltage_sel); 1286 return -EINVAL; 1287 } 1288 1289 /* Always do the SAW register writes on the first CPU */ 1290 return smp_call_function_single(0, spmi_saw_set_vdd, \ 1291 &voltage_sel, true); 1292 } 1293 1294 static struct regulator_ops spmi_saw_ops = {}; 1295 1296 static const struct regulator_ops spmi_smps_ops = { 1297 .enable = regulator_enable_regmap, 1298 .disable = regulator_disable_regmap, 1299 .is_enabled = regulator_is_enabled_regmap, 1300 .set_voltage_sel = spmi_regulator_common_set_voltage, 1301 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1302 .get_voltage_sel = spmi_regulator_common_get_voltage, 1303 .map_voltage = spmi_regulator_common_map_voltage, 1304 .list_voltage = spmi_regulator_common_list_voltage, 1305 .set_mode = spmi_regulator_common_set_mode, 1306 .get_mode = spmi_regulator_common_get_mode, 1307 .set_load = spmi_regulator_common_set_load, 1308 .set_pull_down = spmi_regulator_common_set_pull_down, 1309 }; 1310 1311 static const struct regulator_ops spmi_ldo_ops = { 1312 .enable = regulator_enable_regmap, 1313 .disable = regulator_disable_regmap, 1314 .is_enabled = regulator_is_enabled_regmap, 1315 .set_voltage_sel = spmi_regulator_common_set_voltage, 1316 .get_voltage_sel = spmi_regulator_common_get_voltage, 1317 .map_voltage = spmi_regulator_common_map_voltage, 1318 .list_voltage = spmi_regulator_common_list_voltage, 1319 .set_mode = spmi_regulator_common_set_mode, 1320 .get_mode = spmi_regulator_common_get_mode, 1321 .set_load = spmi_regulator_common_set_load, 1322 .set_bypass = spmi_regulator_common_set_bypass, 1323 .get_bypass = spmi_regulator_common_get_bypass, 1324 .set_pull_down = spmi_regulator_common_set_pull_down, 1325 .set_soft_start = spmi_regulator_common_set_soft_start, 1326 }; 1327 1328 static const struct regulator_ops spmi_ln_ldo_ops = { 1329 .enable = regulator_enable_regmap, 1330 .disable = regulator_disable_regmap, 1331 .is_enabled = regulator_is_enabled_regmap, 1332 .set_voltage_sel = spmi_regulator_common_set_voltage, 1333 .get_voltage_sel = spmi_regulator_common_get_voltage, 1334 .map_voltage = spmi_regulator_common_map_voltage, 1335 .list_voltage = spmi_regulator_common_list_voltage, 1336 .set_bypass = spmi_regulator_common_set_bypass, 1337 .get_bypass = spmi_regulator_common_get_bypass, 1338 }; 1339 1340 static const struct regulator_ops spmi_vs_ops = { 1341 .enable = spmi_regulator_vs_enable, 1342 .disable = regulator_disable_regmap, 1343 .is_enabled = regulator_is_enabled_regmap, 1344 .set_pull_down = spmi_regulator_common_set_pull_down, 1345 .set_soft_start = spmi_regulator_common_set_soft_start, 1346 .set_over_current_protection = spmi_regulator_vs_ocp, 1347 .set_mode = spmi_regulator_common_set_mode, 1348 .get_mode = spmi_regulator_common_get_mode, 1349 }; 1350 1351 static const struct regulator_ops spmi_boost_ops = { 1352 .enable = regulator_enable_regmap, 1353 .disable = regulator_disable_regmap, 1354 .is_enabled = regulator_is_enabled_regmap, 1355 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1356 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1357 .map_voltage = spmi_regulator_single_map_voltage, 1358 .list_voltage = spmi_regulator_common_list_voltage, 1359 .set_input_current_limit = spmi_regulator_set_ilim, 1360 }; 1361 1362 static const struct regulator_ops spmi_ftsmps_ops = { 1363 .enable = regulator_enable_regmap, 1364 .disable = regulator_disable_regmap, 1365 .is_enabled = regulator_is_enabled_regmap, 1366 .set_voltage_sel = spmi_regulator_common_set_voltage, 1367 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1368 .get_voltage_sel = spmi_regulator_common_get_voltage, 1369 .map_voltage = spmi_regulator_common_map_voltage, 1370 .list_voltage = spmi_regulator_common_list_voltage, 1371 .set_mode = spmi_regulator_common_set_mode, 1372 .get_mode = spmi_regulator_common_get_mode, 1373 .set_load = spmi_regulator_common_set_load, 1374 .set_pull_down = spmi_regulator_common_set_pull_down, 1375 }; 1376 1377 static const struct regulator_ops spmi_ult_lo_smps_ops = { 1378 .enable = regulator_enable_regmap, 1379 .disable = regulator_disable_regmap, 1380 .is_enabled = regulator_is_enabled_regmap, 1381 .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage, 1382 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1383 .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage, 1384 .list_voltage = spmi_regulator_common_list_voltage, 1385 .set_mode = spmi_regulator_common_set_mode, 1386 .get_mode = spmi_regulator_common_get_mode, 1387 .set_load = spmi_regulator_common_set_load, 1388 .set_pull_down = spmi_regulator_common_set_pull_down, 1389 }; 1390 1391 static const struct regulator_ops spmi_ult_ho_smps_ops = { 1392 .enable = regulator_enable_regmap, 1393 .disable = regulator_disable_regmap, 1394 .is_enabled = regulator_is_enabled_regmap, 1395 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1396 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1397 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1398 .map_voltage = spmi_regulator_single_map_voltage, 1399 .list_voltage = spmi_regulator_common_list_voltage, 1400 .set_mode = spmi_regulator_common_set_mode, 1401 .get_mode = spmi_regulator_common_get_mode, 1402 .set_load = spmi_regulator_common_set_load, 1403 .set_pull_down = spmi_regulator_common_set_pull_down, 1404 }; 1405 1406 static const struct regulator_ops spmi_ult_ldo_ops = { 1407 .enable = regulator_enable_regmap, 1408 .disable = regulator_disable_regmap, 1409 .is_enabled = regulator_is_enabled_regmap, 1410 .set_voltage_sel = spmi_regulator_single_range_set_voltage, 1411 .get_voltage_sel = spmi_regulator_single_range_get_voltage, 1412 .map_voltage = spmi_regulator_single_map_voltage, 1413 .list_voltage = spmi_regulator_common_list_voltage, 1414 .set_mode = spmi_regulator_common_set_mode, 1415 .get_mode = spmi_regulator_common_get_mode, 1416 .set_load = spmi_regulator_common_set_load, 1417 .set_bypass = spmi_regulator_common_set_bypass, 1418 .get_bypass = spmi_regulator_common_get_bypass, 1419 .set_pull_down = spmi_regulator_common_set_pull_down, 1420 .set_soft_start = spmi_regulator_common_set_soft_start, 1421 }; 1422 1423 static const struct regulator_ops spmi_ftsmps426_ops = { 1424 .enable = regulator_enable_regmap, 1425 .disable = regulator_disable_regmap, 1426 .is_enabled = regulator_is_enabled_regmap, 1427 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1428 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1429 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1430 .map_voltage = spmi_regulator_single_map_voltage, 1431 .list_voltage = spmi_regulator_common_list_voltage, 1432 .set_mode = spmi_regulator_ftsmps426_set_mode, 1433 .get_mode = spmi_regulator_ftsmps426_get_mode, 1434 .set_load = spmi_regulator_common_set_load, 1435 .set_pull_down = spmi_regulator_common_set_pull_down, 1436 }; 1437 1438 static const struct regulator_ops spmi_hfs430_ops = { 1439 .enable = regulator_enable_regmap, 1440 .disable = regulator_disable_regmap, 1441 .is_enabled = regulator_is_enabled_regmap, 1442 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, 1443 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, 1444 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, 1445 .map_voltage = spmi_regulator_single_map_voltage, 1446 .list_voltage = spmi_regulator_common_list_voltage, 1447 .set_mode = spmi_regulator_ftsmps426_set_mode, 1448 .get_mode = spmi_regulator_ftsmps426_get_mode, 1449 }; 1450 1451 /* Maximum possible digital major revision value */ 1452 #define INF 0xFF 1453 1454 static const struct spmi_regulator_mapping supported_regulators[] = { 1455 /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ 1456 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), 1457 SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), 1458 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), 1459 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), 1460 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), 1461 SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000), 1462 SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000), 1463 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000), 1464 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000), 1465 SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000), 1466 SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000), 1467 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000), 1468 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000), 1469 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000), 1470 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000), 1471 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000), 1472 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0), 1473 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000), 1474 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000), 1475 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), 1476 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), 1477 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), 1478 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426, 1479 ht_nldo, 30000), 1480 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426, 1481 ht_nldo, 30000), 1482 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426, 1483 ht_nldo, 30000), 1484 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426, 1485 ht_lvpldo, 10000), 1486 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426, 1487 ht_lvpldo, 10000), 1488 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426, 1489 nldo660, 10000), 1490 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426, 1491 nldo660, 10000), 1492 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426, 1493 pldo660, 10000), 1494 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426, 1495 pldo660, 10000), 1496 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426, 1497 pldo660, 10000), 1498 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426, 1499 ht_lvpldo, 10000), 1500 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426, 1501 ht_lvpldo, 10000), 1502 SPMI_VREG_VS(LV100, 0, INF), 1503 SPMI_VREG_VS(LV300, 0, INF), 1504 SPMI_VREG_VS(MV300, 0, INF), 1505 SPMI_VREG_VS(MV500, 0, INF), 1506 SPMI_VREG_VS(HDMI, 0, INF), 1507 SPMI_VREG_VS(OTG, 0, INF), 1508 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), 1509 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), 1510 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), 1511 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000), 1512 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), 1513 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1514 ult_lo_smps, 100000), 1515 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1516 ult_lo_smps, 100000), 1517 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps, 1518 ult_lo_smps, 100000), 1519 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps, 1520 ult_ho_smps, 100000), 1521 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1522 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1523 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1524 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), 1525 SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1526 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1527 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1528 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1529 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1530 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1531 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), 1532 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), 1533 }; 1534 1535 static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) 1536 { 1537 unsigned int n; 1538 struct spmi_voltage_range *range = points->range; 1539 1540 for (; range < points->range + points->count; range++) { 1541 n = 0; 1542 if (range->set_point_max_uV) { 1543 n = range->set_point_max_uV - range->set_point_min_uV; 1544 n = (n / range->step_uV) + 1; 1545 } 1546 range->n_voltages = n; 1547 points->n_voltages += n; 1548 } 1549 } 1550 1551 static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) 1552 { 1553 const struct spmi_regulator_mapping *mapping; 1554 int ret, i; 1555 u32 dig_major_rev; 1556 u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1]; 1557 u8 type, subtype; 1558 1559 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version, 1560 ARRAY_SIZE(version)); 1561 if (ret) { 1562 dev_dbg(vreg->dev, "could not read version registers\n"); 1563 return ret; 1564 } 1565 dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV 1566 - SPMI_COMMON_REG_DIG_MAJOR_REV]; 1567 1568 if (!force_type) { 1569 type = version[SPMI_COMMON_REG_TYPE - 1570 SPMI_COMMON_REG_DIG_MAJOR_REV]; 1571 subtype = version[SPMI_COMMON_REG_SUBTYPE - 1572 SPMI_COMMON_REG_DIG_MAJOR_REV]; 1573 } else { 1574 type = force_type >> 8; 1575 subtype = force_type; 1576 } 1577 1578 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { 1579 mapping = &supported_regulators[i]; 1580 if (mapping->type == type && mapping->subtype == subtype 1581 && mapping->revision_min <= dig_major_rev 1582 && mapping->revision_max >= dig_major_rev) 1583 goto found; 1584 } 1585 1586 dev_err(vreg->dev, 1587 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", 1588 vreg->desc.name, type, subtype, dig_major_rev); 1589 1590 return -ENODEV; 1591 1592 found: 1593 vreg->logical_type = mapping->logical_type; 1594 vreg->set_points = mapping->set_points; 1595 vreg->hpm_min_load = mapping->hpm_min_load; 1596 vreg->desc.ops = mapping->ops; 1597 1598 if (mapping->set_points) { 1599 if (!mapping->set_points->n_voltages) 1600 spmi_calculate_num_voltages(mapping->set_points); 1601 vreg->desc.n_voltages = mapping->set_points->n_voltages; 1602 } 1603 1604 return 0; 1605 } 1606 1607 static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) 1608 { 1609 int ret; 1610 u8 reg = 0; 1611 int step, delay, slew_rate, step_delay; 1612 const struct spmi_voltage_range *range; 1613 1614 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); 1615 if (ret) { 1616 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1617 return ret; 1618 } 1619 1620 range = spmi_regulator_find_range(vreg); 1621 if (!range) 1622 return -EINVAL; 1623 1624 switch (vreg->logical_type) { 1625 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: 1626 step_delay = SPMI_FTSMPS_STEP_DELAY; 1627 break; 1628 default: 1629 step_delay = SPMI_DEFAULT_STEP_DELAY; 1630 break; 1631 } 1632 1633 step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; 1634 step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT; 1635 1636 delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; 1637 delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT; 1638 1639 /* slew_rate has units of uV/us */ 1640 slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step); 1641 slew_rate /= 1000 * (step_delay << delay); 1642 slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM; 1643 slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN; 1644 1645 /* Ensure that the slew rate is greater than 0 */ 1646 vreg->slew_rate = max(slew_rate, 1); 1647 1648 return ret; 1649 } 1650 1651 static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg, 1652 int clock_rate) 1653 { 1654 int ret; 1655 u8 reg = 0; 1656 int delay, slew_rate; 1657 const struct spmi_voltage_range *range = &vreg->set_points->range[0]; 1658 1659 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); 1660 if (ret) { 1661 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); 1662 return ret; 1663 } 1664 1665 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; 1666 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; 1667 1668 /* slew_rate has units of uV/us */ 1669 slew_rate = clock_rate * range->step_uV; 1670 slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay); 1671 slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM; 1672 slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN; 1673 1674 /* Ensure that the slew rate is greater than 0 */ 1675 vreg->slew_rate = max(slew_rate, 1); 1676 1677 return ret; 1678 } 1679 1680 static int spmi_regulator_init_registers(struct spmi_regulator *vreg, 1681 const struct spmi_regulator_init_data *data) 1682 { 1683 int ret; 1684 enum spmi_regulator_logical_type type; 1685 u8 ctrl_reg[8], reg, mask; 1686 1687 type = vreg->logical_type; 1688 1689 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1690 if (ret) 1691 return ret; 1692 1693 /* Set up enable pin control. */ 1694 if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) { 1695 switch (type) { 1696 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1697 case SPMI_REGULATOR_LOGICAL_TYPE_LDO: 1698 case SPMI_REGULATOR_LOGICAL_TYPE_VS: 1699 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= 1700 ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; 1701 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= 1702 data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; 1703 break; 1704 default: 1705 break; 1706 } 1707 } 1708 1709 /* Set up mode pin control. */ 1710 if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { 1711 switch (type) { 1712 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1713 case SPMI_REGULATOR_LOGICAL_TYPE_LDO: 1714 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1715 ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK; 1716 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1717 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK; 1718 break; 1719 case SPMI_REGULATOR_LOGICAL_TYPE_VS: 1720 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: 1721 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: 1722 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO: 1723 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1724 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; 1725 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1726 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; 1727 break; 1728 default: 1729 break; 1730 } 1731 } 1732 1733 /* Write back any control register values that were modified. */ 1734 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1735 if (ret) 1736 return ret; 1737 1738 /* Set soft start strength and over current protection for VS. */ 1739 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) { 1740 if (data->vs_soft_start_strength 1741 != SPMI_VS_SOFT_START_STR_HW_DEFAULT) { 1742 reg = data->vs_soft_start_strength 1743 & SPMI_VS_SOFT_START_SEL_MASK; 1744 mask = SPMI_VS_SOFT_START_SEL_MASK; 1745 return spmi_vreg_update_bits(vreg, 1746 SPMI_VS_REG_SOFT_START, 1747 reg, mask); 1748 } 1749 } 1750 1751 return 0; 1752 } 1753 1754 static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg, 1755 struct device_node *node, struct spmi_regulator_init_data *data) 1756 { 1757 /* 1758 * Initialize configuration parameters to use hardware default in case 1759 * no value is specified via device tree. 1760 */ 1761 data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT; 1762 data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT; 1763 data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT; 1764 1765 /* These bindings are optional, so it is okay if they aren't found. */ 1766 of_property_read_u32(node, "qcom,ocp-max-retries", 1767 &vreg->ocp_max_retries); 1768 of_property_read_u32(node, "qcom,ocp-retry-delay", 1769 &vreg->ocp_retry_delay_ms); 1770 of_property_read_u32(node, "qcom,pin-ctrl-enable", 1771 &data->pin_ctrl_enable); 1772 of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm); 1773 of_property_read_u32(node, "qcom,vs-soft-start-strength", 1774 &data->vs_soft_start_strength); 1775 } 1776 1777 static unsigned int spmi_regulator_of_map_mode(unsigned int mode) 1778 { 1779 if (mode == 1) 1780 return REGULATOR_MODE_NORMAL; 1781 if (mode == 2) 1782 return REGULATOR_MODE_FAST; 1783 1784 return REGULATOR_MODE_IDLE; 1785 } 1786 1787 static int spmi_regulator_of_parse(struct device_node *node, 1788 const struct regulator_desc *desc, 1789 struct regulator_config *config) 1790 { 1791 struct spmi_regulator_init_data data = { }; 1792 struct spmi_regulator *vreg = config->driver_data; 1793 struct device *dev = config->dev; 1794 int ret; 1795 1796 spmi_regulator_get_dt_config(vreg, node, &data); 1797 1798 if (!vreg->ocp_max_retries) 1799 vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES; 1800 if (!vreg->ocp_retry_delay_ms) 1801 vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS; 1802 1803 ret = spmi_regulator_init_registers(vreg, &data); 1804 if (ret) { 1805 dev_err(dev, "common initialization failed, ret=%d\n", ret); 1806 return ret; 1807 } 1808 1809 switch (vreg->logical_type) { 1810 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: 1811 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: 1812 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: 1813 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: 1814 ret = spmi_regulator_init_slew_rate(vreg); 1815 if (ret) 1816 return ret; 1817 break; 1818 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426: 1819 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, 1820 SPMI_FTSMPS426_CLOCK_RATE); 1821 if (ret) 1822 return ret; 1823 break; 1824 case SPMI_REGULATOR_LOGICAL_TYPE_HFS430: 1825 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, 1826 SPMI_HFS430_CLOCK_RATE); 1827 if (ret) 1828 return ret; 1829 break; 1830 default: 1831 break; 1832 } 1833 1834 if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS) 1835 vreg->ocp_irq = 0; 1836 1837 if (vreg->ocp_irq) { 1838 ret = devm_request_irq(dev, vreg->ocp_irq, 1839 spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp", 1840 vreg); 1841 if (ret < 0) { 1842 dev_err(dev, "failed to request irq %d, ret=%d\n", 1843 vreg->ocp_irq, ret); 1844 return ret; 1845 } 1846 1847 INIT_DELAYED_WORK(&vreg->ocp_work, spmi_regulator_vs_ocp_work); 1848 } 1849 1850 return 0; 1851 } 1852 1853 static const struct spmi_regulator_data pm8941_regulators[] = { 1854 { "s1", 0x1400, "vdd_s1", }, 1855 { "s2", 0x1700, "vdd_s2", }, 1856 { "s3", 0x1a00, "vdd_s3", }, 1857 { "s4", 0xa000, }, 1858 { "l1", 0x4000, "vdd_l1_l3", }, 1859 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, 1860 { "l3", 0x4200, "vdd_l1_l3", }, 1861 { "l4", 0x4300, "vdd_l4_l11", }, 1862 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, 1863 { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, 1864 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, 1865 { "l8", 0x4700, "vdd_l8_l16_l18_19", }, 1866 { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, 1867 { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, 1868 { "l11", 0x4a00, "vdd_l4_l11", }, 1869 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, 1870 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, 1871 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, 1872 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, 1873 { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, 1874 { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, 1875 { "l18", 0x5100, "vdd_l8_l16_l18_19", }, 1876 { "l19", 0x5200, "vdd_l8_l16_l18_19", }, 1877 { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, 1878 { "l21", 0x5400, "vdd_l21", }, 1879 { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, 1880 { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, 1881 { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, 1882 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, 1883 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, 1884 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, 1885 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, 1886 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, 1887 { } 1888 }; 1889 1890 static const struct spmi_regulator_data pm8841_regulators[] = { 1891 { "s1", 0x1400, "vdd_s1", }, 1892 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 }, 1893 { "s3", 0x1a00, "vdd_s3", }, 1894 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 }, 1895 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 }, 1896 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 }, 1897 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 }, 1898 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 }, 1899 { } 1900 }; 1901 1902 static const struct spmi_regulator_data pm8916_regulators[] = { 1903 { "s1", 0x1400, "vdd_s1", }, 1904 { "s2", 0x1700, "vdd_s2", }, 1905 { "s3", 0x1a00, "vdd_s3", }, 1906 { "s4", 0x1d00, "vdd_s4", }, 1907 { "l1", 0x4000, "vdd_l1_l3", }, 1908 { "l2", 0x4100, "vdd_l2", }, 1909 { "l3", 0x4200, "vdd_l1_l3", }, 1910 { "l4", 0x4300, "vdd_l4_l5_l6", }, 1911 { "l5", 0x4400, "vdd_l4_l5_l6", }, 1912 { "l6", 0x4500, "vdd_l4_l5_l6", }, 1913 { "l7", 0x4600, "vdd_l7", }, 1914 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", }, 1915 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", }, 1916 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", }, 1917 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", }, 1918 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", }, 1919 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", }, 1920 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", }, 1921 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", }, 1922 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, 1923 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, 1924 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, 1925 { } 1926 }; 1927 1928 static const struct spmi_regulator_data pm8950_regulators[] = { 1929 { "s1", 0x1400, "vdd_s1", }, 1930 { "s2", 0x1700, "vdd_s2", }, 1931 { "s3", 0x1a00, "vdd_s3", }, 1932 { "s4", 0x1d00, "vdd_s4", }, 1933 { "s5", 0x2000, "vdd_s5", }, 1934 { "s6", 0x2300, "vdd_s6", }, 1935 { "l1", 0x4000, "vdd_l1_l19", }, 1936 { "l2", 0x4100, "vdd_l2_l23", }, 1937 { "l3", 0x4200, "vdd_l3", }, 1938 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", }, 1939 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", }, 1940 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", }, 1941 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", }, 1942 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", }, 1943 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", }, 1944 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", }, 1945 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", }, 1946 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", }, 1947 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", }, 1948 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", }, 1949 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", }, 1950 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", }, 1951 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", }, 1952 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", }, 1953 { "l19", 0x5200, "vdd_l1_l19", }, 1954 { "l20", 0x5300, "vdd_l20", }, 1955 { "l21", 0x5400, "vdd_l21", }, 1956 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", }, 1957 { "l23", 0x5600, "vdd_l2_l23", }, 1958 { } 1959 }; 1960 1961 static const struct spmi_regulator_data pm8994_regulators[] = { 1962 { "s1", 0x1400, "vdd_s1", }, 1963 { "s2", 0x1700, "vdd_s2", }, 1964 { "s3", 0x1a00, "vdd_s3", }, 1965 { "s4", 0x1d00, "vdd_s4", }, 1966 { "s5", 0x2000, "vdd_s5", }, 1967 { "s6", 0x2300, "vdd_s6", }, 1968 { "s7", 0x2600, "vdd_s7", }, 1969 { "s8", 0x2900, "vdd_s8", }, 1970 { "s9", 0x2c00, "vdd_s9", }, 1971 { "s10", 0x2f00, "vdd_s10", }, 1972 { "s11", 0x3200, "vdd_s11", }, 1973 { "s12", 0x3500, "vdd_s12", }, 1974 { "l1", 0x4000, "vdd_l1", }, 1975 { "l2", 0x4100, "vdd_l2_l26_l28", }, 1976 { "l3", 0x4200, "vdd_l3_l11", }, 1977 { "l4", 0x4300, "vdd_l4_l27_l31", }, 1978 { "l5", 0x4400, "vdd_l5_l7", }, 1979 { "l6", 0x4500, "vdd_l6_l12_l32", }, 1980 { "l7", 0x4600, "vdd_l5_l7", }, 1981 { "l8", 0x4700, "vdd_l8_l16_l30", }, 1982 { "l9", 0x4800, "vdd_l9_l10_l18_l22", }, 1983 { "l10", 0x4900, "vdd_l9_l10_l18_l22", }, 1984 { "l11", 0x4a00, "vdd_l3_l11", }, 1985 { "l12", 0x4b00, "vdd_l6_l12_l32", }, 1986 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", }, 1987 { "l14", 0x4d00, "vdd_l14_l15", }, 1988 { "l15", 0x4e00, "vdd_l14_l15", }, 1989 { "l16", 0x4f00, "vdd_l8_l16_l30", }, 1990 { "l17", 0x5000, "vdd_l17_l29", }, 1991 { "l18", 0x5100, "vdd_l9_l10_l18_l22", }, 1992 { "l19", 0x5200, "vdd_l13_l19_l23_l24", }, 1993 { "l20", 0x5300, "vdd_l20_l21", }, 1994 { "l21", 0x5400, "vdd_l20_l21", }, 1995 { "l22", 0x5500, "vdd_l9_l10_l18_l22", }, 1996 { "l23", 0x5600, "vdd_l13_l19_l23_l24", }, 1997 { "l24", 0x5700, "vdd_l13_l19_l23_l24", }, 1998 { "l25", 0x5800, "vdd_l25", }, 1999 { "l26", 0x5900, "vdd_l2_l26_l28", }, 2000 { "l27", 0x5a00, "vdd_l4_l27_l31", }, 2001 { "l28", 0x5b00, "vdd_l2_l26_l28", }, 2002 { "l29", 0x5c00, "vdd_l17_l29", }, 2003 { "l30", 0x5d00, "vdd_l8_l16_l30", }, 2004 { "l31", 0x5e00, "vdd_l4_l27_l31", }, 2005 { "l32", 0x5f00, "vdd_l6_l12_l32", }, 2006 { "lvs1", 0x8000, "vdd_lvs_1_2", }, 2007 { "lvs2", 0x8100, "vdd_lvs_1_2", }, 2008 { } 2009 }; 2010 2011 static const struct spmi_regulator_data pmi8994_regulators[] = { 2012 { "s1", 0x1400, "vdd_s1", }, 2013 { "s2", 0x1700, "vdd_s2", }, 2014 { "s3", 0x1a00, "vdd_s3", }, 2015 { "l1", 0x4000, "vdd_l1", }, 2016 { } 2017 }; 2018 2019 static const struct spmi_regulator_data pm660_regulators[] = { 2020 { "s1", 0x1400, "vdd_s1", }, 2021 { "s2", 0x1700, "vdd_s2", }, 2022 { "s3", 0x1a00, "vdd_s3", }, 2023 { "s4", 0x1d00, "vdd_s3", }, 2024 { "s5", 0x2000, "vdd_s5", }, 2025 { "s6", 0x2300, "vdd_s6", }, 2026 { "l1", 0x4000, "vdd_l1_l6_l7", }, 2027 { "l2", 0x4100, "vdd_l2_l3", }, 2028 { "l3", 0x4200, "vdd_l2_l3", }, 2029 /* l4 is unaccessible on PM660 */ 2030 { "l5", 0x4400, "vdd_l5", }, 2031 { "l6", 0x4500, "vdd_l1_l6_l7", }, 2032 { "l7", 0x4600, "vdd_l1_l6_l7", }, 2033 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2034 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2035 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2036 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2037 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2038 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2039 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, 2040 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, 2041 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, 2042 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, 2043 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, 2044 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, 2045 { } 2046 }; 2047 2048 static const struct spmi_regulator_data pm660l_regulators[] = { 2049 { "s1", 0x1400, "vdd_s1", }, 2050 { "s2", 0x1700, "vdd_s2", }, 2051 { "s3", 0x1a00, "vdd_s3", }, 2052 { "s4", 0x1d00, "vdd_s4", }, 2053 { "s5", 0x2000, "vdd_s5", }, 2054 { "l1", 0x4000, "vdd_l1_l9_l10", }, 2055 { "l2", 0x4100, "vdd_l2", }, 2056 { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, 2057 { "l4", 0x4300, "vdd_l4_l6", }, 2058 { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, 2059 { "l6", 0x4500, "vdd_l4_l6", }, 2060 { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, 2061 { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, 2062 { "l9", 0x4800, "vdd_l1_l9_l10", }, 2063 { "l10", 0x4900, "vdd_l1_l9_l10", }, 2064 { } 2065 }; 2066 2067 2068 static const struct spmi_regulator_data pm8004_regulators[] = { 2069 { "s2", 0x1700, "vdd_s2", }, 2070 { "s5", 0x2000, "vdd_s5", }, 2071 { } 2072 }; 2073 2074 static const struct spmi_regulator_data pm8005_regulators[] = { 2075 { "s1", 0x1400, "vdd_s1", }, 2076 { "s2", 0x1700, "vdd_s2", }, 2077 { "s3", 0x1a00, "vdd_s3", }, 2078 { "s4", 0x1d00, "vdd_s4", }, 2079 { } 2080 }; 2081 2082 static const struct spmi_regulator_data pms405_regulators[] = { 2083 { "s3", 0x1a00, "vdd_s3"}, 2084 { } 2085 }; 2086 2087 static const struct of_device_id qcom_spmi_regulator_match[] = { 2088 { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, 2089 { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, 2090 { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, 2091 { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, 2092 { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, 2093 { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators }, 2094 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, 2095 { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, 2096 { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, 2097 { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, 2098 { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, 2099 { } 2100 }; 2101 MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); 2102 2103 static int qcom_spmi_regulator_probe(struct platform_device *pdev) 2104 { 2105 const struct spmi_regulator_data *reg; 2106 const struct spmi_voltage_range *range; 2107 const struct of_device_id *match; 2108 struct regulator_config config = { }; 2109 struct regulator_dev *rdev; 2110 struct spmi_regulator *vreg; 2111 struct regmap *regmap; 2112 const char *name; 2113 struct device *dev = &pdev->dev; 2114 struct device_node *node = pdev->dev.of_node; 2115 struct device_node *syscon, *reg_node; 2116 struct property *reg_prop; 2117 int ret, lenp; 2118 struct list_head *vreg_list; 2119 2120 vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); 2121 if (!vreg_list) 2122 return -ENOMEM; 2123 INIT_LIST_HEAD(vreg_list); 2124 platform_set_drvdata(pdev, vreg_list); 2125 2126 regmap = dev_get_regmap(dev->parent, NULL); 2127 if (!regmap) 2128 return -ENODEV; 2129 2130 match = of_match_device(qcom_spmi_regulator_match, &pdev->dev); 2131 if (!match) 2132 return -ENODEV; 2133 2134 if (of_find_property(node, "qcom,saw-reg", &lenp)) { 2135 syscon = of_parse_phandle(node, "qcom,saw-reg", 0); 2136 saw_regmap = syscon_node_to_regmap(syscon); 2137 of_node_put(syscon); 2138 if (IS_ERR(saw_regmap)) 2139 dev_err(dev, "ERROR reading SAW regmap\n"); 2140 } 2141 2142 for (reg = match->data; reg->name; reg++) { 2143 2144 if (saw_regmap) { 2145 reg_node = of_get_child_by_name(node, reg->name); 2146 reg_prop = of_find_property(reg_node, "qcom,saw-slave", 2147 &lenp); 2148 of_node_put(reg_node); 2149 if (reg_prop) 2150 continue; 2151 } 2152 2153 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); 2154 if (!vreg) 2155 return -ENOMEM; 2156 2157 vreg->dev = dev; 2158 vreg->base = reg->base; 2159 vreg->regmap = regmap; 2160 if (reg->ocp) { 2161 vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); 2162 if (vreg->ocp_irq < 0) { 2163 ret = vreg->ocp_irq; 2164 goto err; 2165 } 2166 } 2167 vreg->desc.id = -1; 2168 vreg->desc.owner = THIS_MODULE; 2169 vreg->desc.type = REGULATOR_VOLTAGE; 2170 vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; 2171 vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK; 2172 vreg->desc.enable_val = SPMI_COMMON_ENABLE; 2173 vreg->desc.name = name = reg->name; 2174 vreg->desc.supply_name = reg->supply; 2175 vreg->desc.of_match = reg->name; 2176 vreg->desc.of_parse_cb = spmi_regulator_of_parse; 2177 vreg->desc.of_map_mode = spmi_regulator_of_map_mode; 2178 2179 ret = spmi_regulator_match(vreg, reg->force_type); 2180 if (ret) 2181 continue; 2182 2183 if (saw_regmap) { 2184 reg_node = of_get_child_by_name(node, reg->name); 2185 reg_prop = of_find_property(reg_node, "qcom,saw-leader", 2186 &lenp); 2187 of_node_put(reg_node); 2188 if (reg_prop) { 2189 spmi_saw_ops = *(vreg->desc.ops); 2190 spmi_saw_ops.set_voltage_sel = 2191 spmi_regulator_saw_set_voltage; 2192 vreg->desc.ops = &spmi_saw_ops; 2193 } 2194 } 2195 2196 if (vreg->set_points && vreg->set_points->count == 1) { 2197 /* since there is only one range */ 2198 range = vreg->set_points->range; 2199 vreg->desc.uV_step = range->step_uV; 2200 } 2201 2202 config.dev = dev; 2203 config.driver_data = vreg; 2204 config.regmap = regmap; 2205 rdev = devm_regulator_register(dev, &vreg->desc, &config); 2206 if (IS_ERR(rdev)) { 2207 dev_err(dev, "failed to register %s\n", name); 2208 ret = PTR_ERR(rdev); 2209 goto err; 2210 } 2211 2212 INIT_LIST_HEAD(&vreg->node); 2213 list_add(&vreg->node, vreg_list); 2214 } 2215 2216 return 0; 2217 2218 err: 2219 list_for_each_entry(vreg, vreg_list, node) 2220 if (vreg->ocp_irq) 2221 cancel_delayed_work_sync(&vreg->ocp_work); 2222 return ret; 2223 } 2224 2225 static int qcom_spmi_regulator_remove(struct platform_device *pdev) 2226 { 2227 struct spmi_regulator *vreg; 2228 struct list_head *vreg_list = platform_get_drvdata(pdev); 2229 2230 list_for_each_entry(vreg, vreg_list, node) 2231 if (vreg->ocp_irq) 2232 cancel_delayed_work_sync(&vreg->ocp_work); 2233 2234 return 0; 2235 } 2236 2237 static struct platform_driver qcom_spmi_regulator_driver = { 2238 .driver = { 2239 .name = "qcom-spmi-regulator", 2240 .of_match_table = qcom_spmi_regulator_match, 2241 }, 2242 .probe = qcom_spmi_regulator_probe, 2243 .remove = qcom_spmi_regulator_remove, 2244 }; 2245 module_platform_driver(qcom_spmi_regulator_driver); 2246 2247 MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver"); 2248 MODULE_LICENSE("GPL v2"); 2249 MODULE_ALIAS("platform:qcom-spmi-regulator"); 2250