1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, Sony Mobile Communications AB. 4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/regulator/driver.h> 12 #include <linux/soc/qcom/smd-rpm.h> 13 14 struct qcom_rpm_reg { 15 struct device *dev; 16 17 struct qcom_smd_rpm *rpm; 18 19 u32 type; 20 u32 id; 21 22 struct regulator_desc desc; 23 24 int is_enabled; 25 int uV; 26 u32 load; 27 28 unsigned int enabled_updated:1; 29 unsigned int uv_updated:1; 30 unsigned int load_updated:1; 31 }; 32 33 struct rpm_regulator_req { 34 __le32 key; 35 __le32 nbytes; 36 __le32 value; 37 }; 38 39 #define RPM_KEY_SWEN 0x6e657773 /* "swen" */ 40 #define RPM_KEY_UV 0x00007675 /* "uv" */ 41 #define RPM_KEY_MA 0x0000616d /* "ma" */ 42 43 static int rpm_reg_write_active(struct qcom_rpm_reg *vreg) 44 { 45 struct rpm_regulator_req req[3]; 46 int reqlen = 0; 47 int ret; 48 49 if (vreg->enabled_updated) { 50 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN); 51 req[reqlen].nbytes = cpu_to_le32(sizeof(u32)); 52 req[reqlen].value = cpu_to_le32(vreg->is_enabled); 53 reqlen++; 54 } 55 56 if (vreg->uv_updated && vreg->is_enabled) { 57 req[reqlen].key = cpu_to_le32(RPM_KEY_UV); 58 req[reqlen].nbytes = cpu_to_le32(sizeof(u32)); 59 req[reqlen].value = cpu_to_le32(vreg->uV); 60 reqlen++; 61 } 62 63 if (vreg->load_updated && vreg->is_enabled) { 64 req[reqlen].key = cpu_to_le32(RPM_KEY_MA); 65 req[reqlen].nbytes = cpu_to_le32(sizeof(u32)); 66 req[reqlen].value = cpu_to_le32(vreg->load / 1000); 67 reqlen++; 68 } 69 70 if (!reqlen) 71 return 0; 72 73 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 74 vreg->type, vreg->id, 75 req, sizeof(req[0]) * reqlen); 76 if (!ret) { 77 vreg->enabled_updated = 0; 78 vreg->uv_updated = 0; 79 vreg->load_updated = 0; 80 } 81 82 return ret; 83 } 84 85 static int rpm_reg_enable(struct regulator_dev *rdev) 86 { 87 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 88 int ret; 89 90 vreg->is_enabled = 1; 91 vreg->enabled_updated = 1; 92 93 ret = rpm_reg_write_active(vreg); 94 if (ret) 95 vreg->is_enabled = 0; 96 97 return ret; 98 } 99 100 static int rpm_reg_is_enabled(struct regulator_dev *rdev) 101 { 102 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 103 104 return vreg->is_enabled; 105 } 106 107 static int rpm_reg_disable(struct regulator_dev *rdev) 108 { 109 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 110 int ret; 111 112 vreg->is_enabled = 0; 113 vreg->enabled_updated = 1; 114 115 ret = rpm_reg_write_active(vreg); 116 if (ret) 117 vreg->is_enabled = 1; 118 119 return ret; 120 } 121 122 static int rpm_reg_get_voltage(struct regulator_dev *rdev) 123 { 124 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 125 126 return vreg->uV; 127 } 128 129 static int rpm_reg_set_voltage(struct regulator_dev *rdev, 130 int min_uV, 131 int max_uV, 132 unsigned *selector) 133 { 134 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 135 int ret; 136 int old_uV = vreg->uV; 137 138 vreg->uV = min_uV; 139 vreg->uv_updated = 1; 140 141 ret = rpm_reg_write_active(vreg); 142 if (ret) 143 vreg->uV = old_uV; 144 145 return ret; 146 } 147 148 static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA) 149 { 150 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 151 u32 old_load = vreg->load; 152 int ret; 153 154 vreg->load = load_uA; 155 vreg->load_updated = 1; 156 ret = rpm_reg_write_active(vreg); 157 if (ret) 158 vreg->load = old_load; 159 160 return ret; 161 } 162 163 static const struct regulator_ops rpm_smps_ldo_ops = { 164 .enable = rpm_reg_enable, 165 .disable = rpm_reg_disable, 166 .is_enabled = rpm_reg_is_enabled, 167 .list_voltage = regulator_list_voltage_linear_range, 168 169 .get_voltage = rpm_reg_get_voltage, 170 .set_voltage = rpm_reg_set_voltage, 171 172 .set_load = rpm_reg_set_load, 173 }; 174 175 static const struct regulator_ops rpm_smps_ldo_ops_fixed = { 176 .enable = rpm_reg_enable, 177 .disable = rpm_reg_disable, 178 .is_enabled = rpm_reg_is_enabled, 179 180 .get_voltage = rpm_reg_get_voltage, 181 .set_voltage = rpm_reg_set_voltage, 182 183 .set_load = rpm_reg_set_load, 184 }; 185 186 static const struct regulator_ops rpm_switch_ops = { 187 .enable = rpm_reg_enable, 188 .disable = rpm_reg_disable, 189 .is_enabled = rpm_reg_is_enabled, 190 }; 191 192 static const struct regulator_ops rpm_bob_ops = { 193 .enable = rpm_reg_enable, 194 .disable = rpm_reg_disable, 195 .is_enabled = rpm_reg_is_enabled, 196 197 .get_voltage = rpm_reg_get_voltage, 198 .set_voltage = rpm_reg_set_voltage, 199 }; 200 201 static const struct regulator_desc pma8084_hfsmps = { 202 .linear_ranges = (struct regulator_linear_range[]) { 203 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), 204 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000), 205 }, 206 .n_linear_ranges = 2, 207 .n_voltages = 159, 208 .ops = &rpm_smps_ldo_ops, 209 }; 210 211 static const struct regulator_desc pma8084_ftsmps = { 212 .linear_ranges = (struct regulator_linear_range[]) { 213 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000), 214 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000), 215 }, 216 .n_linear_ranges = 2, 217 .n_voltages = 262, 218 .ops = &rpm_smps_ldo_ops, 219 }; 220 221 static const struct regulator_desc pma8084_pldo = { 222 .linear_ranges = (struct regulator_linear_range[]) { 223 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), 224 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), 225 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), 226 }, 227 .n_linear_ranges = 3, 228 .n_voltages = 164, 229 .ops = &rpm_smps_ldo_ops, 230 }; 231 232 static const struct regulator_desc pma8084_nldo = { 233 .linear_ranges = (struct regulator_linear_range[]) { 234 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), 235 }, 236 .n_linear_ranges = 1, 237 .n_voltages = 64, 238 .ops = &rpm_smps_ldo_ops, 239 }; 240 241 static const struct regulator_desc pma8084_switch = { 242 .ops = &rpm_switch_ops, 243 }; 244 245 static const struct regulator_desc pm8x41_hfsmps = { 246 .linear_ranges = (struct regulator_linear_range[]) { 247 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500), 248 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000), 249 }, 250 .n_linear_ranges = 2, 251 .n_voltages = 159, 252 .ops = &rpm_smps_ldo_ops, 253 }; 254 255 static const struct regulator_desc pm8841_ftsmps = { 256 .linear_ranges = (struct regulator_linear_range[]) { 257 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000), 258 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000), 259 }, 260 .n_linear_ranges = 2, 261 .n_voltages = 262, 262 .ops = &rpm_smps_ldo_ops, 263 }; 264 265 static const struct regulator_desc pm8941_boost = { 266 .linear_ranges = (struct regulator_linear_range[]) { 267 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000), 268 }, 269 .n_linear_ranges = 1, 270 .n_voltages = 31, 271 .ops = &rpm_smps_ldo_ops, 272 }; 273 274 static const struct regulator_desc pm8941_pldo = { 275 .linear_ranges = (struct regulator_linear_range[]) { 276 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), 277 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), 278 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), 279 }, 280 .n_linear_ranges = 3, 281 .n_voltages = 164, 282 .ops = &rpm_smps_ldo_ops, 283 }; 284 285 static const struct regulator_desc pm8941_nldo = { 286 .linear_ranges = (struct regulator_linear_range[]) { 287 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), 288 }, 289 .n_linear_ranges = 1, 290 .n_voltages = 64, 291 .ops = &rpm_smps_ldo_ops, 292 }; 293 294 static const struct regulator_desc pm8941_lnldo = { 295 .fixed_uV = 1740000, 296 .n_voltages = 1, 297 .ops = &rpm_smps_ldo_ops_fixed, 298 }; 299 300 static const struct regulator_desc pm8941_switch = { 301 .ops = &rpm_switch_ops, 302 }; 303 304 static const struct regulator_desc pm8916_pldo = { 305 .linear_ranges = (struct regulator_linear_range[]) { 306 REGULATOR_LINEAR_RANGE(750000, 0, 208, 12500), 307 }, 308 .n_linear_ranges = 1, 309 .n_voltages = 209, 310 .ops = &rpm_smps_ldo_ops, 311 }; 312 313 static const struct regulator_desc pm8916_nldo = { 314 .linear_ranges = (struct regulator_linear_range[]) { 315 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500), 316 }, 317 .n_linear_ranges = 1, 318 .n_voltages = 94, 319 .ops = &rpm_smps_ldo_ops, 320 }; 321 322 static const struct regulator_desc pm8916_buck_lvo_smps = { 323 .linear_ranges = (struct regulator_linear_range[]) { 324 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), 325 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000), 326 }, 327 .n_linear_ranges = 2, 328 .n_voltages = 128, 329 .ops = &rpm_smps_ldo_ops, 330 }; 331 332 static const struct regulator_desc pm8916_buck_hvo_smps = { 333 .linear_ranges = (struct regulator_linear_range[]) { 334 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000), 335 }, 336 .n_linear_ranges = 1, 337 .n_voltages = 32, 338 .ops = &rpm_smps_ldo_ops, 339 }; 340 341 static const struct regulator_desc pm8950_hfsmps = { 342 .linear_ranges = (struct regulator_linear_range[]) { 343 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), 344 REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000), 345 }, 346 .n_linear_ranges = 2, 347 .n_voltages = 128, 348 .ops = &rpm_smps_ldo_ops, 349 }; 350 351 static const struct regulator_desc pm8950_ftsmps2p5 = { 352 .linear_ranges = (struct regulator_linear_range[]) { 353 REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000), 354 REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000), 355 }, 356 .n_linear_ranges = 2, 357 .n_voltages = 461, 358 .ops = &rpm_smps_ldo_ops, 359 }; 360 361 static const struct regulator_desc pm8950_ult_nldo = { 362 .linear_ranges = (struct regulator_linear_range[]) { 363 REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500), 364 }, 365 .n_linear_ranges = 1, 366 .n_voltages = 203, 367 .ops = &rpm_smps_ldo_ops, 368 }; 369 370 static const struct regulator_desc pm8950_ult_pldo = { 371 .linear_ranges = (struct regulator_linear_range[]) { 372 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500), 373 }, 374 .n_linear_ranges = 1, 375 .n_voltages = 128, 376 .ops = &rpm_smps_ldo_ops, 377 }; 378 379 static const struct regulator_desc pm8950_pldo_lv = { 380 .linear_ranges = (struct regulator_linear_range[]) { 381 REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000), 382 }, 383 .n_linear_ranges = 1, 384 .n_voltages = 17, 385 .ops = &rpm_smps_ldo_ops, 386 }; 387 388 static const struct regulator_desc pm8950_pldo = { 389 .linear_ranges = (struct regulator_linear_range[]) { 390 REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500), 391 }, 392 .n_linear_ranges = 1, 393 .n_voltages = 165, 394 .ops = &rpm_smps_ldo_ops, 395 }; 396 397 398 static const struct regulator_desc pm8994_hfsmps = { 399 .linear_ranges = (struct regulator_linear_range[]) { 400 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500), 401 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000), 402 }, 403 .n_linear_ranges = 2, 404 .n_voltages = 159, 405 .ops = &rpm_smps_ldo_ops, 406 }; 407 408 static const struct regulator_desc pm8994_ftsmps = { 409 .linear_ranges = (struct regulator_linear_range[]) { 410 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000), 411 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000), 412 }, 413 .n_linear_ranges = 2, 414 .n_voltages = 350, 415 .ops = &rpm_smps_ldo_ops, 416 }; 417 418 static const struct regulator_desc pm8994_nldo = { 419 .linear_ranges = (struct regulator_linear_range[]) { 420 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), 421 }, 422 .n_linear_ranges = 1, 423 .n_voltages = 64, 424 .ops = &rpm_smps_ldo_ops, 425 }; 426 427 static const struct regulator_desc pm8994_pldo = { 428 .linear_ranges = (struct regulator_linear_range[]) { 429 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), 430 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), 431 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), 432 }, 433 .n_linear_ranges = 3, 434 .n_voltages = 164, 435 .ops = &rpm_smps_ldo_ops, 436 }; 437 438 static const struct regulator_desc pm8994_switch = { 439 .ops = &rpm_switch_ops, 440 }; 441 442 static const struct regulator_desc pm8994_lnldo = { 443 .fixed_uV = 1740000, 444 .n_voltages = 1, 445 .ops = &rpm_smps_ldo_ops_fixed, 446 }; 447 448 static const struct regulator_desc pm8998_ftsmps = { 449 .linear_ranges = (struct regulator_linear_range[]) { 450 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000), 451 }, 452 .n_linear_ranges = 1, 453 .n_voltages = 259, 454 .ops = &rpm_smps_ldo_ops, 455 }; 456 457 static const struct regulator_desc pm8998_hfsmps = { 458 .linear_ranges = (struct regulator_linear_range[]) { 459 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), 460 }, 461 .n_linear_ranges = 1, 462 .n_voltages = 216, 463 .ops = &rpm_smps_ldo_ops, 464 }; 465 466 static const struct regulator_desc pm8998_nldo = { 467 .linear_ranges = (struct regulator_linear_range[]) { 468 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), 469 }, 470 .n_linear_ranges = 1, 471 .n_voltages = 128, 472 .ops = &rpm_smps_ldo_ops, 473 }; 474 475 static const struct regulator_desc pm8998_pldo = { 476 .linear_ranges = (struct regulator_linear_range[]) { 477 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000), 478 }, 479 .n_linear_ranges = 1, 480 .n_voltages = 256, 481 .ops = &rpm_smps_ldo_ops, 482 }; 483 484 static const struct regulator_desc pm8998_pldo_lv = { 485 .linear_ranges = (struct regulator_linear_range[]) { 486 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000), 487 }, 488 .n_linear_ranges = 1, 489 .n_voltages = 128, 490 .ops = &rpm_smps_ldo_ops, 491 }; 492 493 static const struct regulator_desc pm8998_switch = { 494 .ops = &rpm_switch_ops, 495 }; 496 497 static const struct regulator_desc pmi8998_bob = { 498 .linear_ranges = (struct regulator_linear_range[]) { 499 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000), 500 }, 501 .n_linear_ranges = 1, 502 .n_voltages = 84, 503 .ops = &rpm_bob_ops, 504 }; 505 506 static const struct regulator_desc pms405_hfsmps3 = { 507 .linear_ranges = (struct regulator_linear_range[]) { 508 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), 509 }, 510 .n_linear_ranges = 1, 511 .n_voltages = 216, 512 .ops = &rpm_smps_ldo_ops, 513 }; 514 515 static const struct regulator_desc pms405_nldo300 = { 516 .linear_ranges = (struct regulator_linear_range[]) { 517 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), 518 }, 519 .n_linear_ranges = 1, 520 .n_voltages = 128, 521 .ops = &rpm_smps_ldo_ops, 522 }; 523 524 static const struct regulator_desc pms405_nldo1200 = { 525 .linear_ranges = (struct regulator_linear_range[]) { 526 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), 527 }, 528 .n_linear_ranges = 1, 529 .n_voltages = 128, 530 .ops = &rpm_smps_ldo_ops, 531 }; 532 533 static const struct regulator_desc pms405_pldo50 = { 534 .linear_ranges = (struct regulator_linear_range[]) { 535 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000), 536 }, 537 .n_linear_ranges = 1, 538 .n_voltages = 129, 539 .ops = &rpm_smps_ldo_ops, 540 }; 541 542 static const struct regulator_desc pms405_pldo150 = { 543 .linear_ranges = (struct regulator_linear_range[]) { 544 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000), 545 }, 546 .n_linear_ranges = 1, 547 .n_voltages = 129, 548 .ops = &rpm_smps_ldo_ops, 549 }; 550 551 static const struct regulator_desc pms405_pldo600 = { 552 .linear_ranges = (struct regulator_linear_range[]) { 553 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000), 554 }, 555 .n_linear_ranges = 1, 556 .n_voltages = 99, 557 .ops = &rpm_smps_ldo_ops, 558 }; 559 560 struct rpm_regulator_data { 561 const char *name; 562 u32 type; 563 u32 id; 564 const struct regulator_desc *desc; 565 const char *supply; 566 }; 567 568 static const struct rpm_regulator_data rpm_pm8841_regulators[] = { 569 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" }, 570 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" }, 571 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" }, 572 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" }, 573 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" }, 574 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" }, 575 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" }, 576 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" }, 577 {} 578 }; 579 580 static const struct rpm_regulator_data rpm_pm8916_regulators[] = { 581 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" }, 582 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" }, 583 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" }, 584 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" }, 585 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" }, 586 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" }, 587 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" }, 588 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" }, 589 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" }, 590 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" }, 591 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" }, 592 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" }, 593 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" }, 594 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 595 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 596 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 597 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 598 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 599 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 600 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 601 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 602 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 603 {} 604 }; 605 606 static const struct rpm_regulator_data rpm_pm8941_regulators[] = { 607 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" }, 608 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" }, 609 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" }, 610 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost }, 611 612 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" }, 613 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" }, 614 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" }, 615 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" }, 616 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" }, 617 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 618 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" }, 619 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 620 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 621 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 622 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" }, 623 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 624 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 625 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 626 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 627 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 628 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 629 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 630 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 631 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 632 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" }, 633 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 634 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 635 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 636 637 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" }, 638 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" }, 639 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" }, 640 641 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" }, 642 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" }, 643 644 {} 645 }; 646 647 static const struct rpm_regulator_data rpm_pma8084_regulators[] = { 648 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" }, 649 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" }, 650 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" }, 651 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" }, 652 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" }, 653 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" }, 654 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" }, 655 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" }, 656 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" }, 657 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" }, 658 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" }, 659 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" }, 660 661 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" }, 662 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 663 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 664 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 665 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" }, 666 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 667 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" }, 668 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" }, 669 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 670 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 671 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" }, 672 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 673 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 674 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 675 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 676 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" }, 677 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" }, 678 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" }, 679 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" }, 680 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 681 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" }, 682 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" }, 683 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 684 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 685 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" }, 686 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 687 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 688 689 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch }, 690 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch }, 691 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch }, 692 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch }, 693 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch }, 694 695 {} 696 }; 697 698 static const struct rpm_regulator_data rpm_pm8950_regulators[] = { 699 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" }, 700 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" }, 701 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" }, 702 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" }, 703 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" }, 704 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" }, 705 706 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" }, 707 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" }, 708 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" }, 709 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" }, 710 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l4_l5_l6_l7_l16" }, 711 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l4_l5_l6_l7_l16" }, 712 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l4_l5_l6_l7_l16" }, 713 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" }, 714 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" }, 715 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"}, 716 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22"}, 717 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22"}, 718 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18"}, 719 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18"}, 720 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18"}, 721 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16"}, 722 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22"}, 723 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18"}, 724 { "l19", QCOM_SMD_RPM_LDOA, 18, &pm8950_pldo, "vdd_l1_l19"}, 725 { "l20", QCOM_SMD_RPM_LDOA, 18, &pm8950_pldo, "vdd_l20"}, 726 { "l21", QCOM_SMD_RPM_LDOA, 18, &pm8950_pldo, "vdd_l21"}, 727 { "l22", QCOM_SMD_RPM_LDOA, 18, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22"}, 728 { "l23", QCOM_SMD_RPM_LDOA, 18, &pm8950_pldo, "vdd_l2_l23"}, 729 {} 730 }; 731 732 static const struct rpm_regulator_data rpm_pm8994_regulators[] = { 733 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" }, 734 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" }, 735 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" }, 736 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" }, 737 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" }, 738 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" }, 739 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" }, 740 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" }, 741 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" }, 742 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" }, 743 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" }, 744 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" }, 745 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" }, 746 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" }, 747 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" }, 748 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" }, 749 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" }, 750 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" }, 751 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" }, 752 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" }, 753 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 754 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 755 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" }, 756 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" }, 757 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 758 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" }, 759 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" }, 760 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" }, 761 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" }, 762 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 763 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 764 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" }, 765 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" }, 766 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 767 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 768 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 769 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" }, 770 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" }, 771 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" }, 772 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" }, 773 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" }, 774 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" }, 775 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" }, 776 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" }, 777 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" }, 778 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" }, 779 780 {} 781 }; 782 783 static const struct rpm_regulator_data rpm_pm8998_regulators[] = { 784 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" }, 785 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" }, 786 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" }, 787 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" }, 788 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" }, 789 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" }, 790 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" }, 791 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" }, 792 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" }, 793 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" }, 794 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" }, 795 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" }, 796 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" }, 797 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" }, 798 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" }, 799 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" }, 800 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" }, 801 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" }, 802 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" }, 803 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 804 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" }, 805 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" }, 806 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" }, 807 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" }, 808 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 809 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" }, 810 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 811 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 812 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" }, 813 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" }, 814 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" }, 815 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" }, 816 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" }, 817 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" }, 818 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" }, 819 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" }, 820 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" }, 821 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" }, 822 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" }, 823 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" }, 824 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" }, 825 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" }, 826 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" }, 827 {} 828 }; 829 830 static const struct rpm_regulator_data rpm_pmi8998_regulators[] = { 831 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" }, 832 {} 833 }; 834 835 static const struct rpm_regulator_data rpm_pms405_regulators[] = { 836 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" }, 837 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" }, 838 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" }, 839 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" }, 840 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" }, 841 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" }, 842 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" }, 843 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" }, 844 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" }, 845 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" }, 846 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" }, 847 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" }, 848 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" }, 849 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" }, 850 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" }, 851 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" }, 852 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" }, 853 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" }, 854 {} 855 }; 856 857 static const struct of_device_id rpm_of_match[] = { 858 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, 859 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, 860 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, 861 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators }, 862 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, 863 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators }, 864 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, 865 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators }, 866 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators }, 867 {} 868 }; 869 MODULE_DEVICE_TABLE(of, rpm_of_match); 870 871 static int rpm_reg_probe(struct platform_device *pdev) 872 { 873 const struct rpm_regulator_data *reg; 874 const struct of_device_id *match; 875 struct regulator_config config = { }; 876 struct regulator_dev *rdev; 877 struct qcom_rpm_reg *vreg; 878 struct qcom_smd_rpm *rpm; 879 880 rpm = dev_get_drvdata(pdev->dev.parent); 881 if (!rpm) { 882 dev_err(&pdev->dev, "unable to retrieve handle to rpm\n"); 883 return -ENODEV; 884 } 885 886 match = of_match_device(rpm_of_match, &pdev->dev); 887 if (!match) { 888 dev_err(&pdev->dev, "failed to match device\n"); 889 return -ENODEV; 890 } 891 892 for (reg = match->data; reg->name; reg++) { 893 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL); 894 if (!vreg) 895 return -ENOMEM; 896 897 vreg->dev = &pdev->dev; 898 vreg->type = reg->type; 899 vreg->id = reg->id; 900 vreg->rpm = rpm; 901 902 memcpy(&vreg->desc, reg->desc, sizeof(vreg->desc)); 903 904 vreg->desc.id = -1; 905 vreg->desc.owner = THIS_MODULE; 906 vreg->desc.type = REGULATOR_VOLTAGE; 907 vreg->desc.name = reg->name; 908 vreg->desc.supply_name = reg->supply; 909 vreg->desc.of_match = reg->name; 910 911 config.dev = &pdev->dev; 912 config.driver_data = vreg; 913 rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config); 914 if (IS_ERR(rdev)) { 915 dev_err(&pdev->dev, "failed to register %s\n", reg->name); 916 return PTR_ERR(rdev); 917 } 918 } 919 920 return 0; 921 } 922 923 static struct platform_driver rpm_reg_driver = { 924 .probe = rpm_reg_probe, 925 .driver = { 926 .name = "qcom_rpm_smd_regulator", 927 .of_match_table = rpm_of_match, 928 }, 929 }; 930 931 static int __init rpm_reg_init(void) 932 { 933 return platform_driver_register(&rpm_reg_driver); 934 } 935 subsys_initcall(rpm_reg_init); 936 937 static void __exit rpm_reg_exit(void) 938 { 939 platform_driver_unregister(&rpm_reg_driver); 940 } 941 module_exit(rpm_reg_exit) 942 943 MODULE_DESCRIPTION("Qualcomm RPM regulator driver"); 944 MODULE_LICENSE("GPL v2"); 945