1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/err.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/regulator/of_regulator.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/regulator/pfuze100.h>
16 #include <linux/i2c.h>
17 #include <linux/slab.h>
18 #include <linux/regmap.h>
19 
20 #define PFUZE_FLAG_DISABLE_SW	BIT(1)
21 
22 #define PFUZE_NUMREGS		128
23 #define PFUZE100_VOL_OFFSET	0
24 #define PFUZE100_STANDBY_OFFSET	1
25 #define PFUZE100_MODE_OFFSET	3
26 #define PFUZE100_CONF_OFFSET	4
27 
28 #define PFUZE100_DEVICEID	0x0
29 #define PFUZE100_REVID		0x3
30 #define PFUZE100_FABID		0x4
31 
32 #define PFUZE100_COINVOL	0x1a
33 #define PFUZE100_SW1ABVOL	0x20
34 #define PFUZE100_SW1ABMODE	0x23
35 #define PFUZE100_SW1CVOL	0x2e
36 #define PFUZE100_SW1CMODE	0x31
37 #define PFUZE100_SW2VOL		0x35
38 #define PFUZE100_SW2MODE	0x38
39 #define PFUZE100_SW3AVOL	0x3c
40 #define PFUZE100_SW3AMODE	0x3f
41 #define PFUZE100_SW3BVOL	0x43
42 #define PFUZE100_SW3BMODE	0x46
43 #define PFUZE100_SW4VOL		0x4a
44 #define PFUZE100_SW4MODE	0x4d
45 #define PFUZE100_SWBSTCON1	0x66
46 #define PFUZE100_VREFDDRCON	0x6a
47 #define PFUZE100_VSNVSVOL	0x6b
48 #define PFUZE100_VGEN1VOL	0x6c
49 #define PFUZE100_VGEN2VOL	0x6d
50 #define PFUZE100_VGEN3VOL	0x6e
51 #define PFUZE100_VGEN4VOL	0x6f
52 #define PFUZE100_VGEN5VOL	0x70
53 #define PFUZE100_VGEN6VOL	0x71
54 
55 #define PFUZE100_SWxMODE_MASK	0xf
56 #define PFUZE100_SWxMODE_APS_APS	0x8
57 #define PFUZE100_SWxMODE_APS_OFF	0x4
58 
59 #define PFUZE100_VGENxLPWR	BIT(6)
60 #define PFUZE100_VGENxSTBY	BIT(5)
61 
62 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
63 
64 struct pfuze_regulator {
65 	struct regulator_desc desc;
66 	unsigned char stby_reg;
67 	unsigned char stby_mask;
68 	bool sw_reg;
69 };
70 
71 struct pfuze_chip {
72 	int	chip_id;
73 	int     flags;
74 	struct regmap *regmap;
75 	struct device *dev;
76 	struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
77 	struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
78 	struct pfuze_regulator *pfuze_regulators;
79 };
80 
81 static const int pfuze100_swbst[] = {
82 	5000000, 5050000, 5100000, 5150000,
83 };
84 
85 static const int pfuze100_vsnvs[] = {
86 	1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
87 };
88 
89 static const int pfuze100_coin[] = {
90 	2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
91 };
92 
93 static const int pfuze3000_sw1a[] = {
94 	700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
95 	900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
96 	1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
97 	1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
98 };
99 
100 static const int pfuze3000_sw2lo[] = {
101 	1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
102 };
103 
104 static const int pfuze3000_sw2hi[] = {
105 	2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
106 };
107 
108 static const struct of_device_id pfuze_dt_ids[] = {
109 	{ .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
110 	{ .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
111 	{ .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
112 	{ .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
113 	{ }
114 };
115 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
116 
117 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
118 {
119 	struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
120 	int id = rdev_get_id(rdev);
121 	bool reg_has_ramp_delay;
122 	unsigned int ramp_bits = 0;
123 	int ret;
124 
125 	switch (pfuze100->chip_id) {
126 	case PFUZE3001:
127 		/* no dynamic voltage scaling for PF3001 */
128 		reg_has_ramp_delay = false;
129 		break;
130 	case PFUZE3000:
131 		reg_has_ramp_delay = (id < PFUZE3000_SWBST);
132 		break;
133 	case PFUZE200:
134 		reg_has_ramp_delay = (id < PFUZE200_SWBST);
135 		break;
136 	case PFUZE100:
137 	default:
138 		reg_has_ramp_delay = (id < PFUZE100_SWBST);
139 		break;
140 	}
141 
142 	if (reg_has_ramp_delay) {
143 		if (ramp_delay > 0) {
144 			ramp_delay = 12500 / ramp_delay;
145 			ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
146 		}
147 
148 		ret = regmap_update_bits(pfuze100->regmap,
149 					 rdev->desc->vsel_reg + 4,
150 					 0xc0, ramp_bits << 6);
151 		if (ret < 0)
152 			dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
153 	} else {
154 		ret = -EACCES;
155 	}
156 
157 	return ret;
158 }
159 
160 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
161 	.enable = regulator_enable_regmap,
162 	.disable = regulator_disable_regmap,
163 	.is_enabled = regulator_is_enabled_regmap,
164 	.list_voltage = regulator_list_voltage_linear,
165 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
166 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
167 };
168 
169 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
170 	.enable = regulator_enable_regmap,
171 	.disable = regulator_disable_regmap,
172 	.is_enabled = regulator_is_enabled_regmap,
173 	.list_voltage = regulator_list_voltage_linear,
174 };
175 
176 static const struct regulator_ops pfuze100_sw_regulator_ops = {
177 	.list_voltage = regulator_list_voltage_linear,
178 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
179 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
180 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
181 	.set_ramp_delay = pfuze100_set_ramp_delay,
182 };
183 
184 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
185 	.enable = regulator_enable_regmap,
186 	.disable = regulator_disable_regmap,
187 	.is_enabled = regulator_is_enabled_regmap,
188 	.list_voltage = regulator_list_voltage_linear,
189 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
190 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
191 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
192 	.set_ramp_delay = pfuze100_set_ramp_delay,
193 };
194 
195 static const struct regulator_ops pfuze100_swb_regulator_ops = {
196 	.enable = regulator_enable_regmap,
197 	.disable = regulator_disable_regmap,
198 	.is_enabled = regulator_is_enabled_regmap,
199 	.list_voltage = regulator_list_voltage_table,
200 	.map_voltage = regulator_map_voltage_ascend,
201 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
202 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
203 
204 };
205 
206 static const struct regulator_ops pfuze3000_sw_regulator_ops = {
207 	.enable = regulator_enable_regmap,
208 	.disable = regulator_disable_regmap,
209 	.is_enabled = regulator_is_enabled_regmap,
210 	.list_voltage = regulator_list_voltage_table,
211 	.map_voltage = regulator_map_voltage_ascend,
212 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
213 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
214 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
215 	.set_ramp_delay = pfuze100_set_ramp_delay,
216 
217 };
218 
219 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage)	\
220 	[_chip ## _ ## _name] = {	\
221 		.desc = {	\
222 			.name = #_name,	\
223 			.n_voltages = 1,	\
224 			.ops = &pfuze100_fixed_regulator_ops,	\
225 			.type = REGULATOR_VOLTAGE,	\
226 			.id = _chip ## _ ## _name,	\
227 			.owner = THIS_MODULE,	\
228 			.min_uV = (voltage),	\
229 			.enable_reg = (base),	\
230 			.enable_mask = 0x10,	\
231 		},	\
232 	}
233 
234 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step)	\
235 	[_chip ## _ ## _name] = {	\
236 		.desc = {	\
237 			.name = #_name,\
238 			.n_voltages = ((max) - (min)) / (step) + 1,	\
239 			.ops = &pfuze100_sw_regulator_ops,	\
240 			.type = REGULATOR_VOLTAGE,	\
241 			.id = _chip ## _ ## _name,	\
242 			.owner = THIS_MODULE,	\
243 			.min_uV = (min),	\
244 			.uV_step = (step),	\
245 			.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
246 			.vsel_mask = 0x3f,	\
247 			.enable_reg = (base) + PFUZE100_MODE_OFFSET,	\
248 			.enable_mask = 0xf,	\
249 		},	\
250 		.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
251 		.stby_mask = 0x3f,	\
252 		.sw_reg = true,		\
253 	}
254 
255 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages)	\
256 	[_chip ## _ ##  _name] = {	\
257 		.desc = {	\
258 			.name = #_name,	\
259 			.n_voltages = ARRAY_SIZE(voltages),	\
260 			.ops = &pfuze100_swb_regulator_ops,	\
261 			.type = REGULATOR_VOLTAGE,	\
262 			.id = _chip ## _ ## _name,	\
263 			.owner = THIS_MODULE,	\
264 			.volt_table = voltages,	\
265 			.vsel_reg = (base),	\
266 			.vsel_mask = (mask),	\
267 			.enable_reg = (base),	\
268 			.enable_mask = 0x48,	\
269 		},	\
270 	}
271 
272 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step)	\
273 	[_chip ## _ ## _name] = {	\
274 		.desc = {	\
275 			.name = #_name,	\
276 			.n_voltages = ((max) - (min)) / (step) + 1,	\
277 			.ops = &pfuze100_ldo_regulator_ops,	\
278 			.type = REGULATOR_VOLTAGE,	\
279 			.id = _chip ## _ ## _name,	\
280 			.owner = THIS_MODULE,	\
281 			.min_uV = (min),	\
282 			.uV_step = (step),	\
283 			.vsel_reg = (base),	\
284 			.vsel_mask = 0xf,	\
285 			.enable_reg = (base),	\
286 			.enable_mask = 0x10,	\
287 		},	\
288 		.stby_reg = (base),	\
289 		.stby_mask = 0x20,	\
290 	}
291 
292 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages)	\
293 	[_chip ## _ ##  _name] = {	\
294 		.desc = {	\
295 			.name = #_name,	\
296 			.n_voltages = ARRAY_SIZE(voltages),	\
297 			.ops = &pfuze100_swb_regulator_ops,	\
298 			.type = REGULATOR_VOLTAGE,	\
299 			.id = _chip ## _ ## _name,	\
300 			.owner = THIS_MODULE,	\
301 			.volt_table = voltages,	\
302 			.vsel_reg = (base),	\
303 			.vsel_mask = (mask),	\
304 			.enable_reg = (base),	\
305 			.enable_mask = 0x8,	\
306 		},	\
307 	}
308 
309 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step)	{	\
310 	.desc = {	\
311 		.name = #_name,	\
312 		.n_voltages = ((max) - (min)) / (step) + 1,	\
313 		.ops = &pfuze100_ldo_regulator_ops,	\
314 		.type = REGULATOR_VOLTAGE,	\
315 		.id = _chip ## _ ## _name,	\
316 		.owner = THIS_MODULE,	\
317 		.min_uV = (min),	\
318 		.uV_step = (step),	\
319 		.vsel_reg = (base),	\
320 		.vsel_mask = 0x3,	\
321 		.enable_reg = (base),	\
322 		.enable_mask = 0x10,	\
323 	},	\
324 	.stby_reg = (base),	\
325 	.stby_mask = 0x20,	\
326 }
327 
328 /* No linar case for the some switches of PFUZE3000 */
329 #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages)	\
330 	[_chip ## _ ##  _name] = {	\
331 		.desc = {	\
332 			.name = #_name,	\
333 			.n_voltages = ARRAY_SIZE(voltages),	\
334 			.ops = &pfuze3000_sw_regulator_ops,	\
335 			.type = REGULATOR_VOLTAGE,	\
336 			.id = _chip ## _ ## _name,	\
337 			.owner = THIS_MODULE,	\
338 			.volt_table = voltages,	\
339 			.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
340 			.vsel_mask = (mask),	\
341 			.enable_reg = (base) + PFUZE100_MODE_OFFSET,	\
342 			.enable_mask = 0xf,	\
343 			.enable_val = 0x8,	\
344 			.enable_time = 500,	\
345 		},	\
346 		.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
347 		.stby_mask = (mask),	\
348 		.sw_reg = true,		\
349 	}
350 
351 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step)	{	\
352 	.desc = {	\
353 		.name = #_name,\
354 		.n_voltages = ((max) - (min)) / (step) + 1,	\
355 		.ops = &pfuze100_sw_regulator_ops,	\
356 		.type = REGULATOR_VOLTAGE,	\
357 		.id = _chip ## _ ## _name,	\
358 		.owner = THIS_MODULE,	\
359 		.min_uV = (min),	\
360 		.uV_step = (step),	\
361 		.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
362 		.vsel_mask = 0xf,	\
363 	},	\
364 	.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
365 	.stby_mask = 0xf,	\
366 }
367 
368 /* PFUZE100 */
369 static struct pfuze_regulator pfuze100_regulators[] = {
370 	PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
371 	PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
372 	PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
373 	PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
374 	PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
375 	PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
376 	PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
377 	PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
378 	PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
379 	PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
380 	PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
381 	PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
382 	PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
383 	PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
384 	PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
385 	PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
386 };
387 
388 static struct pfuze_regulator pfuze200_regulators[] = {
389 	PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
390 	PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
391 	PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
392 	PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
393 	PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
394 	PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
395 	PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
396 	PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
397 	PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
398 	PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
399 	PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
400 	PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
401 	PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
402 	PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
403 };
404 
405 static struct pfuze_regulator pfuze3000_regulators[] = {
406 	PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
407 	PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
408 	PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
409 	PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
410 	PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
411 	PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
412 	PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
413 	PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
414 	PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
415 	PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
416 	PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
417 	PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
418 	PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
419 };
420 
421 static struct pfuze_regulator pfuze3001_regulators[] = {
422 	PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
423 	PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
424 	PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
425 	PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
426 	PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
427 	PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
428 	PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
429 	PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
430 	PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
431 	PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
432 };
433 
434 /* PFUZE100 */
435 static struct of_regulator_match pfuze100_matches[] = {
436 	{ .name = "sw1ab",	},
437 	{ .name = "sw1c",	},
438 	{ .name = "sw2",	},
439 	{ .name = "sw3a",	},
440 	{ .name = "sw3b",	},
441 	{ .name = "sw4",	},
442 	{ .name = "swbst",	},
443 	{ .name = "vsnvs",	},
444 	{ .name = "vrefddr",	},
445 	{ .name = "vgen1",	},
446 	{ .name = "vgen2",	},
447 	{ .name = "vgen3",	},
448 	{ .name = "vgen4",	},
449 	{ .name = "vgen5",	},
450 	{ .name = "vgen6",	},
451 	{ .name = "coin",	},
452 };
453 
454 /* PFUZE200 */
455 static struct of_regulator_match pfuze200_matches[] = {
456 
457 	{ .name = "sw1ab",	},
458 	{ .name = "sw2",	},
459 	{ .name = "sw3a",	},
460 	{ .name = "sw3b",	},
461 	{ .name = "swbst",	},
462 	{ .name = "vsnvs",	},
463 	{ .name = "vrefddr",	},
464 	{ .name = "vgen1",	},
465 	{ .name = "vgen2",	},
466 	{ .name = "vgen3",	},
467 	{ .name = "vgen4",	},
468 	{ .name = "vgen5",	},
469 	{ .name = "vgen6",	},
470 	{ .name = "coin",	},
471 };
472 
473 /* PFUZE3000 */
474 static struct of_regulator_match pfuze3000_matches[] = {
475 
476 	{ .name = "sw1a",	},
477 	{ .name = "sw1b",	},
478 	{ .name = "sw2",	},
479 	{ .name = "sw3",	},
480 	{ .name = "swbst",	},
481 	{ .name = "vsnvs",	},
482 	{ .name = "vrefddr",	},
483 	{ .name = "vldo1",	},
484 	{ .name = "vldo2",	},
485 	{ .name = "vccsd",	},
486 	{ .name = "v33",	},
487 	{ .name = "vldo3",	},
488 	{ .name = "vldo4",	},
489 };
490 
491 /* PFUZE3001 */
492 static struct of_regulator_match pfuze3001_matches[] = {
493 
494 	{ .name = "sw1",	},
495 	{ .name = "sw2",	},
496 	{ .name = "sw3",	},
497 	{ .name = "vsnvs",	},
498 	{ .name = "vldo1",	},
499 	{ .name = "vldo2",	},
500 	{ .name = "vccsd",	},
501 	{ .name = "v33",	},
502 	{ .name = "vldo3",	},
503 	{ .name = "vldo4",	},
504 };
505 
506 static struct of_regulator_match *pfuze_matches;
507 
508 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
509 {
510 	struct device *dev = chip->dev;
511 	struct device_node *np, *parent;
512 	int ret;
513 
514 	np = of_node_get(dev->of_node);
515 	if (!np)
516 		return -EINVAL;
517 
518 	if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
519 		chip->flags |= PFUZE_FLAG_DISABLE_SW;
520 
521 	parent = of_get_child_by_name(np, "regulators");
522 	if (!parent) {
523 		dev_err(dev, "regulators node not found\n");
524 		return -EINVAL;
525 	}
526 
527 	switch (chip->chip_id) {
528 	case PFUZE3001:
529 		pfuze_matches = pfuze3001_matches;
530 		ret = of_regulator_match(dev, parent, pfuze3001_matches,
531 					 ARRAY_SIZE(pfuze3001_matches));
532 		break;
533 	case PFUZE3000:
534 		pfuze_matches = pfuze3000_matches;
535 		ret = of_regulator_match(dev, parent, pfuze3000_matches,
536 					 ARRAY_SIZE(pfuze3000_matches));
537 		break;
538 	case PFUZE200:
539 		pfuze_matches = pfuze200_matches;
540 		ret = of_regulator_match(dev, parent, pfuze200_matches,
541 					 ARRAY_SIZE(pfuze200_matches));
542 		break;
543 
544 	case PFUZE100:
545 	default:
546 		pfuze_matches = pfuze100_matches;
547 		ret = of_regulator_match(dev, parent, pfuze100_matches,
548 					 ARRAY_SIZE(pfuze100_matches));
549 		break;
550 	}
551 
552 	of_node_put(parent);
553 	if (ret < 0) {
554 		dev_err(dev, "Error parsing regulator init data: %d\n",
555 			ret);
556 		return ret;
557 	}
558 
559 	return 0;
560 }
561 
562 static inline struct regulator_init_data *match_init_data(int index)
563 {
564 	return pfuze_matches[index].init_data;
565 }
566 
567 static inline struct device_node *match_of_node(int index)
568 {
569 	return pfuze_matches[index].of_node;
570 }
571 
572 static struct pfuze_chip *syspm_pfuze_chip;
573 
574 static void pfuze_power_off_prepare(void)
575 {
576 	dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
577 
578 	/* Switch from default mode: APS/APS to APS/Off */
579 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
580 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
581 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
582 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
583 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
584 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
585 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
586 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
587 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
588 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
589 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
590 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
591 
592 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
593 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
594 			   PFUZE100_VGENxSTBY);
595 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
596 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
597 			   PFUZE100_VGENxSTBY);
598 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
599 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
600 			   PFUZE100_VGENxSTBY);
601 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
602 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
603 			   PFUZE100_VGENxSTBY);
604 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
605 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
606 			   PFUZE100_VGENxSTBY);
607 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
608 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
609 			   PFUZE100_VGENxSTBY);
610 }
611 
612 static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
613 {
614 	if (pfuze_chip->chip_id != PFUZE100) {
615 		dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
616 		return -ENODEV;
617 	}
618 
619 	if (pm_power_off_prepare) {
620 		dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
621 		return -EBUSY;
622 	}
623 
624 	if (syspm_pfuze_chip) {
625 		dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
626 		return -EBUSY;
627 	}
628 
629 	syspm_pfuze_chip = pfuze_chip;
630 	pm_power_off_prepare = pfuze_power_off_prepare;
631 
632 	return 0;
633 }
634 
635 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
636 {
637 	unsigned int value;
638 	int ret;
639 
640 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
641 	if (ret)
642 		return ret;
643 
644 	if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
645 		/*
646 		 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
647 		 * as ID=8 in PFUZE100
648 		 */
649 		dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
650 	} else if ((value & 0x0f) != pfuze_chip->chip_id &&
651 		   (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
652 		   (value != pfuze_chip->chip_id)) {
653 		/* device id NOT match with your setting */
654 		dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
655 		return -ENODEV;
656 	}
657 
658 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
659 	if (ret)
660 		return ret;
661 	dev_info(pfuze_chip->dev,
662 		 "Full layer: %x, Metal layer: %x\n",
663 		 (value & 0xf0) >> 4, value & 0x0f);
664 
665 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
666 	if (ret)
667 		return ret;
668 	dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
669 		 (value & 0xc) >> 2, value & 0x3);
670 
671 	return 0;
672 }
673 
674 static const struct regmap_config pfuze_regmap_config = {
675 	.reg_bits = 8,
676 	.val_bits = 8,
677 	.max_register = PFUZE_NUMREGS - 1,
678 	.cache_type = REGCACHE_RBTREE,
679 };
680 
681 static int pfuze100_regulator_probe(struct i2c_client *client,
682 				    const struct i2c_device_id *id)
683 {
684 	struct pfuze_chip *pfuze_chip;
685 	struct regulator_config config = { };
686 	int i, ret;
687 	const struct of_device_id *match;
688 	u32 regulator_num;
689 	u32 sw_check_start, sw_check_end, sw_hi = 0x40;
690 
691 	pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
692 			GFP_KERNEL);
693 	if (!pfuze_chip)
694 		return -ENOMEM;
695 
696 	if (client->dev.of_node) {
697 		match = of_match_device(of_match_ptr(pfuze_dt_ids),
698 				&client->dev);
699 		if (!match) {
700 			dev_err(&client->dev, "Error: No device match found\n");
701 			return -ENODEV;
702 		}
703 		pfuze_chip->chip_id = (int)(long)match->data;
704 	} else if (id) {
705 		pfuze_chip->chip_id = id->driver_data;
706 	} else {
707 		dev_err(&client->dev, "No dts match or id table match found\n");
708 		return -ENODEV;
709 	}
710 
711 	i2c_set_clientdata(client, pfuze_chip);
712 	pfuze_chip->dev = &client->dev;
713 
714 	pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
715 	if (IS_ERR(pfuze_chip->regmap)) {
716 		ret = PTR_ERR(pfuze_chip->regmap);
717 		dev_err(&client->dev,
718 			"regmap allocation failed with err %d\n", ret);
719 		return ret;
720 	}
721 
722 	ret = pfuze_identify(pfuze_chip);
723 	if (ret) {
724 		dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
725 		return ret;
726 	}
727 
728 	/* use the right regulators after identify the right device */
729 	switch (pfuze_chip->chip_id) {
730 	case PFUZE3001:
731 		pfuze_chip->pfuze_regulators = pfuze3001_regulators;
732 		regulator_num = ARRAY_SIZE(pfuze3001_regulators);
733 		sw_check_start = PFUZE3001_SW2;
734 		sw_check_end = PFUZE3001_SW2;
735 		sw_hi = 1 << 3;
736 		break;
737 	case PFUZE3000:
738 		pfuze_chip->pfuze_regulators = pfuze3000_regulators;
739 		regulator_num = ARRAY_SIZE(pfuze3000_regulators);
740 		sw_check_start = PFUZE3000_SW2;
741 		sw_check_end = PFUZE3000_SW2;
742 		sw_hi = 1 << 3;
743 		break;
744 	case PFUZE200:
745 		pfuze_chip->pfuze_regulators = pfuze200_regulators;
746 		regulator_num = ARRAY_SIZE(pfuze200_regulators);
747 		sw_check_start = PFUZE200_SW2;
748 		sw_check_end = PFUZE200_SW3B;
749 		break;
750 	case PFUZE100:
751 	default:
752 		pfuze_chip->pfuze_regulators = pfuze100_regulators;
753 		regulator_num = ARRAY_SIZE(pfuze100_regulators);
754 		sw_check_start = PFUZE100_SW2;
755 		sw_check_end = PFUZE100_SW4;
756 		break;
757 	}
758 	dev_info(&client->dev, "pfuze%s found.\n",
759 		(pfuze_chip->chip_id == PFUZE100) ? "100" :
760 		(((pfuze_chip->chip_id == PFUZE200) ? "200" :
761 		((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
762 
763 	memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
764 		sizeof(pfuze_chip->regulator_descs));
765 
766 	ret = pfuze_parse_regulators_dt(pfuze_chip);
767 	if (ret)
768 		return ret;
769 
770 	for (i = 0; i < regulator_num; i++) {
771 		struct regulator_init_data *init_data;
772 		struct regulator_desc *desc;
773 		int val;
774 
775 		desc = &pfuze_chip->regulator_descs[i].desc;
776 
777 		init_data = match_init_data(i);
778 
779 		/* SW2~SW4 high bit check and modify the voltage value table */
780 		if (i >= sw_check_start && i <= sw_check_end) {
781 			ret = regmap_read(pfuze_chip->regmap,
782 						desc->vsel_reg, &val);
783 			if (ret) {
784 				dev_err(&client->dev, "Fails to read from the register.\n");
785 				return ret;
786 			}
787 
788 			if (val & sw_hi) {
789 				if (pfuze_chip->chip_id == PFUZE3000 ||
790 					pfuze_chip->chip_id == PFUZE3001) {
791 					desc->volt_table = pfuze3000_sw2hi;
792 					desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
793 				} else {
794 					desc->min_uV = 800000;
795 					desc->uV_step = 50000;
796 					desc->n_voltages = 51;
797 				}
798 			}
799 		}
800 
801 		/*
802 		 * Allow SW regulators to turn off. Checking it trough a flag is
803 		 * a workaround to keep the backward compatibility with existing
804 		 * old dtb's which may relay on the fact that we didn't disable
805 		 * the switched regulator till yet.
806 		 */
807 		if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
808 			if (pfuze_chip->chip_id == PFUZE100 ||
809 				pfuze_chip->chip_id == PFUZE200) {
810 				if (pfuze_chip->regulator_descs[i].sw_reg) {
811 					desc->ops = &pfuze100_sw_disable_regulator_ops;
812 					desc->enable_val = 0x8;
813 					desc->disable_val = 0x0;
814 					desc->enable_time = 500;
815 				}
816 			}
817 		}
818 
819 		config.dev = &client->dev;
820 		config.init_data = init_data;
821 		config.driver_data = pfuze_chip;
822 		config.of_node = match_of_node(i);
823 
824 		pfuze_chip->regulators[i] =
825 			devm_regulator_register(&client->dev, desc, &config);
826 		if (IS_ERR(pfuze_chip->regulators[i])) {
827 			dev_err(&client->dev, "register regulator%s failed\n",
828 				pfuze_chip->pfuze_regulators[i].desc.name);
829 			return PTR_ERR(pfuze_chip->regulators[i]);
830 		}
831 	}
832 
833 	if (of_property_read_bool(client->dev.of_node,
834 				  "fsl,pmic-stby-poweroff"))
835 		return pfuze_power_off_prepare_init(pfuze_chip);
836 
837 	return 0;
838 }
839 
840 static int pfuze100_regulator_remove(struct i2c_client *client)
841 {
842 	if (syspm_pfuze_chip) {
843 		syspm_pfuze_chip = NULL;
844 		pm_power_off_prepare = NULL;
845 	}
846 
847 	return 0;
848 }
849 
850 static struct i2c_driver pfuze_driver = {
851 	.driver = {
852 		.name = "pfuze100-regulator",
853 		.of_match_table = pfuze_dt_ids,
854 	},
855 	.probe = pfuze100_regulator_probe,
856 	.remove = pfuze100_regulator_remove,
857 };
858 module_i2c_driver(pfuze_driver);
859 
860 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
861 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
862 MODULE_LICENSE("GPL v2");
863