1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/err.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/regulator/of_regulator.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/regulator/pfuze100.h>
16 #include <linux/i2c.h>
17 #include <linux/slab.h>
18 #include <linux/regmap.h>
19 
20 #define PFUZE_FLAG_DISABLE_SW	BIT(1)
21 
22 #define PFUZE_NUMREGS		128
23 #define PFUZE100_VOL_OFFSET	0
24 #define PFUZE100_STANDBY_OFFSET	1
25 #define PFUZE100_MODE_OFFSET	3
26 #define PFUZE100_CONF_OFFSET	4
27 
28 #define PFUZE100_DEVICEID	0x0
29 #define PFUZE100_REVID		0x3
30 #define PFUZE100_FABID		0x4
31 
32 #define PFUZE100_COINVOL	0x1a
33 #define PFUZE100_SW1ABVOL	0x20
34 #define PFUZE100_SW1ABMODE	0x23
35 #define PFUZE100_SW1CVOL	0x2e
36 #define PFUZE100_SW1CMODE	0x31
37 #define PFUZE100_SW2VOL		0x35
38 #define PFUZE100_SW2MODE	0x38
39 #define PFUZE100_SW3AVOL	0x3c
40 #define PFUZE100_SW3AMODE	0x3f
41 #define PFUZE100_SW3BVOL	0x43
42 #define PFUZE100_SW3BMODE	0x46
43 #define PFUZE100_SW4VOL		0x4a
44 #define PFUZE100_SW4MODE	0x4d
45 #define PFUZE100_SWBSTCON1	0x66
46 #define PFUZE100_VREFDDRCON	0x6a
47 #define PFUZE100_VSNVSVOL	0x6b
48 #define PFUZE100_VGEN1VOL	0x6c
49 #define PFUZE100_VGEN2VOL	0x6d
50 #define PFUZE100_VGEN3VOL	0x6e
51 #define PFUZE100_VGEN4VOL	0x6f
52 #define PFUZE100_VGEN5VOL	0x70
53 #define PFUZE100_VGEN6VOL	0x71
54 
55 #define PFUZE100_SWxMODE_MASK	0xf
56 #define PFUZE100_SWxMODE_APS_APS	0x8
57 #define PFUZE100_SWxMODE_APS_OFF	0x4
58 
59 #define PFUZE100_VGENxLPWR	BIT(6)
60 #define PFUZE100_VGENxSTBY	BIT(5)
61 
62 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
63 
64 struct pfuze_regulator {
65 	struct regulator_desc desc;
66 	unsigned char stby_reg;
67 	unsigned char stby_mask;
68 	bool sw_reg;
69 };
70 
71 struct pfuze_chip {
72 	int	chip_id;
73 	int     flags;
74 	struct regmap *regmap;
75 	struct device *dev;
76 	struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
77 	struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
78 	struct pfuze_regulator *pfuze_regulators;
79 };
80 
81 static const int pfuze100_swbst[] = {
82 	5000000, 5050000, 5100000, 5150000,
83 };
84 
85 static const int pfuze100_vsnvs[] = {
86 	1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
87 };
88 
89 static const int pfuze100_coin[] = {
90 	2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
91 };
92 
93 static const int pfuze3000_sw1a[] = {
94 	700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
95 	900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
96 	1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
97 	1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
98 };
99 
100 static const int pfuze3000_sw2lo[] = {
101 	1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
102 };
103 
104 static const int pfuze3000_sw2hi[] = {
105 	2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
106 };
107 
108 static const struct i2c_device_id pfuze_device_id[] = {
109 	{.name = "pfuze100", .driver_data = PFUZE100},
110 	{.name = "pfuze200", .driver_data = PFUZE200},
111 	{.name = "pfuze3000", .driver_data = PFUZE3000},
112 	{.name = "pfuze3001", .driver_data = PFUZE3001},
113 	{ }
114 };
115 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
116 
117 static const struct of_device_id pfuze_dt_ids[] = {
118 	{ .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
119 	{ .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
120 	{ .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
121 	{ .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
122 	{ }
123 };
124 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
125 
126 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
127 {
128 	struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
129 	int id = rdev_get_id(rdev);
130 	bool reg_has_ramp_delay;
131 	unsigned int ramp_bits;
132 	int ret;
133 
134 	switch (pfuze100->chip_id) {
135 	case PFUZE3001:
136 		/* no dynamic voltage scaling for PF3001 */
137 		reg_has_ramp_delay = false;
138 		break;
139 	case PFUZE3000:
140 		reg_has_ramp_delay = (id < PFUZE3000_SWBST);
141 		break;
142 	case PFUZE200:
143 		reg_has_ramp_delay = (id < PFUZE200_SWBST);
144 		break;
145 	case PFUZE100:
146 	default:
147 		reg_has_ramp_delay = (id < PFUZE100_SWBST);
148 		break;
149 	}
150 
151 	if (reg_has_ramp_delay) {
152 		ramp_delay = 12500 / ramp_delay;
153 		ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
154 		ret = regmap_update_bits(pfuze100->regmap,
155 					 rdev->desc->vsel_reg + 4,
156 					 0xc0, ramp_bits << 6);
157 		if (ret < 0)
158 			dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
159 	} else {
160 		ret = -EACCES;
161 	}
162 
163 	return ret;
164 }
165 
166 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
167 	.enable = regulator_enable_regmap,
168 	.disable = regulator_disable_regmap,
169 	.is_enabled = regulator_is_enabled_regmap,
170 	.list_voltage = regulator_list_voltage_linear,
171 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
172 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
173 };
174 
175 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
176 	.enable = regulator_enable_regmap,
177 	.disable = regulator_disable_regmap,
178 	.is_enabled = regulator_is_enabled_regmap,
179 	.list_voltage = regulator_list_voltage_linear,
180 };
181 
182 static const struct regulator_ops pfuze100_sw_regulator_ops = {
183 	.list_voltage = regulator_list_voltage_linear,
184 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
185 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
186 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
187 	.set_ramp_delay = pfuze100_set_ramp_delay,
188 };
189 
190 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
191 	.enable = regulator_enable_regmap,
192 	.disable = regulator_disable_regmap,
193 	.is_enabled = regulator_is_enabled_regmap,
194 	.list_voltage = regulator_list_voltage_linear,
195 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
196 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
197 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
198 	.set_ramp_delay = pfuze100_set_ramp_delay,
199 };
200 
201 static const struct regulator_ops pfuze100_swb_regulator_ops = {
202 	.enable = regulator_enable_regmap,
203 	.disable = regulator_disable_regmap,
204 	.is_enabled = regulator_is_enabled_regmap,
205 	.list_voltage = regulator_list_voltage_table,
206 	.map_voltage = regulator_map_voltage_ascend,
207 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
208 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
209 
210 };
211 
212 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage)	\
213 	[_chip ## _ ## _name] = {	\
214 		.desc = {	\
215 			.name = #_name,	\
216 			.n_voltages = 1,	\
217 			.ops = &pfuze100_fixed_regulator_ops,	\
218 			.type = REGULATOR_VOLTAGE,	\
219 			.id = _chip ## _ ## _name,	\
220 			.owner = THIS_MODULE,	\
221 			.min_uV = (voltage),	\
222 			.enable_reg = (base),	\
223 			.enable_mask = 0x10,	\
224 		},	\
225 	}
226 
227 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step)	\
228 	[_chip ## _ ## _name] = {	\
229 		.desc = {	\
230 			.name = #_name,\
231 			.n_voltages = ((max) - (min)) / (step) + 1,	\
232 			.ops = &pfuze100_sw_regulator_ops,	\
233 			.type = REGULATOR_VOLTAGE,	\
234 			.id = _chip ## _ ## _name,	\
235 			.owner = THIS_MODULE,	\
236 			.min_uV = (min),	\
237 			.uV_step = (step),	\
238 			.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
239 			.vsel_mask = 0x3f,	\
240 			.enable_reg = (base) + PFUZE100_MODE_OFFSET,	\
241 			.enable_mask = 0xf,	\
242 		},	\
243 		.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
244 		.stby_mask = 0x3f,	\
245 		.sw_reg = true,		\
246 	}
247 
248 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages)	\
249 	[_chip ## _ ##  _name] = {	\
250 		.desc = {	\
251 			.name = #_name,	\
252 			.n_voltages = ARRAY_SIZE(voltages),	\
253 			.ops = &pfuze100_swb_regulator_ops,	\
254 			.type = REGULATOR_VOLTAGE,	\
255 			.id = _chip ## _ ## _name,	\
256 			.owner = THIS_MODULE,	\
257 			.volt_table = voltages,	\
258 			.vsel_reg = (base),	\
259 			.vsel_mask = (mask),	\
260 			.enable_reg = (base),	\
261 			.enable_mask = 0x48,	\
262 		},	\
263 	}
264 
265 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step)	\
266 	[_chip ## _ ## _name] = {	\
267 		.desc = {	\
268 			.name = #_name,	\
269 			.n_voltages = ((max) - (min)) / (step) + 1,	\
270 			.ops = &pfuze100_ldo_regulator_ops,	\
271 			.type = REGULATOR_VOLTAGE,	\
272 			.id = _chip ## _ ## _name,	\
273 			.owner = THIS_MODULE,	\
274 			.min_uV = (min),	\
275 			.uV_step = (step),	\
276 			.vsel_reg = (base),	\
277 			.vsel_mask = 0xf,	\
278 			.enable_reg = (base),	\
279 			.enable_mask = 0x10,	\
280 		},	\
281 		.stby_reg = (base),	\
282 		.stby_mask = 0x20,	\
283 	}
284 
285 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages)	\
286 	[_chip ## _ ##  _name] = {	\
287 		.desc = {	\
288 			.name = #_name,	\
289 			.n_voltages = ARRAY_SIZE(voltages),	\
290 			.ops = &pfuze100_swb_regulator_ops,	\
291 			.type = REGULATOR_VOLTAGE,	\
292 			.id = _chip ## _ ## _name,	\
293 			.owner = THIS_MODULE,	\
294 			.volt_table = voltages,	\
295 			.vsel_reg = (base),	\
296 			.vsel_mask = (mask),	\
297 			.enable_reg = (base),	\
298 			.enable_mask = 0x8,	\
299 		},	\
300 	}
301 
302 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step)	{	\
303 	.desc = {	\
304 		.name = #_name,	\
305 		.n_voltages = ((max) - (min)) / (step) + 1,	\
306 		.ops = &pfuze100_ldo_regulator_ops,	\
307 		.type = REGULATOR_VOLTAGE,	\
308 		.id = _chip ## _ ## _name,	\
309 		.owner = THIS_MODULE,	\
310 		.min_uV = (min),	\
311 		.uV_step = (step),	\
312 		.vsel_reg = (base),	\
313 		.vsel_mask = 0x3,	\
314 		.enable_reg = (base),	\
315 		.enable_mask = 0x10,	\
316 	},	\
317 	.stby_reg = (base),	\
318 	.stby_mask = 0x20,	\
319 }
320 
321 
322 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step)	{	\
323 	.desc = {	\
324 		.name = #_name,\
325 		.n_voltages = ((max) - (min)) / (step) + 1,	\
326 		.ops = &pfuze100_sw_regulator_ops,	\
327 		.type = REGULATOR_VOLTAGE,	\
328 		.id = _chip ## _ ## _name,	\
329 		.owner = THIS_MODULE,	\
330 		.min_uV = (min),	\
331 		.uV_step = (step),	\
332 		.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
333 		.vsel_mask = 0x7,	\
334 	},	\
335 	.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
336 	.stby_mask = 0x7,	\
337 }
338 
339 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step)	{	\
340 	.desc = {	\
341 		.name = #_name,\
342 		.n_voltages = ((max) - (min)) / (step) + 1,	\
343 		.ops = &pfuze100_sw_regulator_ops,	\
344 		.type = REGULATOR_VOLTAGE,	\
345 		.id = _chip ## _ ## _name,	\
346 		.owner = THIS_MODULE,	\
347 		.min_uV = (min),	\
348 		.uV_step = (step),	\
349 		.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
350 		.vsel_mask = 0xf,	\
351 	},	\
352 	.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
353 	.stby_mask = 0xf,	\
354 }
355 
356 /* PFUZE100 */
357 static struct pfuze_regulator pfuze100_regulators[] = {
358 	PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
359 	PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
360 	PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
361 	PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
362 	PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
363 	PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
364 	PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
365 	PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
366 	PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
367 	PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
368 	PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
369 	PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
370 	PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
371 	PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
372 	PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
373 	PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
374 };
375 
376 static struct pfuze_regulator pfuze200_regulators[] = {
377 	PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
378 	PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
379 	PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
380 	PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
381 	PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
382 	PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
383 	PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
384 	PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
385 	PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
386 	PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
387 	PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
388 	PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
389 	PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
390 	PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
391 };
392 
393 static struct pfuze_regulator pfuze3000_regulators[] = {
394 	PFUZE100_SWB_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
395 	PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
396 	PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
397 	PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
398 	PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
399 	PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
400 	PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
401 	PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
402 	PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
403 	PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
404 	PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
405 	PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
406 	PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
407 };
408 
409 static struct pfuze_regulator pfuze3001_regulators[] = {
410 	PFUZE100_SWB_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
411 	PFUZE100_SWB_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
412 	PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
413 	PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
414 	PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
415 	PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
416 	PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
417 	PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
418 	PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
419 	PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
420 };
421 
422 #ifdef CONFIG_OF
423 /* PFUZE100 */
424 static struct of_regulator_match pfuze100_matches[] = {
425 	{ .name = "sw1ab",	},
426 	{ .name = "sw1c",	},
427 	{ .name = "sw2",	},
428 	{ .name = "sw3a",	},
429 	{ .name = "sw3b",	},
430 	{ .name = "sw4",	},
431 	{ .name = "swbst",	},
432 	{ .name = "vsnvs",	},
433 	{ .name = "vrefddr",	},
434 	{ .name = "vgen1",	},
435 	{ .name = "vgen2",	},
436 	{ .name = "vgen3",	},
437 	{ .name = "vgen4",	},
438 	{ .name = "vgen5",	},
439 	{ .name = "vgen6",	},
440 	{ .name = "coin",	},
441 };
442 
443 /* PFUZE200 */
444 static struct of_regulator_match pfuze200_matches[] = {
445 
446 	{ .name = "sw1ab",	},
447 	{ .name = "sw2",	},
448 	{ .name = "sw3a",	},
449 	{ .name = "sw3b",	},
450 	{ .name = "swbst",	},
451 	{ .name = "vsnvs",	},
452 	{ .name = "vrefddr",	},
453 	{ .name = "vgen1",	},
454 	{ .name = "vgen2",	},
455 	{ .name = "vgen3",	},
456 	{ .name = "vgen4",	},
457 	{ .name = "vgen5",	},
458 	{ .name = "vgen6",	},
459 	{ .name = "coin",	},
460 };
461 
462 /* PFUZE3000 */
463 static struct of_regulator_match pfuze3000_matches[] = {
464 
465 	{ .name = "sw1a",	},
466 	{ .name = "sw1b",	},
467 	{ .name = "sw2",	},
468 	{ .name = "sw3",	},
469 	{ .name = "swbst",	},
470 	{ .name = "vsnvs",	},
471 	{ .name = "vrefddr",	},
472 	{ .name = "vldo1",	},
473 	{ .name = "vldo2",	},
474 	{ .name = "vccsd",	},
475 	{ .name = "v33",	},
476 	{ .name = "vldo3",	},
477 	{ .name = "vldo4",	},
478 };
479 
480 /* PFUZE3001 */
481 static struct of_regulator_match pfuze3001_matches[] = {
482 
483 	{ .name = "sw1",	},
484 	{ .name = "sw2",	},
485 	{ .name = "sw3",	},
486 	{ .name = "vsnvs",	},
487 	{ .name = "vldo1",	},
488 	{ .name = "vldo2",	},
489 	{ .name = "vccsd",	},
490 	{ .name = "v33",	},
491 	{ .name = "vldo3",	},
492 	{ .name = "vldo4",	},
493 };
494 
495 static struct of_regulator_match *pfuze_matches;
496 
497 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
498 {
499 	struct device *dev = chip->dev;
500 	struct device_node *np, *parent;
501 	int ret;
502 
503 	np = of_node_get(dev->of_node);
504 	if (!np)
505 		return -EINVAL;
506 
507 	if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
508 		chip->flags |= PFUZE_FLAG_DISABLE_SW;
509 
510 	parent = of_get_child_by_name(np, "regulators");
511 	if (!parent) {
512 		dev_err(dev, "regulators node not found\n");
513 		return -EINVAL;
514 	}
515 
516 	switch (chip->chip_id) {
517 	case PFUZE3001:
518 		pfuze_matches = pfuze3001_matches;
519 		ret = of_regulator_match(dev, parent, pfuze3001_matches,
520 					 ARRAY_SIZE(pfuze3001_matches));
521 		break;
522 	case PFUZE3000:
523 		pfuze_matches = pfuze3000_matches;
524 		ret = of_regulator_match(dev, parent, pfuze3000_matches,
525 					 ARRAY_SIZE(pfuze3000_matches));
526 		break;
527 	case PFUZE200:
528 		pfuze_matches = pfuze200_matches;
529 		ret = of_regulator_match(dev, parent, pfuze200_matches,
530 					 ARRAY_SIZE(pfuze200_matches));
531 		break;
532 
533 	case PFUZE100:
534 	default:
535 		pfuze_matches = pfuze100_matches;
536 		ret = of_regulator_match(dev, parent, pfuze100_matches,
537 					 ARRAY_SIZE(pfuze100_matches));
538 		break;
539 	}
540 
541 	of_node_put(parent);
542 	if (ret < 0) {
543 		dev_err(dev, "Error parsing regulator init data: %d\n",
544 			ret);
545 		return ret;
546 	}
547 
548 	return 0;
549 }
550 
551 static inline struct regulator_init_data *match_init_data(int index)
552 {
553 	return pfuze_matches[index].init_data;
554 }
555 
556 static inline struct device_node *match_of_node(int index)
557 {
558 	return pfuze_matches[index].of_node;
559 }
560 #else
561 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
562 {
563 	return 0;
564 }
565 
566 static inline struct regulator_init_data *match_init_data(int index)
567 {
568 	return NULL;
569 }
570 
571 static inline struct device_node *match_of_node(int index)
572 {
573 	return NULL;
574 }
575 #endif
576 
577 static struct pfuze_chip *syspm_pfuze_chip;
578 
579 static void pfuze_power_off_prepare(void)
580 {
581 	dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
582 
583 	/* Switch from default mode: APS/APS to APS/Off */
584 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
585 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
586 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
587 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
588 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
589 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
590 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
591 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
592 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
593 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
594 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
595 			   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
596 
597 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
598 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
599 			   PFUZE100_VGENxSTBY);
600 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
601 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
602 			   PFUZE100_VGENxSTBY);
603 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
604 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
605 			   PFUZE100_VGENxSTBY);
606 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
607 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
608 			   PFUZE100_VGENxSTBY);
609 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
610 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
611 			   PFUZE100_VGENxSTBY);
612 	regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
613 			   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
614 			   PFUZE100_VGENxSTBY);
615 }
616 
617 static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
618 {
619 	if (pfuze_chip->chip_id != PFUZE100) {
620 		dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
621 		return -ENODEV;
622 	}
623 
624 	if (pm_power_off_prepare) {
625 		dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
626 		return -EBUSY;
627 	}
628 
629 	if (syspm_pfuze_chip) {
630 		dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
631 		return -EBUSY;
632 	}
633 
634 	syspm_pfuze_chip = pfuze_chip;
635 	pm_power_off_prepare = pfuze_power_off_prepare;
636 
637 	return 0;
638 }
639 
640 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
641 {
642 	unsigned int value;
643 	int ret;
644 
645 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
646 	if (ret)
647 		return ret;
648 
649 	if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
650 		/*
651 		 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
652 		 * as ID=8 in PFUZE100
653 		 */
654 		dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
655 	} else if ((value & 0x0f) != pfuze_chip->chip_id &&
656 		   (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
657 		   (value != pfuze_chip->chip_id)) {
658 		/* device id NOT match with your setting */
659 		dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
660 		return -ENODEV;
661 	}
662 
663 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
664 	if (ret)
665 		return ret;
666 	dev_info(pfuze_chip->dev,
667 		 "Full layer: %x, Metal layer: %x\n",
668 		 (value & 0xf0) >> 4, value & 0x0f);
669 
670 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
671 	if (ret)
672 		return ret;
673 	dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
674 		 (value & 0xc) >> 2, value & 0x3);
675 
676 	return 0;
677 }
678 
679 static const struct regmap_config pfuze_regmap_config = {
680 	.reg_bits = 8,
681 	.val_bits = 8,
682 	.max_register = PFUZE_NUMREGS - 1,
683 	.cache_type = REGCACHE_RBTREE,
684 };
685 
686 static int pfuze100_regulator_probe(struct i2c_client *client,
687 				    const struct i2c_device_id *id)
688 {
689 	struct pfuze_chip *pfuze_chip;
690 	struct pfuze_regulator_platform_data *pdata =
691 	    dev_get_platdata(&client->dev);
692 	struct regulator_config config = { };
693 	int i, ret;
694 	const struct of_device_id *match;
695 	u32 regulator_num;
696 	u32 sw_check_start, sw_check_end, sw_hi = 0x40;
697 
698 	pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
699 			GFP_KERNEL);
700 	if (!pfuze_chip)
701 		return -ENOMEM;
702 
703 	if (client->dev.of_node) {
704 		match = of_match_device(of_match_ptr(pfuze_dt_ids),
705 				&client->dev);
706 		if (!match) {
707 			dev_err(&client->dev, "Error: No device match found\n");
708 			return -ENODEV;
709 		}
710 		pfuze_chip->chip_id = (int)(long)match->data;
711 	} else if (id) {
712 		pfuze_chip->chip_id = id->driver_data;
713 	} else {
714 		dev_err(&client->dev, "No dts match or id table match found\n");
715 		return -ENODEV;
716 	}
717 
718 	i2c_set_clientdata(client, pfuze_chip);
719 	pfuze_chip->dev = &client->dev;
720 
721 	pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
722 	if (IS_ERR(pfuze_chip->regmap)) {
723 		ret = PTR_ERR(pfuze_chip->regmap);
724 		dev_err(&client->dev,
725 			"regmap allocation failed with err %d\n", ret);
726 		return ret;
727 	}
728 
729 	ret = pfuze_identify(pfuze_chip);
730 	if (ret) {
731 		dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
732 		return ret;
733 	}
734 
735 	/* use the right regulators after identify the right device */
736 	switch (pfuze_chip->chip_id) {
737 	case PFUZE3001:
738 		pfuze_chip->pfuze_regulators = pfuze3001_regulators;
739 		regulator_num = ARRAY_SIZE(pfuze3001_regulators);
740 		sw_check_start = PFUZE3001_SW2;
741 		sw_check_end = PFUZE3001_SW2;
742 		sw_hi = 1 << 3;
743 		break;
744 	case PFUZE3000:
745 		pfuze_chip->pfuze_regulators = pfuze3000_regulators;
746 		regulator_num = ARRAY_SIZE(pfuze3000_regulators);
747 		sw_check_start = PFUZE3000_SW2;
748 		sw_check_end = PFUZE3000_SW2;
749 		sw_hi = 1 << 3;
750 		break;
751 	case PFUZE200:
752 		pfuze_chip->pfuze_regulators = pfuze200_regulators;
753 		regulator_num = ARRAY_SIZE(pfuze200_regulators);
754 		sw_check_start = PFUZE200_SW2;
755 		sw_check_end = PFUZE200_SW3B;
756 		break;
757 	case PFUZE100:
758 	default:
759 		pfuze_chip->pfuze_regulators = pfuze100_regulators;
760 		regulator_num = ARRAY_SIZE(pfuze100_regulators);
761 		sw_check_start = PFUZE100_SW2;
762 		sw_check_end = PFUZE100_SW4;
763 		break;
764 	}
765 	dev_info(&client->dev, "pfuze%s found.\n",
766 		(pfuze_chip->chip_id == PFUZE100) ? "100" :
767 		(((pfuze_chip->chip_id == PFUZE200) ? "200" :
768 		((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
769 
770 	memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
771 		sizeof(pfuze_chip->regulator_descs));
772 
773 	ret = pfuze_parse_regulators_dt(pfuze_chip);
774 	if (ret)
775 		return ret;
776 
777 	for (i = 0; i < regulator_num; i++) {
778 		struct regulator_init_data *init_data;
779 		struct regulator_desc *desc;
780 		int val;
781 
782 		desc = &pfuze_chip->regulator_descs[i].desc;
783 
784 		if (pdata)
785 			init_data = pdata->init_data[i];
786 		else
787 			init_data = match_init_data(i);
788 
789 		/* SW2~SW4 high bit check and modify the voltage value table */
790 		if (i >= sw_check_start && i <= sw_check_end) {
791 			regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
792 			if (val & sw_hi) {
793 				if (pfuze_chip->chip_id == PFUZE3000 ||
794 					pfuze_chip->chip_id == PFUZE3001) {
795 					desc->volt_table = pfuze3000_sw2hi;
796 					desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
797 				} else {
798 					desc->min_uV = 800000;
799 					desc->uV_step = 50000;
800 					desc->n_voltages = 51;
801 				}
802 			}
803 		}
804 
805 		/*
806 		 * Allow SW regulators to turn off. Checking it trough a flag is
807 		 * a workaround to keep the backward compatibility with existing
808 		 * old dtb's which may relay on the fact that we didn't disable
809 		 * the switched regulator till yet.
810 		 */
811 		if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
812 			if (pfuze_chip->regulator_descs[i].sw_reg) {
813 				desc->ops = &pfuze100_sw_disable_regulator_ops;
814 				desc->enable_val = 0x8;
815 				desc->disable_val = 0x0;
816 				desc->enable_time = 500;
817 			}
818 		}
819 
820 		config.dev = &client->dev;
821 		config.init_data = init_data;
822 		config.driver_data = pfuze_chip;
823 		config.of_node = match_of_node(i);
824 
825 		pfuze_chip->regulators[i] =
826 			devm_regulator_register(&client->dev, desc, &config);
827 		if (IS_ERR(pfuze_chip->regulators[i])) {
828 			dev_err(&client->dev, "register regulator%s failed\n",
829 				pfuze_chip->pfuze_regulators[i].desc.name);
830 			return PTR_ERR(pfuze_chip->regulators[i]);
831 		}
832 	}
833 
834 	if (of_property_read_bool(client->dev.of_node,
835 				  "fsl,pmic-stby-poweroff"))
836 		return pfuze_power_off_prepare_init(pfuze_chip);
837 
838 	return 0;
839 }
840 
841 static int pfuze100_regulator_remove(struct i2c_client *client)
842 {
843 	if (syspm_pfuze_chip) {
844 		syspm_pfuze_chip = NULL;
845 		pm_power_off_prepare = NULL;
846 	}
847 
848 	return 0;
849 }
850 
851 static struct i2c_driver pfuze_driver = {
852 	.id_table = pfuze_device_id,
853 	.driver = {
854 		.name = "pfuze100-regulator",
855 		.of_match_table = pfuze_dt_ids,
856 	},
857 	.probe = pfuze100_regulator_probe,
858 	.remove = pfuze100_regulator_remove,
859 };
860 module_i2c_driver(pfuze_driver);
861 
862 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
863 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
864 MODULE_LICENSE("GPL v2");
865