12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
239b1772aSDaniel Ribeiro /*
339b1772aSDaniel Ribeiro * PCAP2 Regulator Driver
439b1772aSDaniel Ribeiro *
539b1772aSDaniel Ribeiro * Copyright (c) 2009 Daniel Ribeiro <drwyrm@gmail.com>
639b1772aSDaniel Ribeiro */
739b1772aSDaniel Ribeiro
839b1772aSDaniel Ribeiro #include <linux/kernel.h>
939b1772aSDaniel Ribeiro #include <linux/module.h>
1039b1772aSDaniel Ribeiro #include <linux/init.h>
1139b1772aSDaniel Ribeiro #include <linux/err.h>
1239b1772aSDaniel Ribeiro #include <linux/platform_device.h>
1339b1772aSDaniel Ribeiro #include <linux/regulator/driver.h>
1439b1772aSDaniel Ribeiro #include <linux/regulator/machine.h>
1539b1772aSDaniel Ribeiro #include <linux/mfd/ezx-pcap.h>
1639b1772aSDaniel Ribeiro
17c49af956SAxel Lin static const unsigned int V1_table[] = {
18c49af956SAxel Lin 2775000, 1275000, 1600000, 1725000, 1825000, 1925000, 2075000, 2275000,
1939b1772aSDaniel Ribeiro };
2039b1772aSDaniel Ribeiro
21c49af956SAxel Lin static const unsigned int V2_table[] = {
22c49af956SAxel Lin 2500000, 2775000,
2339b1772aSDaniel Ribeiro };
2439b1772aSDaniel Ribeiro
25c49af956SAxel Lin static const unsigned int V3_table[] = {
26c49af956SAxel Lin 1075000, 1275000, 1550000, 1725000, 1876000, 1950000, 2075000, 2275000,
2739b1772aSDaniel Ribeiro };
2839b1772aSDaniel Ribeiro
29c49af956SAxel Lin static const unsigned int V4_table[] = {
30c49af956SAxel Lin 1275000, 1550000, 1725000, 1875000, 1950000, 2075000, 2275000, 2775000,
3139b1772aSDaniel Ribeiro };
3239b1772aSDaniel Ribeiro
33c49af956SAxel Lin static const unsigned int V5_table[] = {
34c49af956SAxel Lin 1875000, 2275000, 2475000, 2775000,
3539b1772aSDaniel Ribeiro };
3639b1772aSDaniel Ribeiro
37c49af956SAxel Lin static const unsigned int V6_table[] = {
38c49af956SAxel Lin 2475000, 2775000,
3939b1772aSDaniel Ribeiro };
4039b1772aSDaniel Ribeiro
41c49af956SAxel Lin static const unsigned int V7_table[] = {
42c49af956SAxel Lin 1875000, 2775000,
4339b1772aSDaniel Ribeiro };
4439b1772aSDaniel Ribeiro
4539b1772aSDaniel Ribeiro #define V8_table V4_table
4639b1772aSDaniel Ribeiro
47c49af956SAxel Lin static const unsigned int V9_table[] = {
48c49af956SAxel Lin 1575000, 1875000, 2475000, 2775000,
4939b1772aSDaniel Ribeiro };
5039b1772aSDaniel Ribeiro
51c49af956SAxel Lin static const unsigned int V10_table[] = {
52c49af956SAxel Lin 5000000,
5339b1772aSDaniel Ribeiro };
5439b1772aSDaniel Ribeiro
55c49af956SAxel Lin static const unsigned int VAUX1_table[] = {
56c49af956SAxel Lin 1875000, 2475000, 2775000, 3000000,
5739b1772aSDaniel Ribeiro };
5839b1772aSDaniel Ribeiro
5939b1772aSDaniel Ribeiro #define VAUX2_table VAUX1_table
6039b1772aSDaniel Ribeiro
61c49af956SAxel Lin static const unsigned int VAUX3_table[] = {
62c49af956SAxel Lin 1200000, 1200000, 1200000, 1200000, 1400000, 1600000, 1800000, 2000000,
63c49af956SAxel Lin 2200000, 2400000, 2600000, 2800000, 3000000, 3200000, 3400000, 3600000,
6439b1772aSDaniel Ribeiro };
6539b1772aSDaniel Ribeiro
66c49af956SAxel Lin static const unsigned int VAUX4_table[] = {
67c49af956SAxel Lin 1800000, 1800000, 3000000, 5000000,
6839b1772aSDaniel Ribeiro };
6939b1772aSDaniel Ribeiro
70c49af956SAxel Lin static const unsigned int VSIM_table[] = {
71c49af956SAxel Lin 1875000, 3000000,
7239b1772aSDaniel Ribeiro };
7339b1772aSDaniel Ribeiro
74c49af956SAxel Lin static const unsigned int VSIM2_table[] = {
75c49af956SAxel Lin 1875000,
7639b1772aSDaniel Ribeiro };
7739b1772aSDaniel Ribeiro
78c49af956SAxel Lin static const unsigned int VVIB_table[] = {
79c49af956SAxel Lin 1300000, 1800000, 2000000, 3000000,
8039b1772aSDaniel Ribeiro };
8139b1772aSDaniel Ribeiro
82c49af956SAxel Lin static const unsigned int SW1_table[] = {
83c49af956SAxel Lin 900000, 950000, 1000000, 1050000, 1100000, 1150000, 1200000, 1250000,
84c49af956SAxel Lin 1300000, 1350000, 1400000, 1450000, 1500000, 1600000, 1875000, 2250000,
8539b1772aSDaniel Ribeiro };
8639b1772aSDaniel Ribeiro
8739b1772aSDaniel Ribeiro #define SW2_table SW1_table
8839b1772aSDaniel Ribeiro
8939b1772aSDaniel Ribeiro struct pcap_regulator {
9039b1772aSDaniel Ribeiro const u8 reg;
9139b1772aSDaniel Ribeiro const u8 en;
9239b1772aSDaniel Ribeiro const u8 index;
9339b1772aSDaniel Ribeiro const u8 stby;
9439b1772aSDaniel Ribeiro const u8 lowpwr;
9539b1772aSDaniel Ribeiro };
9639b1772aSDaniel Ribeiro
9739b1772aSDaniel Ribeiro #define NA 0xff
9839b1772aSDaniel Ribeiro
9939b1772aSDaniel Ribeiro #define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \
10039b1772aSDaniel Ribeiro [_vreg] = { \
10139b1772aSDaniel Ribeiro .reg = _reg, \
10239b1772aSDaniel Ribeiro .en = _en, \
10339b1772aSDaniel Ribeiro .index = _index, \
10439b1772aSDaniel Ribeiro .stby = _stby, \
10539b1772aSDaniel Ribeiro .lowpwr = _lowpwr, \
10639b1772aSDaniel Ribeiro }
10739b1772aSDaniel Ribeiro
10839b1772aSDaniel Ribeiro static struct pcap_regulator vreg_table[] = {
10939b1772aSDaniel Ribeiro VREG_INFO(V1, PCAP_REG_VREG1, 1, 2, 18, 0),
11039b1772aSDaniel Ribeiro VREG_INFO(V2, PCAP_REG_VREG1, 5, 6, 19, 22),
11139b1772aSDaniel Ribeiro VREG_INFO(V3, PCAP_REG_VREG1, 7, 8, 20, 23),
11239b1772aSDaniel Ribeiro VREG_INFO(V4, PCAP_REG_VREG1, 11, 12, 21, 24),
11339b1772aSDaniel Ribeiro /* V5 STBY and LOWPWR are on PCAP_REG_VREG2 */
11439b1772aSDaniel Ribeiro VREG_INFO(V5, PCAP_REG_VREG1, 15, 16, 12, 19),
11539b1772aSDaniel Ribeiro
11639b1772aSDaniel Ribeiro VREG_INFO(V6, PCAP_REG_VREG2, 1, 2, 14, 20),
11739b1772aSDaniel Ribeiro VREG_INFO(V7, PCAP_REG_VREG2, 3, 4, 15, 21),
11839b1772aSDaniel Ribeiro VREG_INFO(V8, PCAP_REG_VREG2, 5, 6, 16, 22),
11939b1772aSDaniel Ribeiro VREG_INFO(V9, PCAP_REG_VREG2, 9, 10, 17, 23),
12039b1772aSDaniel Ribeiro VREG_INFO(V10, PCAP_REG_VREG2, 10, NA, 18, 24),
12139b1772aSDaniel Ribeiro
12239b1772aSDaniel Ribeiro VREG_INFO(VAUX1, PCAP_REG_AUXVREG, 1, 2, 22, 23),
12339b1772aSDaniel Ribeiro /* VAUX2 ... VSIM2 STBY and LOWPWR are on PCAP_REG_LOWPWR */
12439b1772aSDaniel Ribeiro VREG_INFO(VAUX2, PCAP_REG_AUXVREG, 4, 5, 0, 1),
12539b1772aSDaniel Ribeiro VREG_INFO(VAUX3, PCAP_REG_AUXVREG, 7, 8, 2, 3),
12639b1772aSDaniel Ribeiro VREG_INFO(VAUX4, PCAP_REG_AUXVREG, 12, 13, 4, 5),
12739b1772aSDaniel Ribeiro VREG_INFO(VSIM, PCAP_REG_AUXVREG, 17, 18, NA, 6),
12839b1772aSDaniel Ribeiro VREG_INFO(VSIM2, PCAP_REG_AUXVREG, 16, NA, NA, 7),
12939b1772aSDaniel Ribeiro VREG_INFO(VVIB, PCAP_REG_AUXVREG, 19, 20, NA, NA),
13039b1772aSDaniel Ribeiro
13139b1772aSDaniel Ribeiro VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
13239b1772aSDaniel Ribeiro VREG_INFO(SW2, PCAP_REG_SWCTRL, 6, 7, NA, NA),
13339b1772aSDaniel Ribeiro /* SW3 STBY is on PCAP_REG_AUXVREG */
13439b1772aSDaniel Ribeiro VREG_INFO(SW3, PCAP_REG_SWCTRL, 11, 12, 24, NA),
13539b1772aSDaniel Ribeiro
13639b1772aSDaniel Ribeiro /* SWxS used to control SWx voltage on standby */
13739b1772aSDaniel Ribeiro /* VREG_INFO(SW1S, PCAP_REG_LOWPWR, NA, 12, NA, NA),
13839b1772aSDaniel Ribeiro VREG_INFO(SW2S, PCAP_REG_LOWPWR, NA, 20, NA, NA), */
13939b1772aSDaniel Ribeiro };
14039b1772aSDaniel Ribeiro
pcap_regulator_set_voltage_sel(struct regulator_dev * rdev,unsigned selector)141d5ec9635SAxel Lin static int pcap_regulator_set_voltage_sel(struct regulator_dev *rdev,
142d5ec9635SAxel Lin unsigned selector)
14339b1772aSDaniel Ribeiro {
14439b1772aSDaniel Ribeiro struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
14539b1772aSDaniel Ribeiro void *pcap = rdev_get_drvdata(rdev);
14639b1772aSDaniel Ribeiro
14739b1772aSDaniel Ribeiro /* the regulator doesn't support voltage switching */
148c49af956SAxel Lin if (rdev->desc->n_voltages == 1)
14939b1772aSDaniel Ribeiro return -EINVAL;
15039b1772aSDaniel Ribeiro
15139b1772aSDaniel Ribeiro return ezx_pcap_set_bits(pcap, vreg->reg,
152c49af956SAxel Lin (rdev->desc->n_voltages - 1) << vreg->index,
153d5ec9635SAxel Lin selector << vreg->index);
15439b1772aSDaniel Ribeiro }
15539b1772aSDaniel Ribeiro
pcap_regulator_get_voltage_sel(struct regulator_dev * rdev)1563cbff37eSAxel Lin static int pcap_regulator_get_voltage_sel(struct regulator_dev *rdev)
15739b1772aSDaniel Ribeiro {
15839b1772aSDaniel Ribeiro struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
15939b1772aSDaniel Ribeiro void *pcap = rdev_get_drvdata(rdev);
16039b1772aSDaniel Ribeiro u32 tmp;
16139b1772aSDaniel Ribeiro
162c49af956SAxel Lin if (rdev->desc->n_voltages == 1)
1633cbff37eSAxel Lin return 0;
16439b1772aSDaniel Ribeiro
16539b1772aSDaniel Ribeiro ezx_pcap_read(pcap, vreg->reg, &tmp);
166c49af956SAxel Lin tmp = ((tmp >> vreg->index) & (rdev->desc->n_voltages - 1));
1673cbff37eSAxel Lin return tmp;
16839b1772aSDaniel Ribeiro }
16939b1772aSDaniel Ribeiro
pcap_regulator_enable(struct regulator_dev * rdev)17039b1772aSDaniel Ribeiro static int pcap_regulator_enable(struct regulator_dev *rdev)
17139b1772aSDaniel Ribeiro {
17239b1772aSDaniel Ribeiro struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
17339b1772aSDaniel Ribeiro void *pcap = rdev_get_drvdata(rdev);
17439b1772aSDaniel Ribeiro
17539b1772aSDaniel Ribeiro if (vreg->en == NA)
17639b1772aSDaniel Ribeiro return -EINVAL;
17739b1772aSDaniel Ribeiro
17839b1772aSDaniel Ribeiro return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 1 << vreg->en);
17939b1772aSDaniel Ribeiro }
18039b1772aSDaniel Ribeiro
pcap_regulator_disable(struct regulator_dev * rdev)18139b1772aSDaniel Ribeiro static int pcap_regulator_disable(struct regulator_dev *rdev)
18239b1772aSDaniel Ribeiro {
18339b1772aSDaniel Ribeiro struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
18439b1772aSDaniel Ribeiro void *pcap = rdev_get_drvdata(rdev);
18539b1772aSDaniel Ribeiro
18639b1772aSDaniel Ribeiro if (vreg->en == NA)
18739b1772aSDaniel Ribeiro return -EINVAL;
18839b1772aSDaniel Ribeiro
18939b1772aSDaniel Ribeiro return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 0);
19039b1772aSDaniel Ribeiro }
19139b1772aSDaniel Ribeiro
pcap_regulator_is_enabled(struct regulator_dev * rdev)19239b1772aSDaniel Ribeiro static int pcap_regulator_is_enabled(struct regulator_dev *rdev)
19339b1772aSDaniel Ribeiro {
19439b1772aSDaniel Ribeiro struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
19539b1772aSDaniel Ribeiro void *pcap = rdev_get_drvdata(rdev);
19639b1772aSDaniel Ribeiro u32 tmp;
19739b1772aSDaniel Ribeiro
19839b1772aSDaniel Ribeiro if (vreg->en == NA)
19939b1772aSDaniel Ribeiro return -EINVAL;
20039b1772aSDaniel Ribeiro
20139b1772aSDaniel Ribeiro ezx_pcap_read(pcap, vreg->reg, &tmp);
20239b1772aSDaniel Ribeiro return (tmp >> vreg->en) & 1;
20339b1772aSDaniel Ribeiro }
20439b1772aSDaniel Ribeiro
20500804e6aSBhumika Goyal static const struct regulator_ops pcap_regulator_ops = {
206c49af956SAxel Lin .list_voltage = regulator_list_voltage_table,
207d5ec9635SAxel Lin .set_voltage_sel = pcap_regulator_set_voltage_sel,
2083cbff37eSAxel Lin .get_voltage_sel = pcap_regulator_get_voltage_sel,
20939b1772aSDaniel Ribeiro .enable = pcap_regulator_enable,
21039b1772aSDaniel Ribeiro .disable = pcap_regulator_disable,
21139b1772aSDaniel Ribeiro .is_enabled = pcap_regulator_is_enabled,
21239b1772aSDaniel Ribeiro };
21339b1772aSDaniel Ribeiro
21439b1772aSDaniel Ribeiro #define VREG(_vreg) \
21539b1772aSDaniel Ribeiro [_vreg] = { \
21639b1772aSDaniel Ribeiro .name = #_vreg, \
21739b1772aSDaniel Ribeiro .id = _vreg, \
21839b1772aSDaniel Ribeiro .n_voltages = ARRAY_SIZE(_vreg##_table), \
219c49af956SAxel Lin .volt_table = _vreg##_table, \
22039b1772aSDaniel Ribeiro .ops = &pcap_regulator_ops, \
22139b1772aSDaniel Ribeiro .type = REGULATOR_VOLTAGE, \
22239b1772aSDaniel Ribeiro .owner = THIS_MODULE, \
22339b1772aSDaniel Ribeiro }
22439b1772aSDaniel Ribeiro
2250d2fbc51SAxel Lin static const struct regulator_desc pcap_regulators[] = {
22639b1772aSDaniel Ribeiro VREG(V1), VREG(V2), VREG(V3), VREG(V4), VREG(V5), VREG(V6), VREG(V7),
22739b1772aSDaniel Ribeiro VREG(V8), VREG(V9), VREG(V10), VREG(VAUX1), VREG(VAUX2), VREG(VAUX3),
22839b1772aSDaniel Ribeiro VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
22939b1772aSDaniel Ribeiro };
23039b1772aSDaniel Ribeiro
pcap_regulator_probe(struct platform_device * pdev)231a5023574SBill Pemberton static int pcap_regulator_probe(struct platform_device *pdev)
23239b1772aSDaniel Ribeiro {
23339b1772aSDaniel Ribeiro struct regulator_dev *rdev;
23470fde5cbSAntonio Ospite void *pcap = dev_get_drvdata(pdev->dev.parent);
235c172708dSMark Brown struct regulator_config config = { };
23639b1772aSDaniel Ribeiro
237c172708dSMark Brown config.dev = &pdev->dev;
238dff91d0bSJingoo Han config.init_data = dev_get_platdata(&pdev->dev);
239c172708dSMark Brown config.driver_data = pcap;
240c172708dSMark Brown
24115dc006aSJingoo Han rdev = devm_regulator_register(&pdev->dev, &pcap_regulators[pdev->id],
24215dc006aSJingoo Han &config);
24339b1772aSDaniel Ribeiro if (IS_ERR(rdev))
24439b1772aSDaniel Ribeiro return PTR_ERR(rdev);
24539b1772aSDaniel Ribeiro
24639b1772aSDaniel Ribeiro platform_set_drvdata(pdev, rdev);
24739b1772aSDaniel Ribeiro
24839b1772aSDaniel Ribeiro return 0;
24939b1772aSDaniel Ribeiro }
25039b1772aSDaniel Ribeiro
25139b1772aSDaniel Ribeiro static struct platform_driver pcap_regulator_driver = {
25239b1772aSDaniel Ribeiro .driver = {
25339b1772aSDaniel Ribeiro .name = "pcap-regulator",
254*259b93b2SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
25539b1772aSDaniel Ribeiro },
25639b1772aSDaniel Ribeiro .probe = pcap_regulator_probe,
25739b1772aSDaniel Ribeiro };
25839b1772aSDaniel Ribeiro
pcap_regulator_init(void)25939b1772aSDaniel Ribeiro static int __init pcap_regulator_init(void)
26039b1772aSDaniel Ribeiro {
26139b1772aSDaniel Ribeiro return platform_driver_register(&pcap_regulator_driver);
26239b1772aSDaniel Ribeiro }
26339b1772aSDaniel Ribeiro
pcap_regulator_exit(void)26439b1772aSDaniel Ribeiro static void __exit pcap_regulator_exit(void)
26539b1772aSDaniel Ribeiro {
26639b1772aSDaniel Ribeiro platform_driver_unregister(&pcap_regulator_driver);
26739b1772aSDaniel Ribeiro }
26839b1772aSDaniel Ribeiro
269e397e7edSAntonio Ospite subsys_initcall(pcap_regulator_init);
27039b1772aSDaniel Ribeiro module_exit(pcap_regulator_exit);
27139b1772aSDaniel Ribeiro
27239b1772aSDaniel Ribeiro MODULE_AUTHOR("Daniel Ribeiro <drwyrm@gmail.com>");
27339b1772aSDaniel Ribeiro MODULE_DESCRIPTION("PCAP2 Regulator Driver");
27439b1772aSDaniel Ribeiro MODULE_LICENSE("GPL");
275