1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2ade7515fSKim, Milo /*
3ade7515fSKim, Milo  * TI LP8788 MFD - ldo regulator driver
4ade7515fSKim, Milo  *
5ade7515fSKim, Milo  * Copyright 2012 Texas Instruments
6ade7515fSKim, Milo  *
7ade7515fSKim, Milo  * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
8ade7515fSKim, Milo  */
9ade7515fSKim, Milo 
10ade7515fSKim, Milo #include <linux/module.h>
11ade7515fSKim, Milo #include <linux/slab.h>
12ade7515fSKim, Milo #include <linux/err.h>
13ade7515fSKim, Milo #include <linux/platform_device.h>
14ade7515fSKim, Milo #include <linux/regulator/driver.h>
152468f0d5SLinus Walleij #include <linux/gpio/consumer.h>
16ade7515fSKim, Milo #include <linux/mfd/lp8788.h>
17ade7515fSKim, Milo 
18ade7515fSKim, Milo /* register address */
19ade7515fSKim, Milo #define LP8788_EN_LDO_A			0x0D	/* DLDO 1 ~ 8 */
20ade7515fSKim, Milo #define LP8788_EN_LDO_B			0x0E	/* DLDO 9 ~ 12, ALDO 1 ~ 4 */
21ade7515fSKim, Milo #define LP8788_EN_LDO_C			0x0F	/* ALDO 5 ~ 10 */
22ade7515fSKim, Milo #define LP8788_EN_SEL			0x10
23ade7515fSKim, Milo #define LP8788_DLDO1_VOUT		0x2E
24ade7515fSKim, Milo #define LP8788_DLDO2_VOUT		0x2F
25ade7515fSKim, Milo #define LP8788_DLDO3_VOUT		0x30
26ade7515fSKim, Milo #define LP8788_DLDO4_VOUT		0x31
27ade7515fSKim, Milo #define LP8788_DLDO5_VOUT		0x32
28ade7515fSKim, Milo #define LP8788_DLDO6_VOUT		0x33
29ade7515fSKim, Milo #define LP8788_DLDO7_VOUT		0x34
30ade7515fSKim, Milo #define LP8788_DLDO8_VOUT		0x35
31ade7515fSKim, Milo #define LP8788_DLDO9_VOUT		0x36
32ade7515fSKim, Milo #define LP8788_DLDO10_VOUT		0x37
33ade7515fSKim, Milo #define LP8788_DLDO11_VOUT		0x38
34ade7515fSKim, Milo #define LP8788_DLDO12_VOUT		0x39
35ade7515fSKim, Milo #define LP8788_ALDO1_VOUT		0x3A
36ade7515fSKim, Milo #define LP8788_ALDO2_VOUT		0x3B
37ade7515fSKim, Milo #define LP8788_ALDO3_VOUT		0x3C
38ade7515fSKim, Milo #define LP8788_ALDO4_VOUT		0x3D
39ade7515fSKim, Milo #define LP8788_ALDO5_VOUT		0x3E
40ade7515fSKim, Milo #define LP8788_ALDO6_VOUT		0x3F
41ade7515fSKim, Milo #define LP8788_ALDO7_VOUT		0x40
42ade7515fSKim, Milo #define LP8788_ALDO8_VOUT		0x41
43ade7515fSKim, Milo #define LP8788_ALDO9_VOUT		0x42
44ade7515fSKim, Milo #define LP8788_ALDO10_VOUT		0x43
45ade7515fSKim, Milo #define LP8788_DLDO1_TIMESTEP		0x44
46ade7515fSKim, Milo 
47ade7515fSKim, Milo /* mask/shift bits */
48ade7515fSKim, Milo #define LP8788_EN_DLDO1_M		BIT(0)	/* Addr 0Dh ~ 0Fh */
49ade7515fSKim, Milo #define LP8788_EN_DLDO2_M		BIT(1)
50ade7515fSKim, Milo #define LP8788_EN_DLDO3_M		BIT(2)
51ade7515fSKim, Milo #define LP8788_EN_DLDO4_M		BIT(3)
52ade7515fSKim, Milo #define LP8788_EN_DLDO5_M		BIT(4)
53ade7515fSKim, Milo #define LP8788_EN_DLDO6_M		BIT(5)
54ade7515fSKim, Milo #define LP8788_EN_DLDO7_M		BIT(6)
55ade7515fSKim, Milo #define LP8788_EN_DLDO8_M		BIT(7)
56ade7515fSKim, Milo #define LP8788_EN_DLDO9_M		BIT(0)
57ade7515fSKim, Milo #define LP8788_EN_DLDO10_M		BIT(1)
58ade7515fSKim, Milo #define LP8788_EN_DLDO11_M		BIT(2)
59ade7515fSKim, Milo #define LP8788_EN_DLDO12_M		BIT(3)
60ade7515fSKim, Milo #define LP8788_EN_ALDO1_M		BIT(4)
61ade7515fSKim, Milo #define LP8788_EN_ALDO2_M		BIT(5)
62ade7515fSKim, Milo #define LP8788_EN_ALDO3_M		BIT(6)
63ade7515fSKim, Milo #define LP8788_EN_ALDO4_M		BIT(7)
64ade7515fSKim, Milo #define LP8788_EN_ALDO5_M		BIT(0)
65ade7515fSKim, Milo #define LP8788_EN_ALDO6_M		BIT(1)
66ade7515fSKim, Milo #define LP8788_EN_ALDO7_M		BIT(2)
67ade7515fSKim, Milo #define LP8788_EN_ALDO8_M		BIT(3)
68ade7515fSKim, Milo #define LP8788_EN_ALDO9_M		BIT(4)
69ade7515fSKim, Milo #define LP8788_EN_ALDO10_M		BIT(5)
70ade7515fSKim, Milo #define LP8788_EN_SEL_DLDO911_M		BIT(0)	/* Addr 10h */
71ade7515fSKim, Milo #define LP8788_EN_SEL_DLDO7_M		BIT(1)
72ade7515fSKim, Milo #define LP8788_EN_SEL_ALDO7_M		BIT(2)
73ade7515fSKim, Milo #define LP8788_EN_SEL_ALDO5_M		BIT(3)
74ade7515fSKim, Milo #define LP8788_EN_SEL_ALDO234_M		BIT(4)
75ade7515fSKim, Milo #define LP8788_EN_SEL_ALDO1_M		BIT(5)
76ade7515fSKim, Milo #define LP8788_VOUT_5BIT_M		0x1F	/* Addr 2Eh ~ 43h */
77ade7515fSKim, Milo #define LP8788_VOUT_4BIT_M		0x0F
78ade7515fSKim, Milo #define LP8788_VOUT_3BIT_M		0x07
79ade7515fSKim, Milo #define LP8788_VOUT_1BIT_M		0x01
80ade7515fSKim, Milo #define LP8788_STARTUP_TIME_M		0xF8	/* Addr 44h ~ 59h */
81ade7515fSKim, Milo #define LP8788_STARTUP_TIME_S		3
82ade7515fSKim, Milo 
83ade7515fSKim, Milo #define ENABLE_TIME_USEC		32
84ade7515fSKim, Milo 
85ade7515fSKim, Milo enum lp8788_ldo_id {
86ade7515fSKim, Milo 	DLDO1,
87ade7515fSKim, Milo 	DLDO2,
88ade7515fSKim, Milo 	DLDO3,
89ade7515fSKim, Milo 	DLDO4,
90ade7515fSKim, Milo 	DLDO5,
91ade7515fSKim, Milo 	DLDO6,
92ade7515fSKim, Milo 	DLDO7,
93ade7515fSKim, Milo 	DLDO8,
94ade7515fSKim, Milo 	DLDO9,
95ade7515fSKim, Milo 	DLDO10,
96ade7515fSKim, Milo 	DLDO11,
97ade7515fSKim, Milo 	DLDO12,
98ade7515fSKim, Milo 	ALDO1,
99ade7515fSKim, Milo 	ALDO2,
100ade7515fSKim, Milo 	ALDO3,
101ade7515fSKim, Milo 	ALDO4,
102ade7515fSKim, Milo 	ALDO5,
103ade7515fSKim, Milo 	ALDO6,
104ade7515fSKim, Milo 	ALDO7,
105ade7515fSKim, Milo 	ALDO8,
106ade7515fSKim, Milo 	ALDO9,
107ade7515fSKim, Milo 	ALDO10,
108ade7515fSKim, Milo };
109ade7515fSKim, Milo 
110ade7515fSKim, Milo struct lp8788_ldo {
111ade7515fSKim, Milo 	struct lp8788 *lp;
112ade7515fSKim, Milo 	struct regulator_desc *desc;
113ade7515fSKim, Milo 	struct regulator_dev *regulator;
1142468f0d5SLinus Walleij 	struct gpio_desc *ena_gpiod;
115ade7515fSKim, Milo };
116ade7515fSKim, Milo 
117ade7515fSKim, Milo /* DLDO 1, 2, 3, 9 voltage table */
1184e92920bSMark Brown static const int lp8788_dldo1239_vtbl[] = {
119ade7515fSKim, Milo 	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
120ade7515fSKim, Milo 	2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
121ade7515fSKim, Milo 	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
122ade7515fSKim, Milo 	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
123ade7515fSKim, Milo };
124ade7515fSKim, Milo 
125ade7515fSKim, Milo /* DLDO 4 voltage table */
126ade7515fSKim, Milo static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };
127ade7515fSKim, Milo 
128ade7515fSKim, Milo /* DLDO 5, 7, 8 and ALDO 6 voltage table */
129ade7515fSKim, Milo static const int lp8788_dldo578_aldo6_vtbl[] = {
130ade7515fSKim, Milo 	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
131ade7515fSKim, Milo 	2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
132ade7515fSKim, Milo };
133ade7515fSKim, Milo 
134ade7515fSKim, Milo /* DLDO 6 voltage table */
135ade7515fSKim, Milo static const int lp8788_dldo6_vtbl[] = {
136ade7515fSKim, Milo 	3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
137ade7515fSKim, Milo };
138ade7515fSKim, Milo 
139ade7515fSKim, Milo /* DLDO 10, 11 voltage table */
140ade7515fSKim, Milo static const int lp8788_dldo1011_vtbl[] = {
141ade7515fSKim, Milo 	1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
142ade7515fSKim, Milo 	1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
143ade7515fSKim, Milo };
144ade7515fSKim, Milo 
145ade7515fSKim, Milo /* ALDO 1 voltage table */
146ade7515fSKim, Milo static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };
147ade7515fSKim, Milo 
148ade7515fSKim, Milo /* ALDO 7 voltage table */
149ade7515fSKim, Milo static const int lp8788_aldo7_vtbl[] = {
150ade7515fSKim, Milo 	1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
151ade7515fSKim, Milo };
152ade7515fSKim, Milo 
153ade7515fSKim, Milo static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
154ade7515fSKim, Milo {
155ade7515fSKim, Milo 	struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
156ade7515fSKim, Milo 	enum lp8788_ldo_id id = rdev_get_id(rdev);
157ade7515fSKim, Milo 	u8 val, addr = LP8788_DLDO1_TIMESTEP + id;
158ade7515fSKim, Milo 
159ade7515fSKim, Milo 	if (lp8788_read_byte(ldo->lp, addr, &val))
160ade7515fSKim, Milo 		return -EINVAL;
161ade7515fSKim, Milo 
162ade7515fSKim, Milo 	val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
163ade7515fSKim, Milo 
164ade7515fSKim, Milo 	return ENABLE_TIME_USEC * val;
165ade7515fSKim, Milo }
166ade7515fSKim, Milo 
16795dfead1SJulia Lawall static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
168ade7515fSKim, Milo 	.list_voltage = regulator_list_voltage_table,
169ade7515fSKim, Milo 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
170ade7515fSKim, Milo 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
171407945fdSKim, Milo 	.enable = regulator_enable_regmap,
172407945fdSKim, Milo 	.disable = regulator_disable_regmap,
173407945fdSKim, Milo 	.is_enabled = regulator_is_enabled_regmap,
174ade7515fSKim, Milo 	.enable_time = lp8788_ldo_enable_time,
175ade7515fSKim, Milo };
176ade7515fSKim, Milo 
17795dfead1SJulia Lawall static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
178b5366e5eSAxel Lin 	.list_voltage = regulator_list_voltage_linear,
179407945fdSKim, Milo 	.enable = regulator_enable_regmap,
180407945fdSKim, Milo 	.disable = regulator_disable_regmap,
181407945fdSKim, Milo 	.is_enabled = regulator_is_enabled_regmap,
182ade7515fSKim, Milo 	.enable_time = lp8788_ldo_enable_time,
183ade7515fSKim, Milo };
184ade7515fSKim, Milo 
18523295d79SAxel Lin static const struct regulator_desc lp8788_dldo_desc[] = {
186ade7515fSKim, Milo 	{
187ade7515fSKim, Milo 		.name = "dldo1",
188ade7515fSKim, Milo 		.id = DLDO1,
189ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
190ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
191ade7515fSKim, Milo 		.volt_table = lp8788_dldo1239_vtbl,
192ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
193ade7515fSKim, Milo 		.owner = THIS_MODULE,
194ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO1_VOUT,
195ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_5BIT_M,
196ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
197ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO1_M,
198ade7515fSKim, Milo 	},
199ade7515fSKim, Milo 	{
200ade7515fSKim, Milo 		.name = "dldo2",
201ade7515fSKim, Milo 		.id = DLDO2,
202ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
203ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
204ade7515fSKim, Milo 		.volt_table = lp8788_dldo1239_vtbl,
205ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
206ade7515fSKim, Milo 		.owner = THIS_MODULE,
207ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO2_VOUT,
208ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_5BIT_M,
209ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
210ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO2_M,
211ade7515fSKim, Milo 	},
212ade7515fSKim, Milo 	{
213ade7515fSKim, Milo 		.name = "dldo3",
214ade7515fSKim, Milo 		.id = DLDO3,
215ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
216ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
217ade7515fSKim, Milo 		.volt_table = lp8788_dldo1239_vtbl,
218ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
219ade7515fSKim, Milo 		.owner = THIS_MODULE,
220ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO3_VOUT,
221ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_5BIT_M,
222ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
223ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO3_M,
224ade7515fSKim, Milo 	},
225ade7515fSKim, Milo 	{
226ade7515fSKim, Milo 		.name = "dldo4",
227ade7515fSKim, Milo 		.id = DLDO4,
228ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
229ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
230ade7515fSKim, Milo 		.volt_table = lp8788_dldo4_vtbl,
231ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
232ade7515fSKim, Milo 		.owner = THIS_MODULE,
233ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO4_VOUT,
234ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_1BIT_M,
235ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
236ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO4_M,
237ade7515fSKim, Milo 	},
238ade7515fSKim, Milo 	{
239ade7515fSKim, Milo 		.name = "dldo5",
240ade7515fSKim, Milo 		.id = DLDO5,
241ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
242ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
243ade7515fSKim, Milo 		.volt_table = lp8788_dldo578_aldo6_vtbl,
244ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
245ade7515fSKim, Milo 		.owner = THIS_MODULE,
246ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO5_VOUT,
247ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_4BIT_M,
248ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
249ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO5_M,
250ade7515fSKim, Milo 	},
251ade7515fSKim, Milo 	{
252ade7515fSKim, Milo 		.name = "dldo6",
253ade7515fSKim, Milo 		.id = DLDO6,
254ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
255ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
256ade7515fSKim, Milo 		.volt_table = lp8788_dldo6_vtbl,
257ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
258ade7515fSKim, Milo 		.owner = THIS_MODULE,
259ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO6_VOUT,
260ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_3BIT_M,
261ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
262ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO6_M,
263ade7515fSKim, Milo 	},
264ade7515fSKim, Milo 	{
265ade7515fSKim, Milo 		.name = "dldo7",
266ade7515fSKim, Milo 		.id = DLDO7,
267ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
268ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
269ade7515fSKim, Milo 		.volt_table = lp8788_dldo578_aldo6_vtbl,
270ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
271ade7515fSKim, Milo 		.owner = THIS_MODULE,
272ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO7_VOUT,
273ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_4BIT_M,
274ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
275ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO7_M,
276ade7515fSKim, Milo 	},
277ade7515fSKim, Milo 	{
278ade7515fSKim, Milo 		.name = "dldo8",
279ade7515fSKim, Milo 		.id = DLDO8,
280ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
281ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
282ade7515fSKim, Milo 		.volt_table = lp8788_dldo578_aldo6_vtbl,
283ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
284ade7515fSKim, Milo 		.owner = THIS_MODULE,
285ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO8_VOUT,
286ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_4BIT_M,
287ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_A,
288ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO8_M,
289ade7515fSKim, Milo 	},
290ade7515fSKim, Milo 	{
291ade7515fSKim, Milo 		.name = "dldo9",
292ade7515fSKim, Milo 		.id = DLDO9,
293ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
294ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
295ade7515fSKim, Milo 		.volt_table = lp8788_dldo1239_vtbl,
296ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
297ade7515fSKim, Milo 		.owner = THIS_MODULE,
298ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO9_VOUT,
299ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_5BIT_M,
300ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
301ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO9_M,
302ade7515fSKim, Milo 	},
303ade7515fSKim, Milo 	{
304ade7515fSKim, Milo 		.name = "dldo10",
305ade7515fSKim, Milo 		.id = DLDO10,
306ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
307ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
308ade7515fSKim, Milo 		.volt_table = lp8788_dldo1011_vtbl,
309ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
310ade7515fSKim, Milo 		.owner = THIS_MODULE,
311ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO10_VOUT,
312ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_4BIT_M,
313ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
314ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO10_M,
315ade7515fSKim, Milo 	},
316ade7515fSKim, Milo 	{
317ade7515fSKim, Milo 		.name = "dldo11",
318ade7515fSKim, Milo 		.id = DLDO11,
319ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
320ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
321ade7515fSKim, Milo 		.volt_table = lp8788_dldo1011_vtbl,
322ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
323ade7515fSKim, Milo 		.owner = THIS_MODULE,
324ade7515fSKim, Milo 		.vsel_reg = LP8788_DLDO11_VOUT,
325ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_4BIT_M,
326ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
327ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO11_M,
328ade7515fSKim, Milo 	},
329ade7515fSKim, Milo 	{
330ade7515fSKim, Milo 		.name = "dldo12",
331ade7515fSKim, Milo 		.id = DLDO12,
332ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
33374c8cfdaSAxel Lin 		.n_voltages = 1,
334ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
335ade7515fSKim, Milo 		.owner = THIS_MODULE,
336ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
337ade7515fSKim, Milo 		.enable_mask = LP8788_EN_DLDO12_M,
338b5366e5eSAxel Lin 		.min_uV = 2500000,
339ade7515fSKim, Milo 	},
340ade7515fSKim, Milo };
341ade7515fSKim, Milo 
34223295d79SAxel Lin static const struct regulator_desc lp8788_aldo_desc[] = {
343ade7515fSKim, Milo 	{
344ade7515fSKim, Milo 		.name = "aldo1",
345ade7515fSKim, Milo 		.id = ALDO1,
346ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
347ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
348ade7515fSKim, Milo 		.volt_table = lp8788_aldo1_vtbl,
349ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
350ade7515fSKim, Milo 		.owner = THIS_MODULE,
351ade7515fSKim, Milo 		.vsel_reg = LP8788_ALDO1_VOUT,
352ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_1BIT_M,
353ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
354ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO1_M,
355ade7515fSKim, Milo 	},
356ade7515fSKim, Milo 	{
357ade7515fSKim, Milo 		.name = "aldo2",
358ade7515fSKim, Milo 		.id = ALDO2,
359ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
36074c8cfdaSAxel Lin 		.n_voltages = 1,
361ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
362ade7515fSKim, Milo 		.owner = THIS_MODULE,
363ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
364ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO2_M,
365b5366e5eSAxel Lin 		.min_uV = 2850000,
366ade7515fSKim, Milo 	},
367ade7515fSKim, Milo 	{
368ade7515fSKim, Milo 		.name = "aldo3",
369ade7515fSKim, Milo 		.id = ALDO3,
370ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
37174c8cfdaSAxel Lin 		.n_voltages = 1,
372ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
373ade7515fSKim, Milo 		.owner = THIS_MODULE,
374ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
375ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO3_M,
376b5366e5eSAxel Lin 		.min_uV = 2850000,
377ade7515fSKim, Milo 	},
378ade7515fSKim, Milo 	{
379ade7515fSKim, Milo 		.name = "aldo4",
380ade7515fSKim, Milo 		.id = ALDO4,
381ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
38274c8cfdaSAxel Lin 		.n_voltages = 1,
383ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
384ade7515fSKim, Milo 		.owner = THIS_MODULE,
385ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_B,
386ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO4_M,
387b5366e5eSAxel Lin 		.min_uV = 2850000,
388ade7515fSKim, Milo 	},
389ade7515fSKim, Milo 	{
390ade7515fSKim, Milo 		.name = "aldo5",
391ade7515fSKim, Milo 		.id = ALDO5,
392ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
39374c8cfdaSAxel Lin 		.n_voltages = 1,
394ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
395ade7515fSKim, Milo 		.owner = THIS_MODULE,
396ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_C,
397ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO5_M,
398b5366e5eSAxel Lin 		.min_uV = 2850000,
399ade7515fSKim, Milo 	},
400ade7515fSKim, Milo 	{
401ade7515fSKim, Milo 		.name = "aldo6",
402ade7515fSKim, Milo 		.id = ALDO6,
403ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
404ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
405ade7515fSKim, Milo 		.volt_table = lp8788_dldo578_aldo6_vtbl,
406ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
407ade7515fSKim, Milo 		.owner = THIS_MODULE,
408ade7515fSKim, Milo 		.vsel_reg = LP8788_ALDO6_VOUT,
409ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_4BIT_M,
410ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_C,
411ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO6_M,
412ade7515fSKim, Milo 	},
413ade7515fSKim, Milo 	{
414ade7515fSKim, Milo 		.name = "aldo7",
415ade7515fSKim, Milo 		.id = ALDO7,
416ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_table_ops,
417ade7515fSKim, Milo 		.n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
418ade7515fSKim, Milo 		.volt_table = lp8788_aldo7_vtbl,
419ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
420ade7515fSKim, Milo 		.owner = THIS_MODULE,
421ade7515fSKim, Milo 		.vsel_reg = LP8788_ALDO7_VOUT,
422ade7515fSKim, Milo 		.vsel_mask = LP8788_VOUT_3BIT_M,
423ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_C,
424ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO7_M,
425ade7515fSKim, Milo 	},
426ade7515fSKim, Milo 	{
427ade7515fSKim, Milo 		.name = "aldo8",
428ade7515fSKim, Milo 		.id = ALDO8,
429ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
43074c8cfdaSAxel Lin 		.n_voltages = 1,
431ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
432ade7515fSKim, Milo 		.owner = THIS_MODULE,
433ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_C,
434ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO8_M,
435b5366e5eSAxel Lin 		.min_uV = 2500000,
436ade7515fSKim, Milo 	},
437ade7515fSKim, Milo 	{
438ade7515fSKim, Milo 		.name = "aldo9",
439ade7515fSKim, Milo 		.id = ALDO9,
440ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
44174c8cfdaSAxel Lin 		.n_voltages = 1,
442ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
443ade7515fSKim, Milo 		.owner = THIS_MODULE,
444ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_C,
445ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO9_M,
446b5366e5eSAxel Lin 		.min_uV = 2500000,
447ade7515fSKim, Milo 	},
448ade7515fSKim, Milo 	{
449ade7515fSKim, Milo 		.name = "aldo10",
450ade7515fSKim, Milo 		.id = ALDO10,
451ade7515fSKim, Milo 		.ops = &lp8788_ldo_voltage_fixed_ops,
45274c8cfdaSAxel Lin 		.n_voltages = 1,
453ade7515fSKim, Milo 		.type = REGULATOR_VOLTAGE,
454ade7515fSKim, Milo 		.owner = THIS_MODULE,
455ade7515fSKim, Milo 		.enable_reg = LP8788_EN_LDO_C,
456ade7515fSKim, Milo 		.enable_mask = LP8788_EN_ALDO10_M,
457b5366e5eSAxel Lin 		.min_uV = 1100000,
458ade7515fSKim, Milo 	},
459ade7515fSKim, Milo };
460ade7515fSKim, Milo 
461f02a3917SKim, Milo static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
462f02a3917SKim, Milo 					struct lp8788_ldo *ldo,
463ade7515fSKim, Milo 					enum lp8788_ldo_id id)
464ade7515fSKim, Milo {
465ade7515fSKim, Milo 	struct lp8788 *lp = ldo->lp;
466ade7515fSKim, Milo 	enum lp8788_ext_ldo_en_id enable_id;
4676cbe29c9SColin Ian King 	static const u8 en_mask[] = {
468ade7515fSKim, Milo 		[EN_ALDO1]   = LP8788_EN_SEL_ALDO1_M,
469ade7515fSKim, Milo 		[EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
470ade7515fSKim, Milo 		[EN_ALDO5]   = LP8788_EN_SEL_ALDO5_M,
471ade7515fSKim, Milo 		[EN_ALDO7]   = LP8788_EN_SEL_ALDO7_M,
472ade7515fSKim, Milo 		[EN_DLDO7]   = LP8788_EN_SEL_DLDO7_M,
473ade7515fSKim, Milo 		[EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
474ade7515fSKim, Milo 	};
475ade7515fSKim, Milo 
476ade7515fSKim, Milo 	switch (id) {
477ade7515fSKim, Milo 	case DLDO7:
478ade7515fSKim, Milo 		enable_id = EN_DLDO7;
479ade7515fSKim, Milo 		break;
480ade7515fSKim, Milo 	case DLDO9:
481ade7515fSKim, Milo 	case DLDO11:
482ade7515fSKim, Milo 		enable_id = EN_DLDO911;
483ade7515fSKim, Milo 		break;
484ade7515fSKim, Milo 	case ALDO1:
485ade7515fSKim, Milo 		enable_id = EN_ALDO1;
486ade7515fSKim, Milo 		break;
487ade7515fSKim, Milo 	case ALDO2 ... ALDO4:
488ade7515fSKim, Milo 		enable_id = EN_ALDO234;
489ade7515fSKim, Milo 		break;
490ade7515fSKim, Milo 	case ALDO5:
491ade7515fSKim, Milo 		enable_id = EN_ALDO5;
492ade7515fSKim, Milo 		break;
493ade7515fSKim, Milo 	case ALDO7:
494ade7515fSKim, Milo 		enable_id = EN_ALDO7;
495ade7515fSKim, Milo 		break;
496ade7515fSKim, Milo 	default:
497ade7515fSKim, Milo 		return 0;
498ade7515fSKim, Milo 	}
499ade7515fSKim, Milo 
5002bb8ede0SLinus Walleij 	/*
5012bb8ede0SLinus Walleij 	 * Do not use devm* here: the regulator core takes over the
5022bb8ede0SLinus Walleij 	 * lifecycle management of the GPIO descriptor.
5032bb8ede0SLinus Walleij 	 * FIXME: check default mode for GPIO here: high or low?
5042bb8ede0SLinus Walleij 	 */
5052bb8ede0SLinus Walleij 	ldo->ena_gpiod = gpiod_get_index_optional(&pdev->dev,
5062468f0d5SLinus Walleij 					       "enable",
5072468f0d5SLinus Walleij 					       enable_id,
50863239e4bSLinus Walleij 					       GPIOD_OUT_HIGH |
50963239e4bSLinus Walleij 					       GPIOD_FLAGS_BIT_NONEXCLUSIVE);
5102468f0d5SLinus Walleij 	if (IS_ERR(ldo->ena_gpiod))
5112468f0d5SLinus Walleij 		return PTR_ERR(ldo->ena_gpiod);
5122468f0d5SLinus Walleij 
5132468f0d5SLinus Walleij 	/* if no GPIO for ldo pin, then set default enable mode */
5142468f0d5SLinus Walleij 	if (!ldo->ena_gpiod)
515ade7515fSKim, Milo 		goto set_default_ldo_enable_mode;
516ade7515fSKim, Milo 
517407945fdSKim, Milo 	return 0;
518ade7515fSKim, Milo 
519ade7515fSKim, Milo set_default_ldo_enable_mode:
52040b5aa8fSAxel Lin 	return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
521ade7515fSKim, Milo }
522ade7515fSKim, Milo 
523a5023574SBill Pemberton static int lp8788_dldo_probe(struct platform_device *pdev)
524ade7515fSKim, Milo {
525ade7515fSKim, Milo 	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
526ade7515fSKim, Milo 	int id = pdev->id;
527ade7515fSKim, Milo 	struct lp8788_ldo *ldo;
528ade7515fSKim, Milo 	struct regulator_config cfg = { };
529ade7515fSKim, Milo 	struct regulator_dev *rdev;
530ade7515fSKim, Milo 	int ret;
531ade7515fSKim, Milo 
532939e88f0SKim, Milo 	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
533ade7515fSKim, Milo 	if (!ldo)
534ade7515fSKim, Milo 		return -ENOMEM;
535ade7515fSKim, Milo 
536ade7515fSKim, Milo 	ldo->lp = lp;
53780abd60dSAxel Lin 	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
538ade7515fSKim, Milo 	if (ret)
539ade7515fSKim, Milo 		return ret;
540ade7515fSKim, Milo 
5412468f0d5SLinus Walleij 	if (ldo->ena_gpiod)
5422468f0d5SLinus Walleij 		cfg.ena_gpiod = ldo->ena_gpiod;
543407945fdSKim, Milo 
544939e88f0SKim, Milo 	cfg.dev = pdev->dev.parent;
545ade7515fSKim, Milo 	cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
546ade7515fSKim, Milo 	cfg.driver_data = ldo;
547ade7515fSKim, Milo 	cfg.regmap = lp->regmap;
548ade7515fSKim, Milo 
5490b7bb090SJingoo Han 	rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
550ade7515fSKim, Milo 	if (IS_ERR(rdev)) {
551ade7515fSKim, Milo 		ret = PTR_ERR(rdev);
552939e88f0SKim, Milo 		dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
553ade7515fSKim, Milo 				id + 1, ret);
554ade7515fSKim, Milo 		return ret;
555ade7515fSKim, Milo 	}
556ade7515fSKim, Milo 
557ade7515fSKim, Milo 	ldo->regulator = rdev;
558ade7515fSKim, Milo 	platform_set_drvdata(pdev, ldo);
559ade7515fSKim, Milo 
560ade7515fSKim, Milo 	return 0;
561ade7515fSKim, Milo }
562ade7515fSKim, Milo 
563ade7515fSKim, Milo static struct platform_driver lp8788_dldo_driver = {
564ade7515fSKim, Milo 	.probe = lp8788_dldo_probe,
565ade7515fSKim, Milo 	.driver = {
566ade7515fSKim, Milo 		.name = LP8788_DEV_DLDO,
567ade7515fSKim, Milo 	},
568ade7515fSKim, Milo };
569ade7515fSKim, Milo 
570a5023574SBill Pemberton static int lp8788_aldo_probe(struct platform_device *pdev)
571ade7515fSKim, Milo {
572ade7515fSKim, Milo 	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
573ade7515fSKim, Milo 	int id = pdev->id;
574ade7515fSKim, Milo 	struct lp8788_ldo *ldo;
575ade7515fSKim, Milo 	struct regulator_config cfg = { };
576ade7515fSKim, Milo 	struct regulator_dev *rdev;
577ade7515fSKim, Milo 	int ret;
578ade7515fSKim, Milo 
579939e88f0SKim, Milo 	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
580ade7515fSKim, Milo 	if (!ldo)
581ade7515fSKim, Milo 		return -ENOMEM;
582ade7515fSKim, Milo 
583ade7515fSKim, Milo 	ldo->lp = lp;
58480abd60dSAxel Lin 	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
585ade7515fSKim, Milo 	if (ret)
586ade7515fSKim, Milo 		return ret;
587ade7515fSKim, Milo 
5882468f0d5SLinus Walleij 	if (ldo->ena_gpiod)
5892468f0d5SLinus Walleij 		cfg.ena_gpiod = ldo->ena_gpiod;
590407945fdSKim, Milo 
591939e88f0SKim, Milo 	cfg.dev = pdev->dev.parent;
592ade7515fSKim, Milo 	cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
593ade7515fSKim, Milo 	cfg.driver_data = ldo;
594ade7515fSKim, Milo 	cfg.regmap = lp->regmap;
595ade7515fSKim, Milo 
5960b7bb090SJingoo Han 	rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
597ade7515fSKim, Milo 	if (IS_ERR(rdev)) {
598ade7515fSKim, Milo 		ret = PTR_ERR(rdev);
599939e88f0SKim, Milo 		dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
600ade7515fSKim, Milo 				id + 1, ret);
601ade7515fSKim, Milo 		return ret;
602ade7515fSKim, Milo 	}
603ade7515fSKim, Milo 
604ade7515fSKim, Milo 	ldo->regulator = rdev;
605ade7515fSKim, Milo 	platform_set_drvdata(pdev, ldo);
606ade7515fSKim, Milo 
607ade7515fSKim, Milo 	return 0;
608ade7515fSKim, Milo }
609ade7515fSKim, Milo 
610ade7515fSKim, Milo static struct platform_driver lp8788_aldo_driver = {
611ade7515fSKim, Milo 	.probe = lp8788_aldo_probe,
612ade7515fSKim, Milo 	.driver = {
613ade7515fSKim, Milo 		.name = LP8788_DEV_ALDO,
614ade7515fSKim, Milo 	},
615ade7515fSKim, Milo };
616ade7515fSKim, Milo 
6177629cef1SThierry Reding static struct platform_driver * const drivers[] = {
6187629cef1SThierry Reding 	&lp8788_dldo_driver,
6197629cef1SThierry Reding 	&lp8788_aldo_driver,
6207629cef1SThierry Reding };
6217629cef1SThierry Reding 
622ade7515fSKim, Milo static int __init lp8788_ldo_init(void)
623ade7515fSKim, Milo {
6247629cef1SThierry Reding 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
625ade7515fSKim, Milo }
626ade7515fSKim, Milo subsys_initcall(lp8788_ldo_init);
627ade7515fSKim, Milo 
628ade7515fSKim, Milo static void __exit lp8788_ldo_exit(void)
629ade7515fSKim, Milo {
6307629cef1SThierry Reding 	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
631ade7515fSKim, Milo }
632ade7515fSKim, Milo module_exit(lp8788_ldo_exit);
633ade7515fSKim, Milo 
634ade7515fSKim, Milo MODULE_DESCRIPTION("TI LP8788 LDO Driver");
635ade7515fSKim, Milo MODULE_AUTHOR("Milo Kim");
636ade7515fSKim, Milo MODULE_LICENSE("GPL");
637ade7515fSKim, Milo MODULE_ALIAS("platform:lp8788-dldo");
638ade7515fSKim, Milo MODULE_ALIAS("platform:lp8788-aldo");
639