1a10e763bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2f0168a9bSKeerthy /*
3f0168a9bSKeerthy  * Regulator driver for LP87565 PMIC
4f0168a9bSKeerthy  *
52ca76b3eSAlexander A. Klimov  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
6f0168a9bSKeerthy  */
7f0168a9bSKeerthy 
8f0168a9bSKeerthy #include <linux/module.h>
9f0168a9bSKeerthy #include <linux/platform_device.h>
10f0168a9bSKeerthy #include <linux/regmap.h>
11f0168a9bSKeerthy 
12f0168a9bSKeerthy #include <linux/mfd/lp87565.h>
13f0168a9bSKeerthy 
145258f7eeSLuca Ceresoli enum LP87565_regulator_id {
155258f7eeSLuca Ceresoli 	/* BUCK's */
165258f7eeSLuca Ceresoli 	LP87565_BUCK_0,
175258f7eeSLuca Ceresoli 	LP87565_BUCK_1,
185258f7eeSLuca Ceresoli 	LP87565_BUCK_2,
195258f7eeSLuca Ceresoli 	LP87565_BUCK_3,
205258f7eeSLuca Ceresoli 	LP87565_BUCK_10,
215258f7eeSLuca Ceresoli 	LP87565_BUCK_23,
225258f7eeSLuca Ceresoli 	LP87565_BUCK_3210,
235258f7eeSLuca Ceresoli };
245258f7eeSLuca Ceresoli 
2581fdcef3SLuca Ceresoli #define LP87565_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm,		\
2681fdcef3SLuca Ceresoli 			  _er, _em, _ev, _delay, _lr, _cr)		\
27f0168a9bSKeerthy 	[_id] = {							\
28f0168a9bSKeerthy 		.desc = {						\
29f0168a9bSKeerthy 			.name			= _name,		\
30f0168a9bSKeerthy 			.supply_name		= _of "-in",		\
31f0168a9bSKeerthy 			.id			= _id,			\
32*f410cfe8SChen Jiahao 			.of_match		= _of,			\
33*f410cfe8SChen Jiahao 			.regulators_node	= "regulators",		\
34f0168a9bSKeerthy 			.ops			= &_ops,		\
35f0168a9bSKeerthy 			.n_voltages		= _n,			\
36f0168a9bSKeerthy 			.type			= REGULATOR_VOLTAGE,	\
37f0168a9bSKeerthy 			.owner			= THIS_MODULE,		\
38f0168a9bSKeerthy 			.vsel_reg		= _vr,			\
39f0168a9bSKeerthy 			.vsel_mask		= _vm,			\
40f0168a9bSKeerthy 			.enable_reg		= _er,			\
41f0168a9bSKeerthy 			.enable_mask		= _em,			\
4281fdcef3SLuca Ceresoli 			.enable_val		= _ev,			\
43f0168a9bSKeerthy 			.ramp_delay		= _delay,		\
44f0168a9bSKeerthy 			.linear_ranges		= _lr,			\
45f0168a9bSKeerthy 			.n_linear_ranges	= ARRAY_SIZE(_lr),	\
46d0ccbe11SAxel Lin 			.curr_table = lp87565_buck_uA,			\
47d0ccbe11SAxel Lin 			.n_current_limits = ARRAY_SIZE(lp87565_buck_uA),\
48d0ccbe11SAxel Lin 			.csel_reg = (_cr),				\
49d0ccbe11SAxel Lin 			.csel_mask = LP87565_BUCK_CTRL_2_ILIM,		\
50f0168a9bSKeerthy 		},							\
51f0168a9bSKeerthy 		.ctrl2_reg = _cr,					\
52f0168a9bSKeerthy 	}
53f0168a9bSKeerthy 
54f0168a9bSKeerthy struct lp87565_regulator {
55f0168a9bSKeerthy 	struct regulator_desc desc;
56f0168a9bSKeerthy 	unsigned int ctrl2_reg;
57f0168a9bSKeerthy };
58f0168a9bSKeerthy 
59f0168a9bSKeerthy static const struct lp87565_regulator regulators[];
60f0168a9bSKeerthy 
6160ab7f41SMatti Vaittinen static const struct linear_range buck0_1_2_3_ranges[] = {
6242f1ea48SKeerthy 	REGULATOR_LINEAR_RANGE(600000, 0xA, 0x17, 10000),
63f0168a9bSKeerthy 	REGULATOR_LINEAR_RANGE(735000, 0x18, 0x9d, 5000),
64f0168a9bSKeerthy 	REGULATOR_LINEAR_RANGE(1420000, 0x9e, 0xff, 20000),
65f0168a9bSKeerthy };
66f0168a9bSKeerthy 
67b7fbc592SAxel Lin static const unsigned int lp87565_buck_ramp_delay[] = {
68f0168a9bSKeerthy 	30000, 15000, 10000, 7500, 3800, 1900, 940, 470
69f0168a9bSKeerthy };
70f0168a9bSKeerthy 
71f0168a9bSKeerthy /* LP87565 BUCK current limit */
72f0168a9bSKeerthy static const unsigned int lp87565_buck_uA[] = {
73f0168a9bSKeerthy 	1500000, 2000000, 2500000, 3000000, 3500000, 4000000, 4500000, 5000000,
74f0168a9bSKeerthy };
75f0168a9bSKeerthy 
lp87565_buck_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)76f0168a9bSKeerthy static int lp87565_buck_set_ramp_delay(struct regulator_dev *rdev,
77f0168a9bSKeerthy 				       int ramp_delay)
78f0168a9bSKeerthy {
79f0168a9bSKeerthy 	int id = rdev_get_id(rdev);
80f0168a9bSKeerthy 	unsigned int reg;
81f0168a9bSKeerthy 	int ret;
82f0168a9bSKeerthy 
83f0168a9bSKeerthy 	if (ramp_delay <= 470)
84f0168a9bSKeerthy 		reg = 7;
85f0168a9bSKeerthy 	else if (ramp_delay <= 940)
86f0168a9bSKeerthy 		reg = 6;
87f0168a9bSKeerthy 	else if (ramp_delay <= 1900)
88f0168a9bSKeerthy 		reg = 5;
89f0168a9bSKeerthy 	else if (ramp_delay <= 3800)
90f0168a9bSKeerthy 		reg = 4;
91f0168a9bSKeerthy 	else if (ramp_delay <= 7500)
92f0168a9bSKeerthy 		reg = 3;
93f0168a9bSKeerthy 	else if (ramp_delay <= 10000)
94f0168a9bSKeerthy 		reg = 2;
95f0168a9bSKeerthy 	else if (ramp_delay <= 15000)
96f0168a9bSKeerthy 		reg = 1;
97f0168a9bSKeerthy 	else
98f0168a9bSKeerthy 		reg = 0;
99f0168a9bSKeerthy 
1006cadd8aeSAxel Lin 	ret = regmap_update_bits(rdev->regmap, regulators[id].ctrl2_reg,
101f0168a9bSKeerthy 				 LP87565_BUCK_CTRL_2_SLEW_RATE,
102f0168a9bSKeerthy 				 reg << __ffs(LP87565_BUCK_CTRL_2_SLEW_RATE));
103f0168a9bSKeerthy 	if (ret) {
1046cadd8aeSAxel Lin 		dev_err(&rdev->dev, "SLEW RATE write failed: %d\n", ret);
105f0168a9bSKeerthy 		return ret;
106f0168a9bSKeerthy 	}
107f0168a9bSKeerthy 
108f0168a9bSKeerthy 	rdev->constraints->ramp_delay = lp87565_buck_ramp_delay[reg];
109f0168a9bSKeerthy 
1102d045e94SKeerthy 	/* Conservatively give a 15% margin */
1112d045e94SKeerthy 	rdev->constraints->ramp_delay =
1122d045e94SKeerthy 				rdev->constraints->ramp_delay * 85 / 100;
1132d045e94SKeerthy 
114f0168a9bSKeerthy 	return 0;
115f0168a9bSKeerthy }
116f0168a9bSKeerthy 
117d0ccbe11SAxel Lin /* Operations permitted on BUCKs */
118b7fbc592SAxel Lin static const struct regulator_ops lp87565_buck_ops = {
119f0168a9bSKeerthy 	.is_enabled		= regulator_is_enabled_regmap,
120f0168a9bSKeerthy 	.enable			= regulator_enable_regmap,
121f0168a9bSKeerthy 	.disable		= regulator_disable_regmap,
122f0168a9bSKeerthy 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
123f0168a9bSKeerthy 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
124f0168a9bSKeerthy 	.list_voltage		= regulator_list_voltage_linear_range,
125f0168a9bSKeerthy 	.map_voltage		= regulator_map_voltage_linear_range,
126f0168a9bSKeerthy 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
127f0168a9bSKeerthy 	.set_ramp_delay		= lp87565_buck_set_ramp_delay,
128d0ccbe11SAxel Lin 	.set_current_limit	= regulator_set_current_limit_regmap,
129d0ccbe11SAxel Lin 	.get_current_limit	= regulator_get_current_limit_regmap,
130f0168a9bSKeerthy };
131f0168a9bSKeerthy 
132f0168a9bSKeerthy static const struct lp87565_regulator regulators[] = {
133f0168a9bSKeerthy 	LP87565_REGULATOR("BUCK0", LP87565_BUCK_0, "buck0", lp87565_buck_ops,
134f0168a9bSKeerthy 			  256, LP87565_REG_BUCK0_VOUT, LP87565_BUCK_VSET,
135f0168a9bSKeerthy 			  LP87565_REG_BUCK0_CTRL_1,
13681fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
13781fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
1382d045e94SKeerthy 			  LP87565_BUCK_CTRL_1_EN, 3230,
139f0168a9bSKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2),
140f0168a9bSKeerthy 	LP87565_REGULATOR("BUCK1", LP87565_BUCK_1, "buck1", lp87565_buck_ops,
141f0168a9bSKeerthy 			  256, LP87565_REG_BUCK1_VOUT, LP87565_BUCK_VSET,
142f0168a9bSKeerthy 			  LP87565_REG_BUCK1_CTRL_1,
14381fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
14481fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
1452d045e94SKeerthy 			  LP87565_BUCK_CTRL_1_EN, 3230,
146f0168a9bSKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK1_CTRL_2),
147f0168a9bSKeerthy 	LP87565_REGULATOR("BUCK2", LP87565_BUCK_2, "buck2", lp87565_buck_ops,
148f0168a9bSKeerthy 			  256, LP87565_REG_BUCK2_VOUT, LP87565_BUCK_VSET,
149f0168a9bSKeerthy 			  LP87565_REG_BUCK2_CTRL_1,
15081fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
15181fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
1522d045e94SKeerthy 			  LP87565_BUCK_CTRL_1_EN, 3230,
153f0168a9bSKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK2_CTRL_2),
154f0168a9bSKeerthy 	LP87565_REGULATOR("BUCK3", LP87565_BUCK_3, "buck3", lp87565_buck_ops,
155f0168a9bSKeerthy 			  256, LP87565_REG_BUCK3_VOUT, LP87565_BUCK_VSET,
156f0168a9bSKeerthy 			  LP87565_REG_BUCK3_CTRL_1,
15781fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
15881fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
1592d045e94SKeerthy 			  LP87565_BUCK_CTRL_1_EN, 3230,
160f0168a9bSKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK3_CTRL_2),
161f0168a9bSKeerthy 	LP87565_REGULATOR("BUCK10", LP87565_BUCK_10, "buck10", lp87565_buck_ops,
162f0168a9bSKeerthy 			  256, LP87565_REG_BUCK0_VOUT, LP87565_BUCK_VSET,
163f0168a9bSKeerthy 			  LP87565_REG_BUCK0_CTRL_1,
1642f51a260SKeerthy 			  LP87565_BUCK_CTRL_1_EN |
16581fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL |
16681fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2,
16781fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
1682f51a260SKeerthy 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2, 3230,
169f0168a9bSKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2),
170f0168a9bSKeerthy 	LP87565_REGULATOR("BUCK23", LP87565_BUCK_23, "buck23", lp87565_buck_ops,
171f0168a9bSKeerthy 			  256, LP87565_REG_BUCK2_VOUT, LP87565_BUCK_VSET,
172f0168a9bSKeerthy 			  LP87565_REG_BUCK2_CTRL_1,
17381fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
17481fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
1752d045e94SKeerthy 			  LP87565_BUCK_CTRL_1_EN, 3230,
176f0168a9bSKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK2_CTRL_2),
1777ee63bd7SKeerthy 	LP87565_REGULATOR("BUCK3210", LP87565_BUCK_3210, "buck3210",
1787ee63bd7SKeerthy 			  lp87565_buck_ops, 256, LP87565_REG_BUCK0_VOUT,
1797ee63bd7SKeerthy 			  LP87565_BUCK_VSET, LP87565_REG_BUCK0_CTRL_1,
1807ee63bd7SKeerthy 			  LP87565_BUCK_CTRL_1_EN |
18181fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL |
18281fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2,
18381fdcef3SLuca Ceresoli 			  LP87565_BUCK_CTRL_1_EN |
1847ee63bd7SKeerthy 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2, 3230,
1857ee63bd7SKeerthy 			  buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2),
186f0168a9bSKeerthy };
187f0168a9bSKeerthy 
lp87565_regulator_probe(struct platform_device * pdev)188f0168a9bSKeerthy static int lp87565_regulator_probe(struct platform_device *pdev)
189f0168a9bSKeerthy {
190f0168a9bSKeerthy 	struct lp87565 *lp87565 = dev_get_drvdata(pdev->dev.parent);
191f0168a9bSKeerthy 	struct regulator_config config = { };
192f0168a9bSKeerthy 	struct regulator_dev *rdev;
193a853c0a0SAxel Lin 	int i, min_idx, max_idx;
194f0168a9bSKeerthy 
195f0168a9bSKeerthy 	platform_set_drvdata(pdev, lp87565);
196f0168a9bSKeerthy 
197f0168a9bSKeerthy 	config.dev = &pdev->dev;
198f0168a9bSKeerthy 	config.dev->of_node = lp87565->dev->of_node;
199f0168a9bSKeerthy 	config.driver_data = lp87565;
200f0168a9bSKeerthy 	config.regmap = lp87565->regmap;
201f0168a9bSKeerthy 
2027ee63bd7SKeerthy 	switch (lp87565->dev_type) {
2037ee63bd7SKeerthy 	case LP87565_DEVICE_TYPE_LP87565_Q1:
204f0168a9bSKeerthy 		min_idx = LP87565_BUCK_10;
205f0168a9bSKeerthy 		max_idx = LP87565_BUCK_23;
2067ee63bd7SKeerthy 		break;
2077ee63bd7SKeerthy 	case LP87565_DEVICE_TYPE_LP87561_Q1:
2087ee63bd7SKeerthy 		min_idx = LP87565_BUCK_3210;
2097ee63bd7SKeerthy 		max_idx = LP87565_BUCK_3210;
210f3f4363bSColin Ian King 		break;
2117ee63bd7SKeerthy 	default:
212a853c0a0SAxel Lin 		min_idx = LP87565_BUCK_0;
213a853c0a0SAxel Lin 		max_idx = LP87565_BUCK_3;
214a853c0a0SAxel Lin 		break;
215f0168a9bSKeerthy 	}
216f0168a9bSKeerthy 
217f0168a9bSKeerthy 	for (i = min_idx; i <= max_idx; i++) {
218f0168a9bSKeerthy 		rdev = devm_regulator_register(&pdev->dev, &regulators[i].desc,
219f0168a9bSKeerthy 					       &config);
220f0168a9bSKeerthy 		if (IS_ERR(rdev)) {
221f0168a9bSKeerthy 			dev_err(lp87565->dev, "failed to register %s regulator\n",
222f0168a9bSKeerthy 				pdev->name);
223f0168a9bSKeerthy 			return PTR_ERR(rdev);
224f0168a9bSKeerthy 		}
225f0168a9bSKeerthy 	}
226f0168a9bSKeerthy 
227f0168a9bSKeerthy 	return 0;
228f0168a9bSKeerthy }
229f0168a9bSKeerthy 
230f0168a9bSKeerthy static const struct platform_device_id lp87565_regulator_id_table[] = {
231f0168a9bSKeerthy 	{ "lp87565-regulator", },
232f0168a9bSKeerthy 	{ "lp87565-q1-regulator", },
233f0168a9bSKeerthy 	{ /* sentinel */ }
234f0168a9bSKeerthy };
235f0168a9bSKeerthy MODULE_DEVICE_TABLE(platform, lp87565_regulator_id_table);
236f0168a9bSKeerthy 
237f0168a9bSKeerthy static struct platform_driver lp87565_regulator_driver = {
238f0168a9bSKeerthy 	.driver = {
239f0168a9bSKeerthy 		.name = "lp87565-pmic",
240259b93b2SDouglas Anderson 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
241f0168a9bSKeerthy 	},
242f0168a9bSKeerthy 	.probe = lp87565_regulator_probe,
243f0168a9bSKeerthy 	.id_table = lp87565_regulator_id_table,
244f0168a9bSKeerthy };
245f0168a9bSKeerthy module_platform_driver(lp87565_regulator_driver);
246f0168a9bSKeerthy 
247f0168a9bSKeerthy MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
248f0168a9bSKeerthy MODULE_DESCRIPTION("LP87565 voltage regulator driver");
249f0168a9bSKeerthy MODULE_LICENSE("GPL v2");
250