1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * DA9121 Single-channel dual-phase 10A buck converter 4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive) 5 * DA9217 Single-channel dual-phase 6A buck converter 6 * DA9122 Dual-channel single-phase 5A buck converter 7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive) 8 * DA9220 Dual-channel single-phase 3A buck converter 9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive) 10 * 11 * Copyright (C) 2020 Dialog Semiconductor 12 * 13 * Authors: Steve Twiss, Dialog Semiconductor 14 * Adam Ward, Dialog Semiconductor 15 */ 16 17 #ifndef __DA9121_REGISTERS_H__ 18 #define __DA9121_REGISTERS_H__ 19 20 /* Values for: DA9121_REG_BUCK_BUCKx_4 registers, fields CHx_y_MODE 21 * DA9121_REG_BUCK_BUCKx_7 registers, fields CHx_RIPPLE_CANCEL 22 */ 23 #include <dt-bindings/regulator/dlg,da9121-regulator.h> 24 25 enum da9121_variant { 26 DA9121_TYPE_DA9121_DA9130, 27 DA9121_TYPE_DA9220_DA9132, 28 DA9121_TYPE_DA9122_DA9131, 29 DA9121_TYPE_DA9217 30 }; 31 32 /* Minimum, maximum and default polling millisecond periods are provided 33 * here as an example. It is expected that any final implementation will 34 * include a modification of these settings to match the required 35 * application. 36 */ 37 #define DA9121_DEFAULT_POLLING_PERIOD_MS 3000 38 #define DA9121_MAX_POLLING_PERIOD_MS 10000 39 #define DA9121_MIN_POLLING_PERIOD_MS 1000 40 41 /* Registers */ 42 43 #define DA9121_REG_SYS_STATUS_0 0x01 44 #define DA9121_REG_SYS_STATUS_1 0x02 45 #define DA9121_REG_SYS_STATUS_2 0x03 46 #define DA9121_REG_SYS_EVENT_0 0x04 47 #define DA9121_REG_SYS_EVENT_1 0x05 48 #define DA9121_REG_SYS_EVENT_2 0x06 49 #define DA9121_REG_SYS_MASK_0 0x07 50 #define DA9121_REG_SYS_MASK_1 0x08 51 #define DA9121_REG_SYS_MASK_2 0x09 52 #define DA9121_REG_SYS_MASK_3 0x0A 53 #define DA9121_REG_SYS_CONFIG_0 0x0B 54 #define DA9121_REG_SYS_CONFIG_1 0x0C 55 #define DA9121_REG_SYS_CONFIG_2 0x0D 56 #define DA9121_REG_SYS_CONFIG_3 0x0E 57 #define DA9121_REG_SYS_GPIO0_0 0x10 58 #define DA9121_REG_SYS_GPIO0_1 0x11 59 #define DA9121_REG_SYS_GPIO1_0 0x12 60 #define DA9121_REG_SYS_GPIO1_1 0x13 61 #define DA9121_REG_SYS_GPIO2_0 0x14 62 #define DA9121_REG_SYS_GPIO2_1 0x15 63 #define DA9121_REG_BUCK_BUCK1_0 0x20 64 #define DA9121_REG_BUCK_BUCK1_1 0x21 65 #define DA9121_REG_BUCK_BUCK1_2 0x22 66 #define DA9121_REG_BUCK_BUCK1_3 0x23 67 #define DA9121_REG_BUCK_BUCK1_4 0x24 68 #define DA9121_REG_BUCK_BUCK1_5 0x25 69 #define DA9121_REG_BUCK_BUCK1_6 0x26 70 #define DA9121_REG_BUCK_BUCK1_7 0x27 71 #define DA9xxx_REG_BUCK_BUCK2_0 0x28 72 #define DA9xxx_REG_BUCK_BUCK2_1 0x29 73 #define DA9xxx_REG_BUCK_BUCK2_2 0x2A 74 #define DA9xxx_REG_BUCK_BUCK2_3 0x2B 75 #define DA9xxx_REG_BUCK_BUCK2_4 0x2C 76 #define DA9xxx_REG_BUCK_BUCK2_5 0x2D 77 #define DA9xxx_REG_BUCK_BUCK2_6 0x2E 78 #define DA9xxx_REG_BUCK_BUCK2_7 0x2F 79 #define DA9121_REG_OTP_DEVICE_ID 0x48 80 #define DA9121_REG_OTP_VARIANT_ID 0x49 81 #define DA9121_REG_OTP_CUSTOMER_ID 0x4A 82 #define DA9121_REG_OTP_CONFIG_ID 0x4B 83 84 /* Register bits */ 85 86 /* DA9121_REG_SYS_STATUS_0 */ 87 88 #define DA9xxx_MASK_SYS_STATUS_0_SG BIT(2) 89 #define DA9121_MASK_SYS_STATUS_0_TEMP_CRIT BIT(1) 90 #define DA9121_MASK_SYS_STATUS_0_TEMP_WARN BIT(0) 91 92 /* DA9121_REG_SYS_STATUS_1 */ 93 94 #define DA9xxx_MASK_SYS_STATUS_1_PG2 BIT(7) 95 #define DA9xxx_MASK_SYS_STATUS_1_OV2 BIT(6) 96 #define DA9xxx_MASK_SYS_STATUS_1_UV2 BIT(5) 97 #define DA9xxx_MASK_SYS_STATUS_1_OC2 BIT(4) 98 #define DA9121_MASK_SYS_STATUS_1_PG1 BIT(3) 99 #define DA9121_MASK_SYS_STATUS_1_OV1 BIT(2) 100 #define DA9121_MASK_SYS_STATUS_1_UV1 BIT(1) 101 #define DA9121_MASK_SYS_STATUS_1_OC1 BIT(0) 102 103 /* DA9121_REG_SYS_STATUS_2 */ 104 105 #define DA9121_MASK_SYS_STATUS_2_GPIO2 BIT(2) 106 #define DA9121_MASK_SYS_STATUS_2_GPIO1 BIT(1) 107 #define DA9121_MASK_SYS_STATUS_2_GPIO0 BIT(0) 108 109 /* DA9121_REG_SYS_EVENT_0 */ 110 111 #define DA9xxx_MASK_SYS_EVENT_0_E_SG BIT(2) 112 #define DA9121_MASK_SYS_EVENT_0_E_TEMP_CRIT BIT(1) 113 #define DA9121_MASK_SYS_EVENT_0_E_TEMP_WARN BIT(0) 114 115 /* DA9121_REG_SYS_EVENT_1 */ 116 117 #define DA9xxx_MASK_SYS_EVENT_1_E_PG2 BIT(7) 118 #define DA9xxx_MASK_SYS_EVENT_1_E_OV2 BIT(6) 119 #define DA9xxx_MASK_SYS_EVENT_1_E_UV2 BIT(5) 120 #define DA9xxx_MASK_SYS_EVENT_1_E_OC2 BIT(4) 121 #define DA9121_MASK_SYS_EVENT_1_E_PG1 BIT(3) 122 #define DA9121_MASK_SYS_EVENT_1_E_OV1 BIT(2) 123 #define DA9121_MASK_SYS_EVENT_1_E_UV1 BIT(1) 124 #define DA9121_MASK_SYS_EVENT_1_E_OC1 BIT(0) 125 126 /* DA9121_REG_SYS_EVENT_2 */ 127 128 #define DA9121_MASK_SYS_EVENT_2_E_GPIO2 BIT(2) 129 #define DA9121_MASK_SYS_EVENT_2_E_GPIO1 BIT(1) 130 #define DA9121_MASK_SYS_EVENT_2_E_GPIO0 BIT(0) 131 132 /* DA9121_REG_SYS_MASK_0 */ 133 134 #define DA9xxx_MASK_SYS_MASK_0_M_SG BIT(2) 135 #define DA9121_MASK_SYS_MASK_0_M_TEMP_CRIT BIT(1) 136 #define DA9121_MASK_SYS_MASK_0_M_TEMP_WARN BIT(0) 137 138 /* DA9121_REG_SYS_MASK_1 */ 139 140 #define DA9xxx_MASK_SYS_MASK_1_M_PG2 BIT(7) 141 #define DA9xxx_MASK_SYS_MASK_1_M_OV2 BIT(6) 142 #define DA9xxx_MASK_SYS_MASK_1_M_UV2 BIT(5) 143 #define DA9xxx_MASK_SYS_MASK_1_M_OC2 BIT(4) 144 #define DA9121_MASK_SYS_MASK_1_M_PG1 BIT(3) 145 #define DA9121_MASK_SYS_MASK_1_M_OV1 BIT(2) 146 #define DA9121_MASK_SYS_MASK_1_M_UV1 BIT(1) 147 #define DA9121_MASK_SYS_MASK_1_M_OC1 BIT(0) 148 149 /* DA9121_REG_SYS_MASK_2 */ 150 151 #define DA9121_MASK_SYS_MASK_2_M_GPIO2 BIT(2) 152 #define DA9121_MASK_SYS_MASK_2_M_GPIO1 BIT(1) 153 #define DA9121_MASK_SYS_MASK_2_M_GPIO0 BIT(0) 154 155 /* DA9122_REG_SYS_MASK_3 */ 156 157 #define DA9121_MASK_SYS_MASK_3_M_VR_HOT BIT(3) 158 #define DA9xxx_MASK_SYS_MASK_3_M_SG_STAT BIT(2) 159 #define DA9xxx_MASK_SYS_MASK_3_M_PG2_STAT BIT(1) 160 #define DA9121_MASK_SYS_MASK_3_M_PG1_STAT BIT(0) 161 162 /* DA9121_REG_SYS_CONFIG_0 */ 163 164 #define DA9121_MASK_SYS_CONFIG_0_CH1_DIS_DLY 0xF0 165 #define DA9121_MASK_SYS_CONFIG_0_CH1_EN_DLY 0x0F 166 167 /* DA9xxx_REG_SYS_CONFIG_1 */ 168 169 #define DA9xxx_MASK_SYS_CONFIG_1_CH2_DIS_DLY 0xF0 170 #define DA9xxx_MASK_SYS_CONFIG_1_CH2_EN_DLY 0x0F 171 172 /* DA9121_REG_SYS_CONFIG_2 */ 173 174 #define DA9121_MASK_SYS_CONFIG_2_OC_LATCHOFF 0x60 175 #define DA9121_MASK_SYS_CONFIG_2_OC_DVC_MASK BIT(4) 176 #define DA9121_MASK_SYS_CONFIG_2_PG_DVC_MASK 0x0C 177 178 /* DA9121_REG_SYS_CONFIG_3 */ 179 180 #define DA9121_MASK_SYS_CONFIG_3_OSC_TUNE 0X70 181 #define DA9121_MASK_SYS_CONFIG_3_I2C_TIMEOUT BIT(1) 182 183 /* DA9121_REG_SYS_GPIO0_0 */ 184 185 #define DA9121_MASK_SYS_GPIO0_0_GPIO0_MODE 0X1E 186 #define DA9121_MASK_SYS_GPIO0_0_GPIO0_OBUF BIT(0) 187 188 /* DA9121_REG_SYS_GPIO0_1 */ 189 190 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_FALL BIT(7) 191 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_RISE BIT(6) 192 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB 0x30 193 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_PUPD BIT(3) 194 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_POL BIT(2) 195 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_TRIG 0x03 196 197 /* DA9121_REG_SYS_GPIO1_0 */ 198 199 #define DA9121_MASK_SYS_GPIO1_0_GPIO1_MODE 0x1E 200 #define DA9121_MASK_SYS_GPIO1_0_GPIO1_OBUF BIT(0) 201 202 /* DA9121_REG_SYS_GPIO1_1 */ 203 204 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_FALL BIT(7) 205 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_RISE BIT(6) 206 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB 0x30 207 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_PUPD BIT(3) 208 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_POL BIT(2) 209 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_TRIG 0x03 210 211 /* DA9121_REG_SYS_GPIO2_0 */ 212 213 #define DA9121_MASK_SYS_GPIO2_0_GPIO2_MODE 0x1E 214 #define DA9121_MASK_SYS_GPIO2_0_GPIO2_OBUF BIT(0) 215 216 /* DA9121_REG_SYS_GPIO2_1 */ 217 218 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_FALL BIT(7) 219 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_RISE BIT(6) 220 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB 0x30 221 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_PUPD BIT(3) 222 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_POL BIT(2) 223 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_TRIG 0x03 224 225 /* DA9121_REG_BUCK_BUCK1_0 / DA9xxx_REG_BUCK_BUCK2_0 */ 226 227 #define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_DWN 0x70 228 #define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_UP 0x0E 229 #define DA9121_MASK_BUCK_BUCKx_0_CHx_EN BIT(0) 230 231 /* DA9121_REG_BUCK_BUCK1_1 / DA9xxx_REG_BUCK_BUCK2_1 */ 232 233 #define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_SHDN 0x70 234 #define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_STARTUP 0x0E 235 #define DA9121_MASK_BUCK_BUCKx_1_CHx_PD_DIS BIT(0) 236 237 /* DA9121_REG_BUCK_BUCK1_2 / DA9xxx_REG_BUCK_BUCK2_2 */ 238 239 #define DA9121_MASK_BUCK_BUCKx_2_CHx_ILIM 0x0F 240 241 /* DA9121_REG_BUCK_BUCK1_3 / DA9xxx_REG_BUCK_BUCK2_3 */ 242 243 #define DA9121_MASK_BUCK_BUCKx_3_CHx_VMAX 0xFF 244 245 /* DA9121_REG_BUCK_BUCK1_4 / DA9xxx_REG_BUCK_BUCK2_4 */ 246 247 #define DA9121_MASK_BUCK_BUCKx_4_CHx_VSEL BIT(4) 248 #define DA9121_MASK_BUCK_BUCKx_4_CHx_B_MODE 0x0C 249 #define DA9121_MASK_BUCK_BUCKx_4_CHx_A_MODE 0x03 250 251 /* DA9121_REG_BUCK_BUCK1_5 / DA9xxx_REG_BUCK_BUCK2_5 */ 252 253 #define DA9121_MASK_BUCK_BUCKx_5_CHx_A_VOUT 0xFF 254 255 /* DA9121_REG_BUCK_BUCK1_6 / DA9xxx_REG_BUCK_BUCK2_6 */ 256 257 #define DA9121_MASK_BUCK_BUCKx_6_CHx_B_VOUT 0xFF 258 259 /* DA9121_REG_BUCK_BUCK1_7 / DA9xxx_REG_BUCK_BUCK2_7 */ 260 261 #define DA9xxx_MASK_BUCK_BUCKx_7_CHx_RIPPLE_CANCEL 0x03 262 263 264 /* DA9121_REG_OTP_DEVICE_ID */ 265 266 #define DA9121_MASK_OTP_DEVICE_ID_DEV_ID 0xFF 267 268 #define DA9121_DEVICE_ID 0x05 269 270 /* DA9121_REG_OTP_VARIANT_ID */ 271 272 #define DA9121_SHIFT_OTP_VARIANT_ID_MRC 4 273 #define DA9121_MASK_OTP_VARIANT_ID_MRC 0xF0 274 #define DA9121_SHIFT_OTP_VARIANT_ID_VRC 0 275 #define DA9121_MASK_OTP_VARIANT_ID_VRC 0x0F 276 277 #define DA9121_VARIANT_MRC_BASE 0x2 278 #define DA9121_VARIANT_VRC 0x1 279 #define DA9220_VARIANT_VRC 0x0 280 #define DA9122_VARIANT_VRC 0x2 281 #define DA9217_VARIANT_VRC 0x7 282 283 /* DA9121_REG_OTP_CUSTOMER_ID */ 284 285 #define DA9121_MASK_OTP_CUSTOMER_ID_CUST_ID 0xFF 286 287 /* DA9121_REG_OTP_CONFIG_ID */ 288 289 #define DA9121_MASK_OTP_CONFIG_ID_CONFIG_REV 0xFF 290 291 #endif /* __DA9121_REGISTERS_H__ */ 292