1 /* 2 * AXP20x regulators driver. 3 * 4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General 7 * Public License. See the file "COPYING" in the main directory of this 8 * archive for more details. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/mfd/axp20x.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/regulator/machine.h> 28 #include <linux/regulator/of_regulator.h> 29 30 #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0) 31 #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0) 32 33 #define AXP20X_IO_ENABLED 0x03 34 #define AXP20X_IO_DISABLED 0x07 35 36 #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2) 37 #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1) 38 39 #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0) 40 41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2) 42 43 #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0) 44 #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0) 45 #define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4) 46 #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0) 47 #define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0) 48 #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4) 49 50 #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0) 51 #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1) 52 #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2) 53 #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3) 54 #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4) 55 #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6) 56 57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0) 58 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \ 59 ((x) << 0) 60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1) 61 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \ 62 ((x) << 1) 63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2) 64 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2) 65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3) 66 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3) 67 68 #define AXP20X_LDO4_V_OUT_1250mV_START 0x0 69 #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0 70 #define AXP20X_LDO4_V_OUT_1250mV_END \ 71 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS) 72 #define AXP20X_LDO4_V_OUT_1300mV_START 0x1 73 #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7 74 #define AXP20X_LDO4_V_OUT_1300mV_END \ 75 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS) 76 #define AXP20X_LDO4_V_OUT_2500mV_START 0x9 77 #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0 78 #define AXP20X_LDO4_V_OUT_2500mV_END \ 79 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS) 80 #define AXP20X_LDO4_V_OUT_2700mV_START 0xa 81 #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1 82 #define AXP20X_LDO4_V_OUT_2700mV_END \ 83 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS) 84 #define AXP20X_LDO4_V_OUT_3000mV_START 0xc 85 #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3 86 #define AXP20X_LDO4_V_OUT_3000mV_END \ 87 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS) 88 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16 89 90 #define AXP22X_IO_ENABLED 0x03 91 #define AXP22X_IO_DISABLED 0x04 92 93 #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x) 94 95 #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) 96 97 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0) 98 #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0) 99 #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0) 100 #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0) 101 #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0) 102 #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0) 103 #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0) 104 #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0) 105 #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0) 106 #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0) 107 #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0) 108 #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0) 109 #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0) 110 #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0) 111 #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0) 112 #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0) 113 #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0) 114 #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0) 115 116 #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0) 117 #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1) 118 #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2) 119 #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3) 120 #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4) 121 #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5) 122 #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6) 123 #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7) 124 125 #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6) 126 #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7) 127 128 #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0) 129 #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1) 130 #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2) 131 #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3) 132 #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4) 133 #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5) 134 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6) 135 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7) 136 137 #define AXP313A_DCDC1_NUM_VOLTAGES 107 138 #define AXP313A_DCDC23_NUM_VOLTAGES 88 139 #define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0) 140 #define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0) 141 142 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) 143 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) 144 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) 145 #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3) 146 #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4) 147 #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5) 148 149 #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2) 150 #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3) 151 152 #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0) 153 #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0) 154 #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0) 155 #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0) 156 #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0) 157 #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0) 158 159 #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0) 160 #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0) 161 162 #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6) 163 #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5) 164 165 #define AXP803_DCDC234_500mV_START 0x00 166 #define AXP803_DCDC234_500mV_STEPS 70 167 #define AXP803_DCDC234_500mV_END \ 168 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS) 169 #define AXP803_DCDC234_1220mV_START 0x47 170 #define AXP803_DCDC234_1220mV_STEPS 4 171 #define AXP803_DCDC234_1220mV_END \ 172 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS) 173 #define AXP803_DCDC234_NUM_VOLTAGES 76 174 175 #define AXP803_DCDC5_800mV_START 0x00 176 #define AXP803_DCDC5_800mV_STEPS 32 177 #define AXP803_DCDC5_800mV_END \ 178 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS) 179 #define AXP803_DCDC5_1140mV_START 0x21 180 #define AXP803_DCDC5_1140mV_STEPS 35 181 #define AXP803_DCDC5_1140mV_END \ 182 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS) 183 #define AXP803_DCDC5_NUM_VOLTAGES 69 184 185 #define AXP803_DCDC6_600mV_START 0x00 186 #define AXP803_DCDC6_600mV_STEPS 50 187 #define AXP803_DCDC6_600mV_END \ 188 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS) 189 #define AXP803_DCDC6_1120mV_START 0x33 190 #define AXP803_DCDC6_1120mV_STEPS 20 191 #define AXP803_DCDC6_1120mV_END \ 192 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) 193 #define AXP803_DCDC6_NUM_VOLTAGES 72 194 195 #define AXP803_DLDO2_700mV_START 0x00 196 #define AXP803_DLDO2_700mV_STEPS 26 197 #define AXP803_DLDO2_700mV_END \ 198 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS) 199 #define AXP803_DLDO2_3400mV_START 0x1b 200 #define AXP803_DLDO2_3400mV_STEPS 4 201 #define AXP803_DLDO2_3400mV_END \ 202 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS) 203 #define AXP803_DLDO2_NUM_VOLTAGES 32 204 205 #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0) 206 #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0) 207 #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0) 208 #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0) 209 #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0) 210 #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0) 211 #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0) 212 #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0) 213 #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0) 214 #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0) 215 #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0) 216 #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0) 217 #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0) 218 #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0) 219 #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0) 220 221 #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0) 222 #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1) 223 #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2) 224 #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3) 225 #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4) 226 #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5) 227 #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6) 228 #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7) 229 #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0) 230 #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1) 231 #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2) 232 #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3) 233 #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4) 234 #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5) 235 #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6) 236 #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7) 237 238 #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40 239 #define AXP806_DCDCABC_POLYPHASE_TRI 0x80 240 #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6) 241 242 #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5) 243 244 #define AXP806_DCDCA_600mV_START 0x00 245 #define AXP806_DCDCA_600mV_STEPS 50 246 #define AXP806_DCDCA_600mV_END \ 247 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS) 248 #define AXP806_DCDCA_1120mV_START 0x33 249 #define AXP806_DCDCA_1120mV_STEPS 20 250 #define AXP806_DCDCA_1120mV_END \ 251 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS) 252 #define AXP806_DCDCA_NUM_VOLTAGES 72 253 254 #define AXP806_DCDCD_600mV_START 0x00 255 #define AXP806_DCDCD_600mV_STEPS 45 256 #define AXP806_DCDCD_600mV_END \ 257 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS) 258 #define AXP806_DCDCD_1600mV_START 0x2e 259 #define AXP806_DCDCD_1600mV_STEPS 17 260 #define AXP806_DCDCD_1600mV_END \ 261 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS) 262 #define AXP806_DCDCD_NUM_VOLTAGES 64 263 264 #define AXP809_DCDC4_600mV_START 0x00 265 #define AXP809_DCDC4_600mV_STEPS 47 266 #define AXP809_DCDC4_600mV_END \ 267 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS) 268 #define AXP809_DCDC4_1800mV_START 0x30 269 #define AXP809_DCDC4_1800mV_STEPS 8 270 #define AXP809_DCDC4_1800mV_END \ 271 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS) 272 #define AXP809_DCDC4_NUM_VOLTAGES 57 273 274 #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0) 275 276 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6) 277 278 #define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0) 279 #define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0) 280 #define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0) 281 #define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0) 282 #define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0) 283 #define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0) 284 #define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0) 285 #define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0) 286 #define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0) 287 #define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0) 288 #define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0) 289 #define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0) 290 #define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0) 291 #define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0) 292 #define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0) 293 #define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0) 294 #define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0) 295 #define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0) 296 #define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0) 297 #define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0) 298 #define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0) 299 300 #define AXP15060_PWR_OUT_DCDC1_MASK BIT_MASK(0) 301 #define AXP15060_PWR_OUT_DCDC2_MASK BIT_MASK(1) 302 #define AXP15060_PWR_OUT_DCDC3_MASK BIT_MASK(2) 303 #define AXP15060_PWR_OUT_DCDC4_MASK BIT_MASK(3) 304 #define AXP15060_PWR_OUT_DCDC5_MASK BIT_MASK(4) 305 #define AXP15060_PWR_OUT_DCDC6_MASK BIT_MASK(5) 306 #define AXP15060_PWR_OUT_ALDO1_MASK BIT_MASK(0) 307 #define AXP15060_PWR_OUT_ALDO2_MASK BIT_MASK(1) 308 #define AXP15060_PWR_OUT_ALDO3_MASK BIT_MASK(2) 309 #define AXP15060_PWR_OUT_ALDO4_MASK BIT_MASK(3) 310 #define AXP15060_PWR_OUT_ALDO5_MASK BIT_MASK(4) 311 #define AXP15060_PWR_OUT_BLDO1_MASK BIT_MASK(5) 312 #define AXP15060_PWR_OUT_BLDO2_MASK BIT_MASK(6) 313 #define AXP15060_PWR_OUT_BLDO3_MASK BIT_MASK(7) 314 #define AXP15060_PWR_OUT_BLDO4_MASK BIT_MASK(0) 315 #define AXP15060_PWR_OUT_BLDO5_MASK BIT_MASK(1) 316 #define AXP15060_PWR_OUT_CLDO1_MASK BIT_MASK(2) 317 #define AXP15060_PWR_OUT_CLDO2_MASK BIT_MASK(3) 318 #define AXP15060_PWR_OUT_CLDO3_MASK BIT_MASK(4) 319 #define AXP15060_PWR_OUT_CLDO4_MASK BIT_MASK(5) 320 #define AXP15060_PWR_OUT_CPUSLDO_MASK BIT_MASK(6) 321 #define AXP15060_PWR_OUT_SW_MASK BIT_MASK(7) 322 323 #define AXP15060_DCDC23_POLYPHASE_DUAL_MASK BIT_MASK(6) 324 #define AXP15060_DCDC46_POLYPHASE_DUAL_MASK BIT_MASK(7) 325 326 #define AXP15060_DCDC234_500mV_START 0x00 327 #define AXP15060_DCDC234_500mV_STEPS 70 328 #define AXP15060_DCDC234_500mV_END \ 329 (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS) 330 #define AXP15060_DCDC234_1220mV_START 0x47 331 #define AXP15060_DCDC234_1220mV_STEPS 16 332 #define AXP15060_DCDC234_1220mV_END \ 333 (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS) 334 #define AXP15060_DCDC234_NUM_VOLTAGES 88 335 336 #define AXP15060_DCDC5_800mV_START 0x00 337 #define AXP15060_DCDC5_800mV_STEPS 32 338 #define AXP15060_DCDC5_800mV_END \ 339 (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS) 340 #define AXP15060_DCDC5_1140mV_START 0x21 341 #define AXP15060_DCDC5_1140mV_STEPS 35 342 #define AXP15060_DCDC5_1140mV_END \ 343 (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS) 344 #define AXP15060_DCDC5_NUM_VOLTAGES 69 345 346 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 347 _vmask, _ereg, _emask, _enable_val, _disable_val) \ 348 [_family##_##_id] = { \ 349 .name = (_match), \ 350 .supply_name = (_supply), \ 351 .of_match = of_match_ptr(_match), \ 352 .regulators_node = of_match_ptr("regulators"), \ 353 .type = REGULATOR_VOLTAGE, \ 354 .id = _family##_##_id, \ 355 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 356 .owner = THIS_MODULE, \ 357 .min_uV = (_min) * 1000, \ 358 .uV_step = (_step) * 1000, \ 359 .vsel_reg = (_vreg), \ 360 .vsel_mask = (_vmask), \ 361 .enable_reg = (_ereg), \ 362 .enable_mask = (_emask), \ 363 .enable_val = (_enable_val), \ 364 .disable_val = (_disable_val), \ 365 .ops = &axp20x_ops, \ 366 } 367 368 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 369 _vmask, _ereg, _emask) \ 370 [_family##_##_id] = { \ 371 .name = (_match), \ 372 .supply_name = (_supply), \ 373 .of_match = of_match_ptr(_match), \ 374 .regulators_node = of_match_ptr("regulators"), \ 375 .type = REGULATOR_VOLTAGE, \ 376 .id = _family##_##_id, \ 377 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 378 .owner = THIS_MODULE, \ 379 .min_uV = (_min) * 1000, \ 380 .uV_step = (_step) * 1000, \ 381 .vsel_reg = (_vreg), \ 382 .vsel_mask = (_vmask), \ 383 .enable_reg = (_ereg), \ 384 .enable_mask = (_emask), \ 385 .ops = &axp20x_ops, \ 386 } 387 388 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ 389 [_family##_##_id] = { \ 390 .name = (_match), \ 391 .supply_name = (_supply), \ 392 .of_match = of_match_ptr(_match), \ 393 .regulators_node = of_match_ptr("regulators"), \ 394 .type = REGULATOR_VOLTAGE, \ 395 .id = _family##_##_id, \ 396 .owner = THIS_MODULE, \ 397 .enable_reg = (_ereg), \ 398 .enable_mask = (_emask), \ 399 .ops = &axp20x_ops_sw, \ 400 } 401 402 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ 403 [_family##_##_id] = { \ 404 .name = (_match), \ 405 .supply_name = (_supply), \ 406 .of_match = of_match_ptr(_match), \ 407 .regulators_node = of_match_ptr("regulators"), \ 408 .type = REGULATOR_VOLTAGE, \ 409 .id = _family##_##_id, \ 410 .n_voltages = 1, \ 411 .owner = THIS_MODULE, \ 412 .min_uV = (_volt) * 1000, \ 413 .ops = &axp20x_ops_fixed \ 414 } 415 416 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ 417 _vreg, _vmask, _ereg, _emask) \ 418 [_family##_##_id] = { \ 419 .name = (_match), \ 420 .supply_name = (_supply), \ 421 .of_match = of_match_ptr(_match), \ 422 .regulators_node = of_match_ptr("regulators"), \ 423 .type = REGULATOR_VOLTAGE, \ 424 .id = _family##_##_id, \ 425 .n_voltages = (_n_voltages), \ 426 .owner = THIS_MODULE, \ 427 .vsel_reg = (_vreg), \ 428 .vsel_mask = (_vmask), \ 429 .enable_reg = (_ereg), \ 430 .enable_mask = (_emask), \ 431 .linear_ranges = (_ranges), \ 432 .n_linear_ranges = ARRAY_SIZE(_ranges), \ 433 .ops = &axp20x_ops_range, \ 434 } 435 436 static const int axp209_dcdc2_ldo3_slew_rates[] = { 437 1600, 438 800, 439 }; 440 441 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) 442 { 443 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 444 int id = rdev_get_id(rdev); 445 u8 reg, mask, enable, cfg = 0xff; 446 const int *slew_rates; 447 int rate_count = 0; 448 449 switch (axp20x->variant) { 450 case AXP209_ID: 451 if (id == AXP20X_DCDC2) { 452 slew_rates = axp209_dcdc2_ldo3_slew_rates; 453 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 454 reg = AXP20X_DCDC2_LDO3_V_RAMP; 455 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | 456 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; 457 enable = (ramp > 0) ? 458 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0; 459 break; 460 } 461 462 if (id == AXP20X_LDO3) { 463 slew_rates = axp209_dcdc2_ldo3_slew_rates; 464 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 465 reg = AXP20X_DCDC2_LDO3_V_RAMP; 466 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | 467 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; 468 enable = (ramp > 0) ? 469 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0; 470 break; 471 } 472 473 if (rate_count > 0) 474 break; 475 476 fallthrough; 477 default: 478 /* Not supported for this regulator */ 479 return -ENOTSUPP; 480 } 481 482 if (ramp == 0) { 483 cfg = enable; 484 } else { 485 int i; 486 487 for (i = 0; i < rate_count; i++) { 488 if (ramp > slew_rates[i]) 489 break; 490 491 if (id == AXP20X_DCDC2) 492 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i); 493 else 494 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i); 495 } 496 497 if (cfg == 0xff) { 498 dev_err(axp20x->dev, "unsupported ramp value %d", ramp); 499 return -EINVAL; 500 } 501 502 cfg |= enable; 503 } 504 505 return regmap_update_bits(axp20x->regmap, reg, mask, cfg); 506 } 507 508 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) 509 { 510 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 511 int id = rdev_get_id(rdev); 512 513 switch (axp20x->variant) { 514 case AXP209_ID: 515 if ((id == AXP20X_LDO3) && 516 rdev->constraints && rdev->constraints->soft_start) { 517 int v_out; 518 int ret; 519 520 /* 521 * On some boards, the LDO3 can be overloaded when 522 * turning on, causing the entire PMIC to shutdown 523 * without warning. Turning it on at the minimal voltage 524 * and then setting the voltage to the requested value 525 * works reliably. 526 */ 527 if (regulator_is_enabled_regmap(rdev)) 528 break; 529 530 v_out = regulator_get_voltage_sel_regmap(rdev); 531 if (v_out < 0) 532 return v_out; 533 534 if (v_out == 0) 535 break; 536 537 ret = regulator_set_voltage_sel_regmap(rdev, 0x00); 538 /* 539 * A small pause is needed between 540 * setting the voltage and enabling the LDO to give the 541 * internal state machine time to process the request. 542 */ 543 usleep_range(1000, 5000); 544 ret |= regulator_enable_regmap(rdev); 545 ret |= regulator_set_voltage_sel_regmap(rdev, v_out); 546 547 return ret; 548 } 549 break; 550 default: 551 /* No quirks */ 552 break; 553 } 554 555 return regulator_enable_regmap(rdev); 556 }; 557 558 static const struct regulator_ops axp20x_ops_fixed = { 559 .list_voltage = regulator_list_voltage_linear, 560 }; 561 562 static const struct regulator_ops axp20x_ops_range = { 563 .set_voltage_sel = regulator_set_voltage_sel_regmap, 564 .get_voltage_sel = regulator_get_voltage_sel_regmap, 565 .list_voltage = regulator_list_voltage_linear_range, 566 .enable = regulator_enable_regmap, 567 .disable = regulator_disable_regmap, 568 .is_enabled = regulator_is_enabled_regmap, 569 }; 570 571 static const struct regulator_ops axp20x_ops = { 572 .set_voltage_sel = regulator_set_voltage_sel_regmap, 573 .get_voltage_sel = regulator_get_voltage_sel_regmap, 574 .list_voltage = regulator_list_voltage_linear, 575 .enable = axp20x_regulator_enable_regmap, 576 .disable = regulator_disable_regmap, 577 .is_enabled = regulator_is_enabled_regmap, 578 .set_ramp_delay = axp20x_set_ramp_delay, 579 }; 580 581 static const struct regulator_ops axp20x_ops_sw = { 582 .enable = regulator_enable_regmap, 583 .disable = regulator_disable_regmap, 584 .is_enabled = regulator_is_enabled_regmap, 585 }; 586 587 static const struct linear_range axp20x_ldo4_ranges[] = { 588 REGULATOR_LINEAR_RANGE(1250000, 589 AXP20X_LDO4_V_OUT_1250mV_START, 590 AXP20X_LDO4_V_OUT_1250mV_END, 591 0), 592 REGULATOR_LINEAR_RANGE(1300000, 593 AXP20X_LDO4_V_OUT_1300mV_START, 594 AXP20X_LDO4_V_OUT_1300mV_END, 595 100000), 596 REGULATOR_LINEAR_RANGE(2500000, 597 AXP20X_LDO4_V_OUT_2500mV_START, 598 AXP20X_LDO4_V_OUT_2500mV_END, 599 0), 600 REGULATOR_LINEAR_RANGE(2700000, 601 AXP20X_LDO4_V_OUT_2700mV_START, 602 AXP20X_LDO4_V_OUT_2700mV_END, 603 100000), 604 REGULATOR_LINEAR_RANGE(3000000, 605 AXP20X_LDO4_V_OUT_3000mV_START, 606 AXP20X_LDO4_V_OUT_3000mV_END, 607 100000), 608 }; 609 610 static const struct regulator_desc axp20x_regulators[] = { 611 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, 612 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK, 613 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK), 614 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, 615 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK, 616 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK), 617 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), 618 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, 619 AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK, 620 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK), 621 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, 622 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK, 623 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK), 624 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", 625 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES, 626 AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK, 627 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK), 628 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, 629 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK, 630 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 631 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), 632 }; 633 634 static const struct regulator_desc axp22x_regulators[] = { 635 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 636 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 637 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 638 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 639 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 640 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 641 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 642 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 643 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 644 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, 645 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 646 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 647 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 648 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 649 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 650 /* secondary switchable output of DCDC1 */ 651 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, 652 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 653 /* LDO regulator internally chained to DCDC5 */ 654 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 655 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 656 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 657 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 658 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 659 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 660 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 661 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 662 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 663 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 664 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 665 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK), 666 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 667 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 668 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 669 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 670 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 671 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 672 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 673 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 674 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 675 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 676 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 677 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 678 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 679 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 680 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 681 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 682 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 683 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 684 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 685 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 686 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 687 /* Note the datasheet only guarantees reliable operation up to 688 * 3.3V, this needs to be enforced via dts provided constraints */ 689 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 690 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 691 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 692 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 693 /* Note the datasheet only guarantees reliable operation up to 694 * 3.3V, this needs to be enforced via dts provided constraints */ 695 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 696 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 697 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 698 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 699 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), 700 }; 701 702 static const struct regulator_desc axp22x_drivevbus_regulator = { 703 .name = "drivevbus", 704 .supply_name = "drivevbus", 705 .of_match = of_match_ptr("drivevbus"), 706 .regulators_node = of_match_ptr("regulators"), 707 .type = REGULATOR_VOLTAGE, 708 .owner = THIS_MODULE, 709 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT, 710 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK, 711 .ops = &axp20x_ops_sw, 712 }; 713 714 static const struct linear_range axp313a_dcdc1_ranges[] = { 715 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 716 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 717 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000), 718 }; 719 720 static const struct linear_range axp313a_dcdc2_ranges[] = { 721 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 722 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 723 }; 724 725 /* 726 * This is deviating from the datasheet. The values here are taken from the 727 * BSP driver and have been confirmed by measurements. 728 */ 729 static const struct linear_range axp313a_dcdc3_ranges[] = { 730 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 731 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000), 732 }; 733 734 static const struct regulator_desc axp313a_regulators[] = { 735 AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1", 736 axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES, 737 AXP313A_DCDC1_CONRTOL, AXP313A_DCDC_V_OUT_MASK, 738 AXP313A_OUTPUT_CONTROL, BIT(0)), 739 AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2", 740 axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES, 741 AXP313A_DCDC2_CONRTOL, AXP313A_DCDC_V_OUT_MASK, 742 AXP313A_OUTPUT_CONTROL, BIT(1)), 743 AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3", 744 axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES, 745 AXP313A_DCDC3_CONRTOL, AXP313A_DCDC_V_OUT_MASK, 746 AXP313A_OUTPUT_CONTROL, BIT(2)), 747 AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100, 748 AXP313A_ALDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, 749 AXP313A_OUTPUT_CONTROL, BIT(3)), 750 AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100, 751 AXP313A_DLDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK, 752 AXP313A_OUTPUT_CONTROL, BIT(4)), 753 AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800), 754 }; 755 756 /* DCDC ranges shared with AXP813 */ 757 static const struct linear_range axp803_dcdc234_ranges[] = { 758 REGULATOR_LINEAR_RANGE(500000, 759 AXP803_DCDC234_500mV_START, 760 AXP803_DCDC234_500mV_END, 761 10000), 762 REGULATOR_LINEAR_RANGE(1220000, 763 AXP803_DCDC234_1220mV_START, 764 AXP803_DCDC234_1220mV_END, 765 20000), 766 }; 767 768 static const struct linear_range axp803_dcdc5_ranges[] = { 769 REGULATOR_LINEAR_RANGE(800000, 770 AXP803_DCDC5_800mV_START, 771 AXP803_DCDC5_800mV_END, 772 10000), 773 REGULATOR_LINEAR_RANGE(1140000, 774 AXP803_DCDC5_1140mV_START, 775 AXP803_DCDC5_1140mV_END, 776 20000), 777 }; 778 779 static const struct linear_range axp803_dcdc6_ranges[] = { 780 REGULATOR_LINEAR_RANGE(600000, 781 AXP803_DCDC6_600mV_START, 782 AXP803_DCDC6_600mV_END, 783 10000), 784 REGULATOR_LINEAR_RANGE(1120000, 785 AXP803_DCDC6_1120mV_START, 786 AXP803_DCDC6_1120mV_END, 787 20000), 788 }; 789 790 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */ 791 static const struct linear_range axp803_dldo2_ranges[] = { 792 REGULATOR_LINEAR_RANGE(700000, 793 AXP803_DLDO2_700mV_START, 794 AXP803_DLDO2_700mV_END, 795 100000), 796 REGULATOR_LINEAR_RANGE(3400000, 797 AXP803_DLDO2_3400mV_START, 798 AXP803_DLDO2_3400mV_END, 799 200000), 800 }; 801 802 static const struct regulator_desc axp803_regulators[] = { 803 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 804 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 805 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 806 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", 807 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 808 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 809 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 810 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", 811 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 812 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 813 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 814 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", 815 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 816 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 817 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 818 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", 819 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 820 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 821 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 822 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", 823 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 824 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 825 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 826 /* secondary switchable output of DCDC1 */ 827 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, 828 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 829 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 830 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 831 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 832 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 833 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 834 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 835 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 836 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 837 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 838 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 839 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 840 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 841 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", 842 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 843 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 844 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 845 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 846 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 847 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 848 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 849 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 850 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 851 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 852 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 853 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 854 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 855 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 856 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 857 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 858 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 859 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 860 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 861 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 862 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 863 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 864 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 865 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 866 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 867 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 868 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 869 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 870 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 871 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 872 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 873 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 874 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000), 875 }; 876 877 static const struct linear_range axp806_dcdca_ranges[] = { 878 REGULATOR_LINEAR_RANGE(600000, 879 AXP806_DCDCA_600mV_START, 880 AXP806_DCDCA_600mV_END, 881 10000), 882 REGULATOR_LINEAR_RANGE(1120000, 883 AXP806_DCDCA_1120mV_START, 884 AXP806_DCDCA_1120mV_END, 885 20000), 886 }; 887 888 static const struct linear_range axp806_dcdcd_ranges[] = { 889 REGULATOR_LINEAR_RANGE(600000, 890 AXP806_DCDCD_600mV_START, 891 AXP806_DCDCD_600mV_END, 892 20000), 893 REGULATOR_LINEAR_RANGE(1600000, 894 AXP806_DCDCD_1600mV_START, 895 AXP806_DCDCD_1600mV_END, 896 100000), 897 }; 898 899 static const struct regulator_desc axp806_regulators[] = { 900 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", 901 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 902 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, 903 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), 904 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, 905 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK, 906 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), 907 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", 908 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 909 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK, 910 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK), 911 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", 912 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES, 913 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK, 914 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK), 915 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100, 916 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK, 917 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK), 918 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 919 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK, 920 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK), 921 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100, 922 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK, 923 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK), 924 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 925 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK, 926 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK), 927 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100, 928 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, 929 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), 930 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, 931 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK, 932 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), 933 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, 934 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, 935 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK), 936 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100, 937 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK, 938 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK), 939 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 940 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK, 941 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK), 942 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", 943 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 944 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK, 945 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK), 946 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100, 947 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK, 948 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK), 949 AXP_DESC_SW(AXP806, SW, "sw", "swin", 950 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK), 951 }; 952 953 static const struct linear_range axp809_dcdc4_ranges[] = { 954 REGULATOR_LINEAR_RANGE(600000, 955 AXP809_DCDC4_600mV_START, 956 AXP809_DCDC4_600mV_END, 957 20000), 958 REGULATOR_LINEAR_RANGE(1800000, 959 AXP809_DCDC4_1800mV_START, 960 AXP809_DCDC4_1800mV_END, 961 100000), 962 }; 963 964 static const struct regulator_desc axp809_regulators[] = { 965 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 966 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 967 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 968 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 969 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 970 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 971 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 972 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 973 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 974 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", 975 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES, 976 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 977 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 978 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 979 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 980 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 981 /* secondary switchable output of DCDC1 */ 982 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, 983 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 984 /* LDO regulator internally chained to DCDC5 */ 985 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 986 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 987 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 988 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 989 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 990 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 991 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 992 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 993 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 994 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 995 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 996 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK), 997 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", 998 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 999 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 1000 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 1001 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 1002 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 1003 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 1004 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 1005 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 1006 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 1007 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 1008 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 1009 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 1010 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 1011 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 1012 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 1013 /* 1014 * Note the datasheet only guarantees reliable operation up to 1015 * 3.3V, this needs to be enforced via dts provided constraints 1016 */ 1017 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 1018 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 1019 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 1020 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1021 /* 1022 * Note the datasheet only guarantees reliable operation up to 1023 * 3.3V, this needs to be enforced via dts provided constraints 1024 */ 1025 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 1026 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 1027 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 1028 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1029 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), 1030 AXP_DESC_SW(AXP809, SW, "sw", "swin", 1031 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK), 1032 }; 1033 1034 static const struct regulator_desc axp813_regulators[] = { 1035 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 1036 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 1037 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 1038 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2", 1039 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 1040 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 1041 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 1042 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3", 1043 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 1044 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 1045 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 1046 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4", 1047 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 1048 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 1049 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 1050 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5", 1051 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 1052 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 1053 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 1054 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6", 1055 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 1056 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 1057 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 1058 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7", 1059 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 1060 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK, 1061 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK), 1062 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 1063 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 1064 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 1065 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 1066 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 1067 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 1068 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 1069 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 1070 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 1071 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 1072 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 1073 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 1074 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", 1075 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 1076 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 1077 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 1078 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 1079 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 1080 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 1081 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 1082 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 1083 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 1084 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 1085 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 1086 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 1087 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 1088 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 1089 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 1090 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 1091 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 1092 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 1093 /* to do / check ... */ 1094 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 1095 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 1096 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 1097 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 1098 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 1099 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 1100 /* 1101 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2 1102 * 1103 * This means FLDO3 effectively switches supplies at runtime, 1104 * something the regulator subsystem does not support. 1105 */ 1106 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800), 1107 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 1108 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 1109 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 1110 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1111 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 1112 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 1113 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 1114 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1115 AXP_DESC_SW(AXP813, SW, "sw", "swin", 1116 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 1117 }; 1118 1119 static const struct linear_range axp15060_dcdc234_ranges[] = { 1120 REGULATOR_LINEAR_RANGE(500000, 1121 AXP15060_DCDC234_500mV_START, 1122 AXP15060_DCDC234_500mV_END, 1123 10000), 1124 REGULATOR_LINEAR_RANGE(1220000, 1125 AXP15060_DCDC234_1220mV_START, 1126 AXP15060_DCDC234_1220mV_END, 1127 20000), 1128 }; 1129 1130 static const struct linear_range axp15060_dcdc5_ranges[] = { 1131 REGULATOR_LINEAR_RANGE(800000, 1132 AXP15060_DCDC5_800mV_START, 1133 AXP15060_DCDC5_800mV_END, 1134 10000), 1135 REGULATOR_LINEAR_RANGE(1140000, 1136 AXP15060_DCDC5_1140mV_START, 1137 AXP15060_DCDC5_1140mV_END, 1138 20000), 1139 }; 1140 1141 static const struct regulator_desc axp15060_regulators[] = { 1142 AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100, 1143 AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK, 1144 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK), 1145 AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2", 1146 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, 1147 AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK, 1148 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK), 1149 AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3", 1150 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, 1151 AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK, 1152 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK), 1153 AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4", 1154 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, 1155 AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK, 1156 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK), 1157 AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5", 1158 axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES, 1159 AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK, 1160 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK), 1161 AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100, 1162 AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK, 1163 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK), 1164 AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 1165 AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK, 1166 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK), 1167 AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 1168 AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK, 1169 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK), 1170 AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 1171 AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK, 1172 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK), 1173 AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100, 1174 AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK, 1175 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK), 1176 AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100, 1177 AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK, 1178 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK), 1179 AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100, 1180 AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK, 1181 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK), 1182 AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100, 1183 AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK, 1184 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK), 1185 AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100, 1186 AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK, 1187 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK), 1188 AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100, 1189 AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK, 1190 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK), 1191 AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100, 1192 AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK, 1193 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK), 1194 AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 1195 AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK, 1196 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK), 1197 AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100, 1198 AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK, 1199 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK), 1200 AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100, 1201 AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK, 1202 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK), 1203 AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100, 1204 AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK, 1205 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK), 1206 /* Supply comes from DCDC5 */ 1207 AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50, 1208 AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK, 1209 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK), 1210 /* Supply comes from DCDC1 */ 1211 AXP_DESC_SW(AXP15060, SW, "sw", NULL, 1212 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK), 1213 /* Supply comes from ALDO1 */ 1214 AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800), 1215 }; 1216 1217 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) 1218 { 1219 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1220 unsigned int reg = AXP20X_DCDC_FREQ; 1221 u32 min, max, def, step; 1222 1223 switch (axp20x->variant) { 1224 case AXP202_ID: 1225 case AXP209_ID: 1226 min = 750; 1227 max = 1875; 1228 def = 1500; 1229 step = 75; 1230 break; 1231 case AXP803_ID: 1232 case AXP813_ID: 1233 /* 1234 * AXP803/AXP813 DCDC work frequency setting has the same 1235 * range and step as AXP22X, but at a different register. 1236 * (See include/linux/mfd/axp20x.h) 1237 */ 1238 reg = AXP803_DCDC_FREQ_CTRL; 1239 fallthrough; /* to the check below */ 1240 case AXP806_ID: 1241 /* 1242 * AXP806 also have DCDC work frequency setting register at a 1243 * different position. 1244 */ 1245 if (axp20x->variant == AXP806_ID) 1246 reg = AXP806_DCDC_FREQ_CTRL; 1247 fallthrough; 1248 case AXP221_ID: 1249 case AXP223_ID: 1250 case AXP809_ID: 1251 min = 1800; 1252 max = 4050; 1253 def = 3000; 1254 step = 150; 1255 break; 1256 case AXP313A_ID: 1257 case AXP15060_ID: 1258 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */ 1259 if (dcdcfreq != 0) { 1260 dev_err(&pdev->dev, 1261 "DCDC frequency on this PMIC is fixed to 3 MHz.\n"); 1262 return -EINVAL; 1263 } 1264 1265 return 0; 1266 default: 1267 dev_err(&pdev->dev, 1268 "Setting DCDC frequency for unsupported AXP variant\n"); 1269 return -EINVAL; 1270 } 1271 1272 if (dcdcfreq == 0) 1273 dcdcfreq = def; 1274 1275 if (dcdcfreq < min) { 1276 dcdcfreq = min; 1277 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", 1278 min); 1279 } 1280 1281 if (dcdcfreq > max) { 1282 dcdcfreq = max; 1283 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", 1284 max); 1285 } 1286 1287 dcdcfreq = (dcdcfreq - min) / step; 1288 1289 return regmap_update_bits(axp20x->regmap, reg, 1290 AXP20X_FREQ_DCDC_MASK, dcdcfreq); 1291 } 1292 1293 static int axp20x_regulator_parse_dt(struct platform_device *pdev) 1294 { 1295 struct device_node *np, *regulators; 1296 int ret = 0; 1297 u32 dcdcfreq = 0; 1298 1299 np = of_node_get(pdev->dev.parent->of_node); 1300 if (!np) 1301 return 0; 1302 1303 regulators = of_get_child_by_name(np, "regulators"); 1304 if (!regulators) { 1305 dev_warn(&pdev->dev, "regulators node not found\n"); 1306 } else { 1307 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); 1308 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); 1309 if (ret < 0) { 1310 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); 1311 } 1312 of_node_put(regulators); 1313 } 1314 1315 of_node_put(np); 1316 return ret; 1317 } 1318 1319 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) 1320 { 1321 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 1322 unsigned int reg = AXP20X_DCDC_MODE; 1323 unsigned int mask; 1324 1325 switch (axp20x->variant) { 1326 case AXP202_ID: 1327 case AXP209_ID: 1328 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) 1329 return -EINVAL; 1330 1331 mask = AXP20X_WORKMODE_DCDC2_MASK; 1332 if (id == AXP20X_DCDC3) 1333 mask = AXP20X_WORKMODE_DCDC3_MASK; 1334 1335 workmode <<= ffs(mask) - 1; 1336 break; 1337 1338 case AXP806_ID: 1339 /* 1340 * AXP806 DCDC regulator IDs have the same range as AXP22X. 1341 * (See include/linux/mfd/axp20x.h) 1342 */ 1343 reg = AXP806_DCDC_MODE_CTRL2; 1344 fallthrough; /* to the check below */ 1345 case AXP221_ID: 1346 case AXP223_ID: 1347 case AXP809_ID: 1348 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) 1349 return -EINVAL; 1350 1351 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); 1352 workmode <<= id - AXP22X_DCDC1; 1353 break; 1354 1355 case AXP803_ID: 1356 if (id < AXP803_DCDC1 || id > AXP803_DCDC6) 1357 return -EINVAL; 1358 1359 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); 1360 workmode <<= id - AXP803_DCDC1; 1361 break; 1362 1363 case AXP813_ID: 1364 if (id < AXP813_DCDC1 || id > AXP813_DCDC7) 1365 return -EINVAL; 1366 1367 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1); 1368 workmode <<= id - AXP813_DCDC1; 1369 break; 1370 1371 case AXP15060_ID: 1372 reg = AXP15060_DCDC_MODE_CTRL2; 1373 if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6) 1374 return -EINVAL; 1375 1376 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1); 1377 workmode <<= id - AXP15060_DCDC1; 1378 break; 1379 1380 default: 1381 /* should not happen */ 1382 WARN_ON(1); 1383 return -EINVAL; 1384 } 1385 1386 return regmap_update_bits(rdev->regmap, reg, mask, workmode); 1387 } 1388 1389 /* 1390 * This function checks whether a regulator is part of a poly-phase 1391 * output setup based on the registers settings. Returns true if it is. 1392 */ 1393 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id) 1394 { 1395 u32 reg = 0; 1396 1397 /* 1398 * Currently in our supported AXP variants, only AXP803, AXP806, 1399 * AXP813 and AXP15060 have polyphase regulators. 1400 */ 1401 switch (axp20x->variant) { 1402 case AXP803_ID: 1403 case AXP813_ID: 1404 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); 1405 1406 switch (id) { 1407 case AXP803_DCDC3: 1408 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); 1409 case AXP803_DCDC6: 1410 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); 1411 } 1412 break; 1413 1414 case AXP806_ID: 1415 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); 1416 1417 switch (id) { 1418 case AXP806_DCDCB: 1419 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1420 AXP806_DCDCAB_POLYPHASE_DUAL) || 1421 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1422 AXP806_DCDCABC_POLYPHASE_TRI)); 1423 case AXP806_DCDCC: 1424 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1425 AXP806_DCDCABC_POLYPHASE_TRI); 1426 case AXP806_DCDCE: 1427 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); 1428 } 1429 break; 1430 1431 case AXP15060_ID: 1432 regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, ®); 1433 1434 switch (id) { 1435 case AXP15060_DCDC3: 1436 return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK); 1437 case AXP15060_DCDC6: 1438 return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK); 1439 } 1440 break; 1441 1442 default: 1443 return false; 1444 } 1445 1446 return false; 1447 } 1448 1449 static int axp20x_regulator_probe(struct platform_device *pdev) 1450 { 1451 struct regulator_dev *rdev; 1452 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1453 const struct regulator_desc *regulators; 1454 struct regulator_config config = { 1455 .dev = pdev->dev.parent, 1456 .regmap = axp20x->regmap, 1457 .driver_data = axp20x, 1458 }; 1459 int ret, i, nregulators; 1460 u32 workmode; 1461 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name; 1462 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name; 1463 const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name; 1464 bool drivevbus = false; 1465 1466 switch (axp20x->variant) { 1467 case AXP202_ID: 1468 case AXP209_ID: 1469 regulators = axp20x_regulators; 1470 nregulators = AXP20X_REG_ID_MAX; 1471 break; 1472 case AXP221_ID: 1473 case AXP223_ID: 1474 regulators = axp22x_regulators; 1475 nregulators = AXP22X_REG_ID_MAX; 1476 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1477 "x-powers,drive-vbus-en"); 1478 break; 1479 case AXP313A_ID: 1480 regulators = axp313a_regulators; 1481 nregulators = AXP313A_REG_ID_MAX; 1482 break; 1483 case AXP803_ID: 1484 regulators = axp803_regulators; 1485 nregulators = AXP803_REG_ID_MAX; 1486 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1487 "x-powers,drive-vbus-en"); 1488 break; 1489 case AXP806_ID: 1490 regulators = axp806_regulators; 1491 nregulators = AXP806_REG_ID_MAX; 1492 break; 1493 case AXP809_ID: 1494 regulators = axp809_regulators; 1495 nregulators = AXP809_REG_ID_MAX; 1496 break; 1497 case AXP813_ID: 1498 regulators = axp813_regulators; 1499 nregulators = AXP813_REG_ID_MAX; 1500 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1501 "x-powers,drive-vbus-en"); 1502 break; 1503 case AXP15060_ID: 1504 regulators = axp15060_regulators; 1505 nregulators = AXP15060_REG_ID_MAX; 1506 break; 1507 default: 1508 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n", 1509 axp20x->variant); 1510 return -EINVAL; 1511 } 1512 1513 /* This only sets the dcdc freq. Ignore any errors */ 1514 axp20x_regulator_parse_dt(pdev); 1515 1516 for (i = 0; i < nregulators; i++) { 1517 const struct regulator_desc *desc = ®ulators[i]; 1518 struct regulator_desc *new_desc; 1519 1520 /* 1521 * If this regulator is a slave in a poly-phase setup, 1522 * skip it, as its controls are bound to the master 1523 * regulator and won't work. 1524 */ 1525 if (axp20x_is_polyphase_slave(axp20x, i)) 1526 continue; 1527 1528 /* Support for AXP813's FLDO3 is not implemented */ 1529 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3) 1530 continue; 1531 1532 /* 1533 * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are 1534 * connected internally, so we have to handle their supply 1535 * names separately. 1536 * 1537 * We always register the regulators in proper sequence, 1538 * so the supply names are correctly read. See the last 1539 * part of this loop to see where we save the DT defined 1540 * name. 1541 */ 1542 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || 1543 (regulators == axp803_regulators && i == AXP803_DC1SW) || 1544 (regulators == axp809_regulators && i == AXP809_DC1SW) || 1545 (regulators == axp15060_regulators && i == AXP15060_SW)) { 1546 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1547 GFP_KERNEL); 1548 if (!new_desc) 1549 return -ENOMEM; 1550 1551 *new_desc = regulators[i]; 1552 new_desc->supply_name = dcdc1_name; 1553 desc = new_desc; 1554 } 1555 1556 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) || 1557 (regulators == axp809_regulators && i == AXP809_DC5LDO) || 1558 (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) { 1559 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1560 GFP_KERNEL); 1561 if (!new_desc) 1562 return -ENOMEM; 1563 1564 *new_desc = regulators[i]; 1565 new_desc->supply_name = dcdc5_name; 1566 desc = new_desc; 1567 } 1568 1569 1570 if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) { 1571 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1572 GFP_KERNEL); 1573 if (!new_desc) 1574 return -ENOMEM; 1575 1576 *new_desc = regulators[i]; 1577 new_desc->supply_name = aldo1_name; 1578 desc = new_desc; 1579 } 1580 1581 rdev = devm_regulator_register(&pdev->dev, desc, &config); 1582 if (IS_ERR(rdev)) { 1583 dev_err(&pdev->dev, "Failed to register %s\n", 1584 regulators[i].name); 1585 1586 return PTR_ERR(rdev); 1587 } 1588 1589 ret = of_property_read_u32(rdev->dev.of_node, 1590 "x-powers,dcdc-workmode", 1591 &workmode); 1592 if (!ret) { 1593 if (axp20x_set_dcdc_workmode(rdev, i, workmode)) 1594 dev_err(&pdev->dev, "Failed to set workmode on %s\n", 1595 rdev->desc->name); 1596 } 1597 1598 /* 1599 * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later. 1600 */ 1601 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) || 1602 (regulators == axp809_regulators && i == AXP809_DCDC1) || 1603 (regulators == axp15060_regulators && i == AXP15060_DCDC1)) 1604 of_property_read_string(rdev->dev.of_node, 1605 "regulator-name", 1606 &dcdc1_name); 1607 1608 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) || 1609 (regulators == axp809_regulators && i == AXP809_DCDC5) || 1610 (regulators == axp15060_regulators && i == AXP15060_DCDC5)) 1611 of_property_read_string(rdev->dev.of_node, 1612 "regulator-name", 1613 &dcdc5_name); 1614 1615 if (regulators == axp15060_regulators && i == AXP15060_ALDO1) 1616 of_property_read_string(rdev->dev.of_node, 1617 "regulator-name", 1618 &aldo1_name); 1619 } 1620 1621 if (drivevbus) { 1622 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */ 1623 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP, 1624 AXP22X_MISC_N_VBUSEN_FUNC, 0); 1625 rdev = devm_regulator_register(&pdev->dev, 1626 &axp22x_drivevbus_regulator, 1627 &config); 1628 if (IS_ERR(rdev)) { 1629 dev_err(&pdev->dev, "Failed to register drivevbus\n"); 1630 return PTR_ERR(rdev); 1631 } 1632 } 1633 1634 return 0; 1635 } 1636 1637 static struct platform_driver axp20x_regulator_driver = { 1638 .probe = axp20x_regulator_probe, 1639 .driver = { 1640 .name = "axp20x-regulator", 1641 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1642 }, 1643 }; 1644 1645 module_platform_driver(axp20x_regulator_driver); 1646 1647 MODULE_LICENSE("GPL v2"); 1648 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 1649 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); 1650 MODULE_ALIAS("platform:axp20x-regulator"); 1651