1 /* 2 * AXP20x regulators driver. 3 * 4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General 7 * Public License. See the file "COPYING" in the main directory of this 8 * archive for more details. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/mfd/axp20x.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/regulator/machine.h> 28 #include <linux/regulator/of_regulator.h> 29 30 #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0) 31 #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0) 32 33 #define AXP20X_IO_ENABLED 0x03 34 #define AXP20X_IO_DISABLED 0x07 35 36 #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2) 37 #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1) 38 39 #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0) 40 41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2) 42 43 #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0) 44 #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0) 45 #define AXP20X_LDO24_V_OUT_MASK GENMASK(7, 4) 46 #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0) 47 #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4) 48 49 #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0) 50 #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1) 51 #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2) 52 #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3) 53 #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4) 54 #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6) 55 56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0) 57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \ 58 ((x) << 0) 59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1) 60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \ 61 ((x) << 1) 62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2) 63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2) 64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3) 65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3) 66 67 #define AXP20X_LDO4_V_OUT_1250mV_START 0x0 68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0 69 #define AXP20X_LDO4_V_OUT_1250mV_END \ 70 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS) 71 #define AXP20X_LDO4_V_OUT_1300mV_START 0x1 72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7 73 #define AXP20X_LDO4_V_OUT_1300mV_END \ 74 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS) 75 #define AXP20X_LDO4_V_OUT_2500mV_START 0x9 76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0 77 #define AXP20X_LDO4_V_OUT_2500mV_END \ 78 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS) 79 #define AXP20X_LDO4_V_OUT_2700mV_START 0xa 80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1 81 #define AXP20X_LDO4_V_OUT_2700mV_END \ 82 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS) 83 #define AXP20X_LDO4_V_OUT_3000mV_START 0xc 84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3 85 #define AXP20X_LDO4_V_OUT_3000mV_END \ 86 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS) 87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16 88 89 #define AXP22X_IO_ENABLED 0x03 90 #define AXP22X_IO_DISABLED 0x04 91 92 #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x) 93 94 #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) 95 96 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0) 97 #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0) 98 #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0) 99 #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0) 100 #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0) 101 #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0) 102 #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0) 103 #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0) 104 #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0) 105 #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0) 106 #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0) 107 #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0) 108 #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0) 109 #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0) 110 #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0) 111 #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0) 112 #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0) 113 #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0) 114 115 #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0) 116 #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1) 117 #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2) 118 #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3) 119 #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4) 120 #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5) 121 #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6) 122 #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7) 123 124 #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6) 125 #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7) 126 127 #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0) 128 #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1) 129 #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2) 130 #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3) 131 #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4) 132 #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5) 133 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6) 134 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7) 135 136 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) 137 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) 138 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) 139 #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3) 140 #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4) 141 #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5) 142 143 #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2) 144 #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3) 145 146 #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0) 147 #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0) 148 #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0) 149 #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0) 150 #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0) 151 #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0) 152 153 #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0) 154 #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0) 155 156 #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6) 157 #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5) 158 159 #define AXP803_DCDC234_500mV_START 0x00 160 #define AXP803_DCDC234_500mV_STEPS 70 161 #define AXP803_DCDC234_500mV_END \ 162 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS) 163 #define AXP803_DCDC234_1220mV_START 0x47 164 #define AXP803_DCDC234_1220mV_STEPS 4 165 #define AXP803_DCDC234_1220mV_END \ 166 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS) 167 #define AXP803_DCDC234_NUM_VOLTAGES 76 168 169 #define AXP803_DCDC5_800mV_START 0x00 170 #define AXP803_DCDC5_800mV_STEPS 32 171 #define AXP803_DCDC5_800mV_END \ 172 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS) 173 #define AXP803_DCDC5_1140mV_START 0x21 174 #define AXP803_DCDC5_1140mV_STEPS 35 175 #define AXP803_DCDC5_1140mV_END \ 176 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS) 177 #define AXP803_DCDC5_NUM_VOLTAGES 69 178 179 #define AXP803_DCDC6_600mV_START 0x00 180 #define AXP803_DCDC6_600mV_STEPS 50 181 #define AXP803_DCDC6_600mV_END \ 182 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS) 183 #define AXP803_DCDC6_1120mV_START 0x33 184 #define AXP803_DCDC6_1120mV_STEPS 20 185 #define AXP803_DCDC6_1120mV_END \ 186 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) 187 #define AXP803_DCDC6_NUM_VOLTAGES 72 188 189 #define AXP803_DLDO2_700mV_START 0x00 190 #define AXP803_DLDO2_700mV_STEPS 26 191 #define AXP803_DLDO2_700mV_END \ 192 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS) 193 #define AXP803_DLDO2_3400mV_START 0x1b 194 #define AXP803_DLDO2_3400mV_STEPS 4 195 #define AXP803_DLDO2_3400mV_END \ 196 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS) 197 #define AXP803_DLDO2_NUM_VOLTAGES 32 198 199 #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0) 200 #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0) 201 #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0) 202 #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0) 203 #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0) 204 #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0) 205 #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0) 206 #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0) 207 #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0) 208 #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0) 209 #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0) 210 #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0) 211 #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0) 212 #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0) 213 #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0) 214 215 #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0) 216 #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1) 217 #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2) 218 #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3) 219 #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4) 220 #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5) 221 #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6) 222 #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7) 223 #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0) 224 #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1) 225 #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2) 226 #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3) 227 #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4) 228 #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5) 229 #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6) 230 #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7) 231 232 #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40 233 #define AXP806_DCDCABC_POLYPHASE_TRI 0x80 234 #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6) 235 236 #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5) 237 238 #define AXP806_DCDCA_600mV_START 0x00 239 #define AXP806_DCDCA_600mV_STEPS 50 240 #define AXP806_DCDCA_600mV_END \ 241 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS) 242 #define AXP806_DCDCA_1120mV_START 0x33 243 #define AXP806_DCDCA_1120mV_STEPS 20 244 #define AXP806_DCDCA_1120mV_END \ 245 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS) 246 #define AXP806_DCDCA_NUM_VOLTAGES 72 247 248 #define AXP806_DCDCD_600mV_START 0x00 249 #define AXP806_DCDCD_600mV_STEPS 45 250 #define AXP806_DCDCD_600mV_END \ 251 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS) 252 #define AXP806_DCDCD_1600mV_START 0x2e 253 #define AXP806_DCDCD_1600mV_STEPS 17 254 #define AXP806_DCDCD_1600mV_END \ 255 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS) 256 #define AXP806_DCDCD_NUM_VOLTAGES 64 257 258 #define AXP809_DCDC4_600mV_START 0x00 259 #define AXP809_DCDC4_600mV_STEPS 47 260 #define AXP809_DCDC4_600mV_END \ 261 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS) 262 #define AXP809_DCDC4_1800mV_START 0x30 263 #define AXP809_DCDC4_1800mV_STEPS 8 264 #define AXP809_DCDC4_1800mV_END \ 265 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS) 266 #define AXP809_DCDC4_NUM_VOLTAGES 57 267 268 #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0) 269 270 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6) 271 272 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 273 _vmask, _ereg, _emask, _enable_val, _disable_val) \ 274 [_family##_##_id] = { \ 275 .name = (_match), \ 276 .supply_name = (_supply), \ 277 .of_match = of_match_ptr(_match), \ 278 .regulators_node = of_match_ptr("regulators"), \ 279 .type = REGULATOR_VOLTAGE, \ 280 .id = _family##_##_id, \ 281 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 282 .owner = THIS_MODULE, \ 283 .min_uV = (_min) * 1000, \ 284 .uV_step = (_step) * 1000, \ 285 .vsel_reg = (_vreg), \ 286 .vsel_mask = (_vmask), \ 287 .enable_reg = (_ereg), \ 288 .enable_mask = (_emask), \ 289 .enable_val = (_enable_val), \ 290 .disable_val = (_disable_val), \ 291 .ops = &axp20x_ops, \ 292 } 293 294 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 295 _vmask, _ereg, _emask) \ 296 [_family##_##_id] = { \ 297 .name = (_match), \ 298 .supply_name = (_supply), \ 299 .of_match = of_match_ptr(_match), \ 300 .regulators_node = of_match_ptr("regulators"), \ 301 .type = REGULATOR_VOLTAGE, \ 302 .id = _family##_##_id, \ 303 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 304 .owner = THIS_MODULE, \ 305 .min_uV = (_min) * 1000, \ 306 .uV_step = (_step) * 1000, \ 307 .vsel_reg = (_vreg), \ 308 .vsel_mask = (_vmask), \ 309 .enable_reg = (_ereg), \ 310 .enable_mask = (_emask), \ 311 .ops = &axp20x_ops, \ 312 } 313 314 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ 315 [_family##_##_id] = { \ 316 .name = (_match), \ 317 .supply_name = (_supply), \ 318 .of_match = of_match_ptr(_match), \ 319 .regulators_node = of_match_ptr("regulators"), \ 320 .type = REGULATOR_VOLTAGE, \ 321 .id = _family##_##_id, \ 322 .owner = THIS_MODULE, \ 323 .enable_reg = (_ereg), \ 324 .enable_mask = (_emask), \ 325 .ops = &axp20x_ops_sw, \ 326 } 327 328 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ 329 [_family##_##_id] = { \ 330 .name = (_match), \ 331 .supply_name = (_supply), \ 332 .of_match = of_match_ptr(_match), \ 333 .regulators_node = of_match_ptr("regulators"), \ 334 .type = REGULATOR_VOLTAGE, \ 335 .id = _family##_##_id, \ 336 .n_voltages = 1, \ 337 .owner = THIS_MODULE, \ 338 .min_uV = (_volt) * 1000, \ 339 .ops = &axp20x_ops_fixed \ 340 } 341 342 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ 343 _vreg, _vmask, _ereg, _emask) \ 344 [_family##_##_id] = { \ 345 .name = (_match), \ 346 .supply_name = (_supply), \ 347 .of_match = of_match_ptr(_match), \ 348 .regulators_node = of_match_ptr("regulators"), \ 349 .type = REGULATOR_VOLTAGE, \ 350 .id = _family##_##_id, \ 351 .n_voltages = (_n_voltages), \ 352 .owner = THIS_MODULE, \ 353 .vsel_reg = (_vreg), \ 354 .vsel_mask = (_vmask), \ 355 .enable_reg = (_ereg), \ 356 .enable_mask = (_emask), \ 357 .linear_ranges = (_ranges), \ 358 .n_linear_ranges = ARRAY_SIZE(_ranges), \ 359 .ops = &axp20x_ops_range, \ 360 } 361 362 static const int axp209_dcdc2_ldo3_slew_rates[] = { 363 1600, 364 800, 365 }; 366 367 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) 368 { 369 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 370 int id = rdev_get_id(rdev); 371 u8 reg, mask, enable, cfg = 0xff; 372 const int *slew_rates; 373 int rate_count = 0; 374 375 switch (axp20x->variant) { 376 case AXP209_ID: 377 if (id == AXP20X_DCDC2) { 378 slew_rates = axp209_dcdc2_ldo3_slew_rates; 379 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 380 reg = AXP20X_DCDC2_LDO3_V_RAMP; 381 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | 382 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; 383 enable = (ramp > 0) ? 384 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 385 !AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN; 386 break; 387 } 388 389 if (id == AXP20X_LDO3) { 390 slew_rates = axp209_dcdc2_ldo3_slew_rates; 391 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 392 reg = AXP20X_DCDC2_LDO3_V_RAMP; 393 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | 394 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; 395 enable = (ramp > 0) ? 396 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 397 !AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN; 398 break; 399 } 400 401 if (rate_count > 0) 402 break; 403 404 /* fall through */ 405 default: 406 /* Not supported for this regulator */ 407 return -ENOTSUPP; 408 } 409 410 if (ramp == 0) { 411 cfg = enable; 412 } else { 413 int i; 414 415 for (i = 0; i < rate_count; i++) { 416 if (ramp <= slew_rates[i]) 417 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i); 418 else 419 break; 420 } 421 422 if (cfg == 0xff) { 423 dev_err(axp20x->dev, "unsupported ramp value %d", ramp); 424 return -EINVAL; 425 } 426 427 cfg |= enable; 428 } 429 430 return regmap_update_bits(axp20x->regmap, reg, mask, cfg); 431 } 432 433 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) 434 { 435 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 436 int id = rdev_get_id(rdev); 437 438 switch (axp20x->variant) { 439 case AXP209_ID: 440 if ((id == AXP20X_LDO3) && 441 rdev->constraints && rdev->constraints->soft_start) { 442 int v_out; 443 int ret; 444 445 /* 446 * On some boards, the LDO3 can be overloaded when 447 * turning on, causing the entire PMIC to shutdown 448 * without warning. Turning it on at the minimal voltage 449 * and then setting the voltage to the requested value 450 * works reliably. 451 */ 452 if (regulator_is_enabled_regmap(rdev)) 453 break; 454 455 v_out = regulator_get_voltage_sel_regmap(rdev); 456 if (v_out < 0) 457 return v_out; 458 459 if (v_out == 0) 460 break; 461 462 ret = regulator_set_voltage_sel_regmap(rdev, 0x00); 463 /* 464 * A small pause is needed between 465 * setting the voltage and enabling the LDO to give the 466 * internal state machine time to process the request. 467 */ 468 usleep_range(1000, 5000); 469 ret |= regulator_enable_regmap(rdev); 470 ret |= regulator_set_voltage_sel_regmap(rdev, v_out); 471 472 return ret; 473 } 474 break; 475 default: 476 /* No quirks */ 477 break; 478 } 479 480 return regulator_enable_regmap(rdev); 481 }; 482 483 static const struct regulator_ops axp20x_ops_fixed = { 484 .list_voltage = regulator_list_voltage_linear, 485 }; 486 487 static const struct regulator_ops axp20x_ops_range = { 488 .set_voltage_sel = regulator_set_voltage_sel_regmap, 489 .get_voltage_sel = regulator_get_voltage_sel_regmap, 490 .list_voltage = regulator_list_voltage_linear_range, 491 .enable = regulator_enable_regmap, 492 .disable = regulator_disable_regmap, 493 .is_enabled = regulator_is_enabled_regmap, 494 }; 495 496 static const struct regulator_ops axp20x_ops = { 497 .set_voltage_sel = regulator_set_voltage_sel_regmap, 498 .get_voltage_sel = regulator_get_voltage_sel_regmap, 499 .list_voltage = regulator_list_voltage_linear, 500 .enable = axp20x_regulator_enable_regmap, 501 .disable = regulator_disable_regmap, 502 .is_enabled = regulator_is_enabled_regmap, 503 .set_ramp_delay = axp20x_set_ramp_delay, 504 }; 505 506 static const struct regulator_ops axp20x_ops_sw = { 507 .enable = regulator_enable_regmap, 508 .disable = regulator_disable_regmap, 509 .is_enabled = regulator_is_enabled_regmap, 510 }; 511 512 static const struct regulator_linear_range axp20x_ldo4_ranges[] = { 513 REGULATOR_LINEAR_RANGE(1250000, 514 AXP20X_LDO4_V_OUT_1250mV_START, 515 AXP20X_LDO4_V_OUT_1250mV_END, 516 0), 517 REGULATOR_LINEAR_RANGE(1300000, 518 AXP20X_LDO4_V_OUT_1300mV_START, 519 AXP20X_LDO4_V_OUT_1300mV_END, 520 100000), 521 REGULATOR_LINEAR_RANGE(2500000, 522 AXP20X_LDO4_V_OUT_2500mV_START, 523 AXP20X_LDO4_V_OUT_2500mV_END, 524 0), 525 REGULATOR_LINEAR_RANGE(2700000, 526 AXP20X_LDO4_V_OUT_2700mV_START, 527 AXP20X_LDO4_V_OUT_2700mV_END, 528 100000), 529 REGULATOR_LINEAR_RANGE(3000000, 530 AXP20X_LDO4_V_OUT_3000mV_START, 531 AXP20X_LDO4_V_OUT_3000mV_END, 532 100000), 533 }; 534 535 static const struct regulator_desc axp20x_regulators[] = { 536 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, 537 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK, 538 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK), 539 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, 540 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK, 541 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK), 542 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), 543 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, 544 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK, 545 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK), 546 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, 547 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK, 548 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK), 549 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", 550 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES, 551 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK, 552 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK), 553 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, 554 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK, 555 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 556 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), 557 }; 558 559 static const struct regulator_desc axp22x_regulators[] = { 560 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 561 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 562 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 563 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 564 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 565 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 566 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 567 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 568 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 569 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, 570 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 571 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 572 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 573 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 574 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 575 /* secondary switchable output of DCDC1 */ 576 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, 577 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 578 /* LDO regulator internally chained to DCDC5 */ 579 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 580 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 581 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 582 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 583 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 584 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 585 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 586 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 587 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 588 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 589 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 590 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK), 591 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 592 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 593 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 594 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 595 AXP22X_DLDO2_V_OUT, AXP22X_PWR_OUT_DLDO2_MASK, 596 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 597 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 598 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 599 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 600 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 601 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 602 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 603 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 604 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 605 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 606 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 607 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 608 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 609 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 610 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 611 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 612 /* Note the datasheet only guarantees reliable operation up to 613 * 3.3V, this needs to be enforced via dts provided constraints */ 614 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 615 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 616 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 617 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 618 /* Note the datasheet only guarantees reliable operation up to 619 * 3.3V, this needs to be enforced via dts provided constraints */ 620 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 621 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 622 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 623 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 624 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), 625 }; 626 627 static const struct regulator_desc axp22x_drivevbus_regulator = { 628 .name = "drivevbus", 629 .supply_name = "drivevbus", 630 .of_match = of_match_ptr("drivevbus"), 631 .regulators_node = of_match_ptr("regulators"), 632 .type = REGULATOR_VOLTAGE, 633 .owner = THIS_MODULE, 634 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT, 635 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK, 636 .ops = &axp20x_ops_sw, 637 }; 638 639 /* DCDC ranges shared with AXP813 */ 640 static const struct regulator_linear_range axp803_dcdc234_ranges[] = { 641 REGULATOR_LINEAR_RANGE(500000, 642 AXP803_DCDC234_500mV_START, 643 AXP803_DCDC234_500mV_END, 644 10000), 645 REGULATOR_LINEAR_RANGE(1220000, 646 AXP803_DCDC234_1220mV_START, 647 AXP803_DCDC234_1220mV_END, 648 20000), 649 }; 650 651 static const struct regulator_linear_range axp803_dcdc5_ranges[] = { 652 REGULATOR_LINEAR_RANGE(800000, 653 AXP803_DCDC5_800mV_START, 654 AXP803_DCDC5_800mV_END, 655 10000), 656 REGULATOR_LINEAR_RANGE(1140000, 657 AXP803_DCDC5_1140mV_START, 658 AXP803_DCDC5_1140mV_END, 659 20000), 660 }; 661 662 static const struct regulator_linear_range axp803_dcdc6_ranges[] = { 663 REGULATOR_LINEAR_RANGE(600000, 664 AXP803_DCDC6_600mV_START, 665 AXP803_DCDC6_600mV_END, 666 10000), 667 REGULATOR_LINEAR_RANGE(1120000, 668 AXP803_DCDC6_1120mV_START, 669 AXP803_DCDC6_1120mV_END, 670 20000), 671 }; 672 673 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */ 674 static const struct regulator_linear_range axp803_dldo2_ranges[] = { 675 REGULATOR_LINEAR_RANGE(700000, 676 AXP803_DLDO2_700mV_START, 677 AXP803_DLDO2_700mV_END, 678 100000), 679 REGULATOR_LINEAR_RANGE(3400000, 680 AXP803_DLDO2_3400mV_START, 681 AXP803_DLDO2_3400mV_END, 682 200000), 683 }; 684 685 static const struct regulator_desc axp803_regulators[] = { 686 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 687 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 688 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 689 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", 690 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 691 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 692 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 693 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", 694 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 695 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 696 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 697 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", 698 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 699 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 700 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 701 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", 702 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 703 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 704 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 705 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", 706 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 707 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 708 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 709 /* secondary switchable output of DCDC1 */ 710 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, 711 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 712 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 713 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 714 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 715 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 716 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 717 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 718 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 719 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 720 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 721 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 722 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 723 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 724 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", 725 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 726 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 727 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 728 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 729 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 730 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 731 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 732 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 733 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 734 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 735 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 736 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 737 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 738 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 739 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 740 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 741 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 742 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 743 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 744 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 745 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 746 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 747 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 748 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 749 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 750 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 751 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 752 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 753 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 754 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 755 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 756 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 757 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000), 758 }; 759 760 static const struct regulator_linear_range axp806_dcdca_ranges[] = { 761 REGULATOR_LINEAR_RANGE(600000, 762 AXP806_DCDCA_600mV_START, 763 AXP806_DCDCA_600mV_END, 764 10000), 765 REGULATOR_LINEAR_RANGE(1120000, 766 AXP806_DCDCA_1120mV_START, 767 AXP806_DCDCA_1120mV_END, 768 20000), 769 }; 770 771 static const struct regulator_linear_range axp806_dcdcd_ranges[] = { 772 REGULATOR_LINEAR_RANGE(600000, 773 AXP806_DCDCD_600mV_START, 774 AXP806_DCDCD_600mV_END, 775 20000), 776 REGULATOR_LINEAR_RANGE(1600000, 777 AXP806_DCDCD_1600mV_START, 778 AXP806_DCDCD_1600mV_END, 779 100000), 780 }; 781 782 static const struct regulator_desc axp806_regulators[] = { 783 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", 784 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 785 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, 786 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), 787 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, 788 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK, 789 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), 790 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", 791 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 792 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK, 793 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK), 794 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", 795 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES, 796 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK, 797 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK), 798 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100, 799 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK, 800 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK), 801 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 802 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK, 803 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK), 804 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100, 805 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK, 806 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK), 807 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 808 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK, 809 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK), 810 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100, 811 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, 812 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), 813 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, 814 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK, 815 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), 816 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, 817 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, 818 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK), 819 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100, 820 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK, 821 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK), 822 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 823 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK, 824 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK), 825 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", 826 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 827 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK, 828 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK), 829 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100, 830 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK, 831 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK), 832 AXP_DESC_SW(AXP806, SW, "sw", "swin", 833 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK), 834 }; 835 836 static const struct regulator_linear_range axp809_dcdc4_ranges[] = { 837 REGULATOR_LINEAR_RANGE(600000, 838 AXP809_DCDC4_600mV_START, 839 AXP809_DCDC4_600mV_END, 840 20000), 841 REGULATOR_LINEAR_RANGE(1800000, 842 AXP809_DCDC4_1800mV_START, 843 AXP809_DCDC4_1800mV_END, 844 100000), 845 }; 846 847 static const struct regulator_desc axp809_regulators[] = { 848 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 849 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 850 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 851 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 852 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 853 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 854 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 855 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 856 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 857 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", 858 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES, 859 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 860 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 861 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 862 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 863 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 864 /* secondary switchable output of DCDC1 */ 865 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, 866 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 867 /* LDO regulator internally chained to DCDC5 */ 868 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 869 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 870 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 871 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 872 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 873 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 874 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 875 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 876 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 877 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 878 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 879 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK), 880 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", 881 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 882 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 883 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 884 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 885 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 886 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 887 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 888 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 889 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 890 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 891 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 892 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 893 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 894 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 895 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 896 /* 897 * Note the datasheet only guarantees reliable operation up to 898 * 3.3V, this needs to be enforced via dts provided constraints 899 */ 900 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 901 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 902 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 903 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 904 /* 905 * Note the datasheet only guarantees reliable operation up to 906 * 3.3V, this needs to be enforced via dts provided constraints 907 */ 908 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 909 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 910 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 911 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 912 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), 913 AXP_DESC_SW(AXP809, SW, "sw", "swin", 914 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK), 915 }; 916 917 static const struct regulator_desc axp813_regulators[] = { 918 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 919 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 920 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 921 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2", 922 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 923 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 924 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 925 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3", 926 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 927 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 928 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 929 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4", 930 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 931 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 932 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 933 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5", 934 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 935 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 936 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 937 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6", 938 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 939 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 940 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 941 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7", 942 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 943 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK, 944 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK), 945 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 946 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 947 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 948 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 949 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 950 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 951 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 952 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 953 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 954 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 955 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 956 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 957 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", 958 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 959 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 960 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 961 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 962 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 963 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 964 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 965 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 966 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 967 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 968 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 969 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 970 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 971 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 972 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 973 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 974 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 975 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 976 /* to do / check ... */ 977 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 978 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 979 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 980 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 981 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 982 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 983 /* 984 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2 985 * 986 * This means FLDO3 effectively switches supplies at runtime, 987 * something the regulator subsystem does not support. 988 */ 989 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800), 990 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 991 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 992 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 993 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 994 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 995 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 996 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 997 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 998 AXP_DESC_SW(AXP813, SW, "sw", "swin", 999 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 1000 }; 1001 1002 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) 1003 { 1004 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1005 unsigned int reg = AXP20X_DCDC_FREQ; 1006 u32 min, max, def, step; 1007 1008 switch (axp20x->variant) { 1009 case AXP202_ID: 1010 case AXP209_ID: 1011 min = 750; 1012 max = 1875; 1013 def = 1500; 1014 step = 75; 1015 break; 1016 case AXP803_ID: 1017 case AXP813_ID: 1018 /* 1019 * AXP803/AXP813 DCDC work frequency setting has the same 1020 * range and step as AXP22X, but at a different register. 1021 * (See include/linux/mfd/axp20x.h) 1022 */ 1023 reg = AXP803_DCDC_FREQ_CTRL; 1024 /* Fall through - to the check below.*/ 1025 case AXP806_ID: 1026 /* 1027 * AXP806 also have DCDC work frequency setting register at a 1028 * different position. 1029 */ 1030 if (axp20x->variant == AXP806_ID) 1031 reg = AXP806_DCDC_FREQ_CTRL; 1032 /* Fall through */ 1033 case AXP221_ID: 1034 case AXP223_ID: 1035 case AXP809_ID: 1036 min = 1800; 1037 max = 4050; 1038 def = 3000; 1039 step = 150; 1040 break; 1041 default: 1042 dev_err(&pdev->dev, 1043 "Setting DCDC frequency for unsupported AXP variant\n"); 1044 return -EINVAL; 1045 } 1046 1047 if (dcdcfreq == 0) 1048 dcdcfreq = def; 1049 1050 if (dcdcfreq < min) { 1051 dcdcfreq = min; 1052 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", 1053 min); 1054 } 1055 1056 if (dcdcfreq > max) { 1057 dcdcfreq = max; 1058 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", 1059 max); 1060 } 1061 1062 dcdcfreq = (dcdcfreq - min) / step; 1063 1064 return regmap_update_bits(axp20x->regmap, reg, 1065 AXP20X_FREQ_DCDC_MASK, dcdcfreq); 1066 } 1067 1068 static int axp20x_regulator_parse_dt(struct platform_device *pdev) 1069 { 1070 struct device_node *np, *regulators; 1071 int ret; 1072 u32 dcdcfreq = 0; 1073 1074 np = of_node_get(pdev->dev.parent->of_node); 1075 if (!np) 1076 return 0; 1077 1078 regulators = of_get_child_by_name(np, "regulators"); 1079 if (!regulators) { 1080 dev_warn(&pdev->dev, "regulators node not found\n"); 1081 } else { 1082 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); 1083 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); 1084 if (ret < 0) { 1085 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); 1086 return ret; 1087 } 1088 1089 of_node_put(regulators); 1090 } 1091 1092 return 0; 1093 } 1094 1095 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) 1096 { 1097 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 1098 unsigned int reg = AXP20X_DCDC_MODE; 1099 unsigned int mask; 1100 1101 switch (axp20x->variant) { 1102 case AXP202_ID: 1103 case AXP209_ID: 1104 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) 1105 return -EINVAL; 1106 1107 mask = AXP20X_WORKMODE_DCDC2_MASK; 1108 if (id == AXP20X_DCDC3) 1109 mask = AXP20X_WORKMODE_DCDC3_MASK; 1110 1111 workmode <<= ffs(mask) - 1; 1112 break; 1113 1114 case AXP806_ID: 1115 /* 1116 * AXP806 DCDC regulator IDs have the same range as AXP22X. 1117 * (See include/linux/mfd/axp20x.h) 1118 */ 1119 reg = AXP806_DCDC_MODE_CTRL2; 1120 /* Fall through - to the check below. */ 1121 case AXP221_ID: 1122 case AXP223_ID: 1123 case AXP809_ID: 1124 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) 1125 return -EINVAL; 1126 1127 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); 1128 workmode <<= id - AXP22X_DCDC1; 1129 break; 1130 1131 case AXP803_ID: 1132 if (id < AXP803_DCDC1 || id > AXP803_DCDC6) 1133 return -EINVAL; 1134 1135 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); 1136 workmode <<= id - AXP803_DCDC1; 1137 break; 1138 1139 case AXP813_ID: 1140 if (id < AXP813_DCDC1 || id > AXP813_DCDC7) 1141 return -EINVAL; 1142 1143 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1); 1144 workmode <<= id - AXP813_DCDC1; 1145 break; 1146 1147 default: 1148 /* should not happen */ 1149 WARN_ON(1); 1150 return -EINVAL; 1151 } 1152 1153 return regmap_update_bits(rdev->regmap, reg, mask, workmode); 1154 } 1155 1156 /* 1157 * This function checks whether a regulator is part of a poly-phase 1158 * output setup based on the registers settings. Returns true if it is. 1159 */ 1160 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id) 1161 { 1162 u32 reg = 0; 1163 1164 /* 1165 * Currently in our supported AXP variants, only AXP803, AXP806, 1166 * and AXP813 have polyphase regulators. 1167 */ 1168 switch (axp20x->variant) { 1169 case AXP803_ID: 1170 case AXP813_ID: 1171 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); 1172 1173 switch (id) { 1174 case AXP803_DCDC3: 1175 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); 1176 case AXP803_DCDC6: 1177 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); 1178 } 1179 break; 1180 1181 case AXP806_ID: 1182 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); 1183 1184 switch (id) { 1185 case AXP806_DCDCB: 1186 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1187 AXP806_DCDCAB_POLYPHASE_DUAL) || 1188 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1189 AXP806_DCDCABC_POLYPHASE_TRI)); 1190 case AXP806_DCDCC: 1191 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1192 AXP806_DCDCABC_POLYPHASE_TRI); 1193 case AXP806_DCDCE: 1194 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); 1195 } 1196 break; 1197 1198 default: 1199 return false; 1200 } 1201 1202 return false; 1203 } 1204 1205 static int axp20x_regulator_probe(struct platform_device *pdev) 1206 { 1207 struct regulator_dev *rdev; 1208 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1209 const struct regulator_desc *regulators; 1210 struct regulator_config config = { 1211 .dev = pdev->dev.parent, 1212 .regmap = axp20x->regmap, 1213 .driver_data = axp20x, 1214 }; 1215 int ret, i, nregulators; 1216 u32 workmode; 1217 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name; 1218 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name; 1219 bool drivevbus = false; 1220 1221 switch (axp20x->variant) { 1222 case AXP202_ID: 1223 case AXP209_ID: 1224 regulators = axp20x_regulators; 1225 nregulators = AXP20X_REG_ID_MAX; 1226 break; 1227 case AXP221_ID: 1228 case AXP223_ID: 1229 regulators = axp22x_regulators; 1230 nregulators = AXP22X_REG_ID_MAX; 1231 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1232 "x-powers,drive-vbus-en"); 1233 break; 1234 case AXP803_ID: 1235 regulators = axp803_regulators; 1236 nregulators = AXP803_REG_ID_MAX; 1237 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1238 "x-powers,drive-vbus-en"); 1239 break; 1240 case AXP806_ID: 1241 regulators = axp806_regulators; 1242 nregulators = AXP806_REG_ID_MAX; 1243 break; 1244 case AXP809_ID: 1245 regulators = axp809_regulators; 1246 nregulators = AXP809_REG_ID_MAX; 1247 break; 1248 case AXP813_ID: 1249 regulators = axp813_regulators; 1250 nregulators = AXP813_REG_ID_MAX; 1251 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1252 "x-powers,drive-vbus-en"); 1253 break; 1254 default: 1255 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n", 1256 axp20x->variant); 1257 return -EINVAL; 1258 } 1259 1260 /* This only sets the dcdc freq. Ignore any errors */ 1261 axp20x_regulator_parse_dt(pdev); 1262 1263 for (i = 0; i < nregulators; i++) { 1264 const struct regulator_desc *desc = ®ulators[i]; 1265 struct regulator_desc *new_desc; 1266 1267 /* 1268 * If this regulator is a slave in a poly-phase setup, 1269 * skip it, as its controls are bound to the master 1270 * regulator and won't work. 1271 */ 1272 if (axp20x_is_polyphase_slave(axp20x, i)) 1273 continue; 1274 1275 /* Support for AXP813's FLDO3 is not implemented */ 1276 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3) 1277 continue; 1278 1279 /* 1280 * Regulators DC1SW and DC5LDO are connected internally, 1281 * so we have to handle their supply names separately. 1282 * 1283 * We always register the regulators in proper sequence, 1284 * so the supply names are correctly read. See the last 1285 * part of this loop to see where we save the DT defined 1286 * name. 1287 */ 1288 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || 1289 (regulators == axp803_regulators && i == AXP803_DC1SW) || 1290 (regulators == axp809_regulators && i == AXP809_DC1SW)) { 1291 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1292 GFP_KERNEL); 1293 if (!new_desc) 1294 return -ENOMEM; 1295 1296 *new_desc = regulators[i]; 1297 new_desc->supply_name = dcdc1_name; 1298 desc = new_desc; 1299 } 1300 1301 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) || 1302 (regulators == axp809_regulators && i == AXP809_DC5LDO)) { 1303 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1304 GFP_KERNEL); 1305 if (!new_desc) 1306 return -ENOMEM; 1307 1308 *new_desc = regulators[i]; 1309 new_desc->supply_name = dcdc5_name; 1310 desc = new_desc; 1311 } 1312 1313 rdev = devm_regulator_register(&pdev->dev, desc, &config); 1314 if (IS_ERR(rdev)) { 1315 dev_err(&pdev->dev, "Failed to register %s\n", 1316 regulators[i].name); 1317 1318 return PTR_ERR(rdev); 1319 } 1320 1321 ret = of_property_read_u32(rdev->dev.of_node, 1322 "x-powers,dcdc-workmode", 1323 &workmode); 1324 if (!ret) { 1325 if (axp20x_set_dcdc_workmode(rdev, i, workmode)) 1326 dev_err(&pdev->dev, "Failed to set workmode on %s\n", 1327 rdev->desc->name); 1328 } 1329 1330 /* 1331 * Save AXP22X DCDC1 / DCDC5 regulator names for later. 1332 */ 1333 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) || 1334 (regulators == axp809_regulators && i == AXP809_DCDC1)) 1335 of_property_read_string(rdev->dev.of_node, 1336 "regulator-name", 1337 &dcdc1_name); 1338 1339 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) || 1340 (regulators == axp809_regulators && i == AXP809_DCDC5)) 1341 of_property_read_string(rdev->dev.of_node, 1342 "regulator-name", 1343 &dcdc5_name); 1344 } 1345 1346 if (drivevbus) { 1347 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */ 1348 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP, 1349 AXP22X_MISC_N_VBUSEN_FUNC, 0); 1350 rdev = devm_regulator_register(&pdev->dev, 1351 &axp22x_drivevbus_regulator, 1352 &config); 1353 if (IS_ERR(rdev)) { 1354 dev_err(&pdev->dev, "Failed to register drivevbus\n"); 1355 return PTR_ERR(rdev); 1356 } 1357 } 1358 1359 return 0; 1360 } 1361 1362 static struct platform_driver axp20x_regulator_driver = { 1363 .probe = axp20x_regulator_probe, 1364 .driver = { 1365 .name = "axp20x-regulator", 1366 }, 1367 }; 1368 1369 module_platform_driver(axp20x_regulator_driver); 1370 1371 MODULE_LICENSE("GPL v2"); 1372 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 1373 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); 1374 MODULE_ALIAS("platform:axp20x-regulator"); 1375