1 /*
2  * AXP20x regulators driver.
3  *
4  * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
5  *
6  * This file is subject to the terms and conditions of the GNU General
7  * Public License. See the file "COPYING" in the main directory of this
8  * archive for more details.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/mfd/axp20x.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/of_regulator.h>
29 
30 #define AXP20X_GPIO0_FUNC_MASK		GENMASK(3, 0)
31 #define AXP20X_GPIO1_FUNC_MASK		GENMASK(3, 0)
32 
33 #define AXP20X_IO_ENABLED		0x03
34 #define AXP20X_IO_DISABLED		0x07
35 
36 #define AXP20X_WORKMODE_DCDC2_MASK	BIT_MASK(2)
37 #define AXP20X_WORKMODE_DCDC3_MASK	BIT_MASK(1)
38 
39 #define AXP20X_FREQ_DCDC_MASK		GENMASK(3, 0)
40 
41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK	BIT_MASK(2)
42 
43 #define AXP20X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
44 #define AXP20X_DCDC3_V_OUT_MASK		GENMASK(7, 0)
45 #define AXP20X_LDO24_V_OUT_MASK		GENMASK(7, 4)
46 #define AXP20X_LDO3_V_OUT_MASK		GENMASK(6, 0)
47 #define AXP20X_LDO5_V_OUT_MASK		GENMASK(7, 4)
48 
49 #define AXP20X_PWR_OUT_EXTEN_MASK	BIT_MASK(0)
50 #define AXP20X_PWR_OUT_DCDC3_MASK	BIT_MASK(1)
51 #define AXP20X_PWR_OUT_LDO2_MASK	BIT_MASK(2)
52 #define AXP20X_PWR_OUT_LDO4_MASK	BIT_MASK(3)
53 #define AXP20X_PWR_OUT_DCDC2_MASK	BIT_MASK(4)
54 #define AXP20X_PWR_OUT_LDO3_MASK	BIT_MASK(6)
55 
56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK	BIT_MASK(0)
57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
58 	((x) << 0)
59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK		BIT_MASK(1)
60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
61 	((x) << 1)
62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK		BIT_MASK(2)
63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN		BIT(2)
64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK		BIT_MASK(3)
65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN		BIT(3)
66 
67 #define AXP20X_LDO4_V_OUT_1250mV_START	0x0
68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS	0
69 #define AXP20X_LDO4_V_OUT_1250mV_END	\
70 	(AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
71 #define AXP20X_LDO4_V_OUT_1300mV_START	0x1
72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS	7
73 #define AXP20X_LDO4_V_OUT_1300mV_END	\
74 	(AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
75 #define AXP20X_LDO4_V_OUT_2500mV_START	0x9
76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS	0
77 #define AXP20X_LDO4_V_OUT_2500mV_END	\
78 	(AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
79 #define AXP20X_LDO4_V_OUT_2700mV_START	0xa
80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS	1
81 #define AXP20X_LDO4_V_OUT_2700mV_END	\
82 	(AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
83 #define AXP20X_LDO4_V_OUT_3000mV_START	0xc
84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS	3
85 #define AXP20X_LDO4_V_OUT_3000mV_END	\
86 	(AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES	16
88 
89 #define AXP22X_IO_ENABLED		0x03
90 #define AXP22X_IO_DISABLED		0x04
91 
92 #define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT_MASK(x)
93 
94 #define AXP22X_MISC_N_VBUSEN_FUNC	BIT(4)
95 
96 #define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
97 #define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
98 #define AXP22X_DCDC3_V_OUT_MASK		GENMASK(5, 0)
99 #define AXP22X_DCDC4_V_OUT_MASK		GENMASK(5, 0)
100 #define AXP22X_DCDC5_V_OUT_MASK		GENMASK(4, 0)
101 #define AXP22X_DC5LDO_V_OUT_MASK	GENMASK(2, 0)
102 #define AXP22X_ALDO1_V_OUT_MASK		GENMASK(4, 0)
103 #define AXP22X_ALDO2_V_OUT_MASK		GENMASK(4, 0)
104 #define AXP22X_ALDO3_V_OUT_MASK		GENMASK(4, 0)
105 #define AXP22X_DLDO1_V_OUT_MASK		GENMASK(4, 0)
106 #define AXP22X_DLDO2_V_OUT_MASK		GENMASK(4, 0)
107 #define AXP22X_DLDO3_V_OUT_MASK		GENMASK(4, 0)
108 #define AXP22X_DLDO4_V_OUT_MASK		GENMASK(4, 0)
109 #define AXP22X_ELDO1_V_OUT_MASK		GENMASK(4, 0)
110 #define AXP22X_ELDO2_V_OUT_MASK		GENMASK(4, 0)
111 #define AXP22X_ELDO3_V_OUT_MASK		GENMASK(4, 0)
112 #define AXP22X_LDO_IO0_V_OUT_MASK	GENMASK(4, 0)
113 #define AXP22X_LDO_IO1_V_OUT_MASK	GENMASK(4, 0)
114 
115 #define AXP22X_PWR_OUT_DC5LDO_MASK	BIT_MASK(0)
116 #define AXP22X_PWR_OUT_DCDC1_MASK	BIT_MASK(1)
117 #define AXP22X_PWR_OUT_DCDC2_MASK	BIT_MASK(2)
118 #define AXP22X_PWR_OUT_DCDC3_MASK	BIT_MASK(3)
119 #define AXP22X_PWR_OUT_DCDC4_MASK	BIT_MASK(4)
120 #define AXP22X_PWR_OUT_DCDC5_MASK	BIT_MASK(5)
121 #define AXP22X_PWR_OUT_ALDO1_MASK	BIT_MASK(6)
122 #define AXP22X_PWR_OUT_ALDO2_MASK	BIT_MASK(7)
123 
124 #define AXP22X_PWR_OUT_SW_MASK		BIT_MASK(6)
125 #define AXP22X_PWR_OUT_DC1SW_MASK	BIT_MASK(7)
126 
127 #define AXP22X_PWR_OUT_ELDO1_MASK	BIT_MASK(0)
128 #define AXP22X_PWR_OUT_ELDO2_MASK	BIT_MASK(1)
129 #define AXP22X_PWR_OUT_ELDO3_MASK	BIT_MASK(2)
130 #define AXP22X_PWR_OUT_DLDO1_MASK	BIT_MASK(3)
131 #define AXP22X_PWR_OUT_DLDO2_MASK	BIT_MASK(4)
132 #define AXP22X_PWR_OUT_DLDO3_MASK	BIT_MASK(5)
133 #define AXP22X_PWR_OUT_DLDO4_MASK	BIT_MASK(6)
134 #define AXP22X_PWR_OUT_ALDO3_MASK	BIT_MASK(7)
135 
136 #define AXP803_PWR_OUT_DCDC1_MASK	BIT_MASK(0)
137 #define AXP803_PWR_OUT_DCDC2_MASK	BIT_MASK(1)
138 #define AXP803_PWR_OUT_DCDC3_MASK	BIT_MASK(2)
139 #define AXP803_PWR_OUT_DCDC4_MASK	BIT_MASK(3)
140 #define AXP803_PWR_OUT_DCDC5_MASK	BIT_MASK(4)
141 #define AXP803_PWR_OUT_DCDC6_MASK	BIT_MASK(5)
142 
143 #define AXP803_PWR_OUT_FLDO1_MASK	BIT_MASK(2)
144 #define AXP803_PWR_OUT_FLDO2_MASK	BIT_MASK(3)
145 
146 #define AXP803_DCDC1_V_OUT_MASK		GENMASK(4, 0)
147 #define AXP803_DCDC2_V_OUT_MASK		GENMASK(6, 0)
148 #define AXP803_DCDC3_V_OUT_MASK		GENMASK(6, 0)
149 #define AXP803_DCDC4_V_OUT_MASK		GENMASK(6, 0)
150 #define AXP803_DCDC5_V_OUT_MASK		GENMASK(6, 0)
151 #define AXP803_DCDC6_V_OUT_MASK		GENMASK(6, 0)
152 
153 #define AXP803_FLDO1_V_OUT_MASK		GENMASK(3, 0)
154 #define AXP803_FLDO2_V_OUT_MASK		GENMASK(3, 0)
155 
156 #define AXP803_DCDC23_POLYPHASE_DUAL	BIT(6)
157 #define AXP803_DCDC56_POLYPHASE_DUAL	BIT(5)
158 
159 #define AXP803_DCDC234_500mV_START	0x00
160 #define AXP803_DCDC234_500mV_STEPS	70
161 #define AXP803_DCDC234_500mV_END	\
162 	(AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
163 #define AXP803_DCDC234_1220mV_START	0x47
164 #define AXP803_DCDC234_1220mV_STEPS	4
165 #define AXP803_DCDC234_1220mV_END	\
166 	(AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
167 #define AXP803_DCDC234_NUM_VOLTAGES	76
168 
169 #define AXP803_DCDC5_800mV_START	0x00
170 #define AXP803_DCDC5_800mV_STEPS	32
171 #define AXP803_DCDC5_800mV_END		\
172 	(AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
173 #define AXP803_DCDC5_1140mV_START	0x21
174 #define AXP803_DCDC5_1140mV_STEPS	35
175 #define AXP803_DCDC5_1140mV_END		\
176 	(AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
177 #define AXP803_DCDC5_NUM_VOLTAGES	68
178 
179 #define AXP803_DCDC6_600mV_START	0x00
180 #define AXP803_DCDC6_600mV_STEPS	50
181 #define AXP803_DCDC6_600mV_END		\
182 	(AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
183 #define AXP803_DCDC6_1120mV_START	0x33
184 #define AXP803_DCDC6_1120mV_STEPS	14
185 #define AXP803_DCDC6_1120mV_END		\
186 	(AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
187 #define AXP803_DCDC6_NUM_VOLTAGES	72
188 
189 #define AXP803_DLDO2_700mV_START	0x00
190 #define AXP803_DLDO2_700mV_STEPS	26
191 #define AXP803_DLDO2_700mV_END		\
192 	(AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
193 #define AXP803_DLDO2_3400mV_START	0x1b
194 #define AXP803_DLDO2_3400mV_STEPS	4
195 #define AXP803_DLDO2_3400mV_END		\
196 	(AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
197 #define AXP803_DLDO2_NUM_VOLTAGES	32
198 
199 #define AXP806_DCDCA_V_CTRL_MASK	GENMASK(6, 0)
200 #define AXP806_DCDCB_V_CTRL_MASK	GENMASK(4, 0)
201 #define AXP806_DCDCC_V_CTRL_MASK	GENMASK(6, 0)
202 #define AXP806_DCDCD_V_CTRL_MASK	GENMASK(5, 0)
203 #define AXP806_DCDCE_V_CTRL_MASK	GENMASK(4, 0)
204 #define AXP806_ALDO1_V_CTRL_MASK	GENMASK(4, 0)
205 #define AXP806_ALDO2_V_CTRL_MASK	GENMASK(4, 0)
206 #define AXP806_ALDO3_V_CTRL_MASK	GENMASK(4, 0)
207 #define AXP806_BLDO1_V_CTRL_MASK	GENMASK(3, 0)
208 #define AXP806_BLDO2_V_CTRL_MASK	GENMASK(3, 0)
209 #define AXP806_BLDO3_V_CTRL_MASK	GENMASK(3, 0)
210 #define AXP806_BLDO4_V_CTRL_MASK	GENMASK(3, 0)
211 #define AXP806_CLDO1_V_CTRL_MASK	GENMASK(4, 0)
212 #define AXP806_CLDO2_V_CTRL_MASK	GENMASK(4, 0)
213 #define AXP806_CLDO3_V_CTRL_MASK	GENMASK(4, 0)
214 
215 #define AXP806_PWR_OUT_DCDCA_MASK	BIT_MASK(0)
216 #define AXP806_PWR_OUT_DCDCB_MASK	BIT_MASK(1)
217 #define AXP806_PWR_OUT_DCDCC_MASK	BIT_MASK(2)
218 #define AXP806_PWR_OUT_DCDCD_MASK	BIT_MASK(3)
219 #define AXP806_PWR_OUT_DCDCE_MASK	BIT_MASK(4)
220 #define AXP806_PWR_OUT_ALDO1_MASK	BIT_MASK(5)
221 #define AXP806_PWR_OUT_ALDO2_MASK	BIT_MASK(6)
222 #define AXP806_PWR_OUT_ALDO3_MASK	BIT_MASK(7)
223 #define AXP806_PWR_OUT_BLDO1_MASK	BIT_MASK(0)
224 #define AXP806_PWR_OUT_BLDO2_MASK	BIT_MASK(1)
225 #define AXP806_PWR_OUT_BLDO3_MASK	BIT_MASK(2)
226 #define AXP806_PWR_OUT_BLDO4_MASK	BIT_MASK(3)
227 #define AXP806_PWR_OUT_CLDO1_MASK	BIT_MASK(4)
228 #define AXP806_PWR_OUT_CLDO2_MASK	BIT_MASK(5)
229 #define AXP806_PWR_OUT_CLDO3_MASK	BIT_MASK(6)
230 #define AXP806_PWR_OUT_SW_MASK		BIT_MASK(7)
231 
232 #define AXP806_DCDCAB_POLYPHASE_DUAL	0x40
233 #define AXP806_DCDCABC_POLYPHASE_TRI	0x80
234 #define AXP806_DCDCABC_POLYPHASE_MASK	GENMASK(7, 6)
235 
236 #define AXP806_DCDCDE_POLYPHASE_DUAL	BIT(5)
237 
238 #define AXP806_DCDCA_600mV_START	0x00
239 #define AXP806_DCDCA_600mV_STEPS	50
240 #define AXP806_DCDCA_600mV_END		\
241 	(AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
242 #define AXP806_DCDCA_1120mV_START	0x33
243 #define AXP806_DCDCA_1120mV_STEPS	14
244 #define AXP806_DCDCA_1120mV_END		\
245 	(AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
246 #define AXP806_DCDCA_NUM_VOLTAGES	72
247 
248 #define AXP806_DCDCD_600mV_START	0x00
249 #define AXP806_DCDCD_600mV_STEPS	45
250 #define AXP806_DCDCD_600mV_END		\
251 	(AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
252 #define AXP806_DCDCD_1600mV_START	0x2e
253 #define AXP806_DCDCD_1600mV_STEPS	17
254 #define AXP806_DCDCD_1600mV_END		\
255 	(AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
256 #define AXP806_DCDCD_NUM_VOLTAGES	64
257 
258 #define AXP809_DCDC4_600mV_START	0x00
259 #define AXP809_DCDC4_600mV_STEPS	47
260 #define AXP809_DCDC4_600mV_END		\
261 	(AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
262 #define AXP809_DCDC4_1800mV_START	0x30
263 #define AXP809_DCDC4_1800mV_STEPS	8
264 #define AXP809_DCDC4_1800mV_END		\
265 	(AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
266 #define AXP809_DCDC4_NUM_VOLTAGES	57
267 
268 #define AXP813_DCDC7_V_OUT_MASK		GENMASK(6, 0)
269 
270 #define AXP813_PWR_OUT_DCDC7_MASK	BIT_MASK(6)
271 
272 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,	\
273 		    _vmask, _ereg, _emask, _enable_val, _disable_val)		\
274 	[_family##_##_id] = {							\
275 		.name		= (_match),					\
276 		.supply_name	= (_supply),					\
277 		.of_match	= of_match_ptr(_match),				\
278 		.regulators_node = of_match_ptr("regulators"),			\
279 		.type		= REGULATOR_VOLTAGE,				\
280 		.id		= _family##_##_id,				\
281 		.n_voltages	= (((_max) - (_min)) / (_step) + 1),		\
282 		.owner		= THIS_MODULE,					\
283 		.min_uV		= (_min) * 1000,				\
284 		.uV_step	= (_step) * 1000,				\
285 		.vsel_reg	= (_vreg),					\
286 		.vsel_mask	= (_vmask),					\
287 		.enable_reg	= (_ereg),					\
288 		.enable_mask	= (_emask),					\
289 		.enable_val	= (_enable_val),				\
290 		.disable_val	= (_disable_val),				\
291 		.ops		= &axp20x_ops,					\
292 	}
293 
294 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,	\
295 		 _vmask, _ereg, _emask) 					\
296 	[_family##_##_id] = {							\
297 		.name		= (_match),					\
298 		.supply_name	= (_supply),					\
299 		.of_match	= of_match_ptr(_match),				\
300 		.regulators_node = of_match_ptr("regulators"),			\
301 		.type		= REGULATOR_VOLTAGE,				\
302 		.id		= _family##_##_id,				\
303 		.n_voltages	= (((_max) - (_min)) / (_step) + 1),		\
304 		.owner		= THIS_MODULE,					\
305 		.min_uV		= (_min) * 1000,				\
306 		.uV_step	= (_step) * 1000,				\
307 		.vsel_reg	= (_vreg),					\
308 		.vsel_mask	= (_vmask),					\
309 		.enable_reg	= (_ereg),					\
310 		.enable_mask	= (_emask),					\
311 		.ops		= &axp20x_ops,					\
312 	}
313 
314 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask)		\
315 	[_family##_##_id] = {							\
316 		.name		= (_match),					\
317 		.supply_name	= (_supply),					\
318 		.of_match	= of_match_ptr(_match),				\
319 		.regulators_node = of_match_ptr("regulators"),			\
320 		.type		= REGULATOR_VOLTAGE,				\
321 		.id		= _family##_##_id,				\
322 		.owner		= THIS_MODULE,					\
323 		.enable_reg	= (_ereg),					\
324 		.enable_mask	= (_emask),					\
325 		.ops		= &axp20x_ops_sw,				\
326 	}
327 
328 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)			\
329 	[_family##_##_id] = {							\
330 		.name		= (_match),					\
331 		.supply_name	= (_supply),					\
332 		.of_match	= of_match_ptr(_match),				\
333 		.regulators_node = of_match_ptr("regulators"),			\
334 		.type		= REGULATOR_VOLTAGE,				\
335 		.id		= _family##_##_id,				\
336 		.n_voltages	= 1,						\
337 		.owner		= THIS_MODULE,					\
338 		.min_uV		= (_volt) * 1000,				\
339 		.ops		= &axp20x_ops_fixed				\
340 	}
341 
342 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages,	\
343 			_vreg, _vmask, _ereg, _emask)				\
344 	[_family##_##_id] = {							\
345 		.name		= (_match),					\
346 		.supply_name	= (_supply),					\
347 		.of_match	= of_match_ptr(_match),				\
348 		.regulators_node = of_match_ptr("regulators"),			\
349 		.type		= REGULATOR_VOLTAGE,				\
350 		.id		= _family##_##_id,				\
351 		.n_voltages	= (_n_voltages),				\
352 		.owner		= THIS_MODULE,					\
353 		.vsel_reg	= (_vreg),					\
354 		.vsel_mask	= (_vmask),					\
355 		.enable_reg	= (_ereg),					\
356 		.enable_mask	= (_emask),					\
357 		.linear_ranges	= (_ranges),					\
358 		.n_linear_ranges = ARRAY_SIZE(_ranges),				\
359 		.ops		= &axp20x_ops_range,				\
360 	}
361 
362 static const int axp209_dcdc2_ldo3_slew_rates[] = {
363 	1600,
364 	 800,
365 };
366 
367 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
368 {
369 	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
370 	const struct regulator_desc *desc;
371 	u8 reg, mask, enable, cfg = 0xff;
372 	const int *slew_rates;
373 	int rate_count = 0;
374 
375 	desc = rdev->desc;
376 
377 	switch (axp20x->variant) {
378 	case AXP209_ID:
379 		if (desc->id == AXP20X_DCDC2) {
380 			slew_rates = axp209_dcdc2_ldo3_slew_rates;
381 			rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
382 			reg = AXP20X_DCDC2_LDO3_V_RAMP;
383 			mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
384 			       AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
385 			enable = (ramp > 0) ?
386 				 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN :
387 				 !AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN;
388 			break;
389 		}
390 
391 		if (desc->id == AXP20X_LDO3) {
392 			slew_rates = axp209_dcdc2_ldo3_slew_rates;
393 			rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
394 			reg = AXP20X_DCDC2_LDO3_V_RAMP;
395 			mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
396 			       AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
397 			enable = (ramp > 0) ?
398 				 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN :
399 				 !AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN;
400 			break;
401 		}
402 
403 		if (rate_count > 0)
404 			break;
405 
406 		/* fall through */
407 	default:
408 		/* Not supported for this regulator */
409 		return -ENOTSUPP;
410 	}
411 
412 	if (ramp == 0) {
413 		cfg = enable;
414 	} else {
415 		int i;
416 
417 		for (i = 0; i < rate_count; i++) {
418 			if (ramp <= slew_rates[i])
419 				cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
420 			else
421 				break;
422 		}
423 
424 		if (cfg == 0xff) {
425 			dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
426 			return -EINVAL;
427 		}
428 
429 		cfg |= enable;
430 	}
431 
432 	return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
433 }
434 
435 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
436 {
437 	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
438 	const struct regulator_desc *desc;
439 
440 	if (!rdev)
441 		return -EINVAL;
442 
443 	desc = rdev->desc;
444 
445 	switch (axp20x->variant) {
446 	case AXP209_ID:
447 		if ((desc->id == AXP20X_LDO3) &&
448 		    rdev->constraints && rdev->constraints->soft_start) {
449 			int v_out;
450 			int ret;
451 
452 			/*
453 			 * On some boards, the LDO3 can be overloaded when
454 			 * turning on, causing the entire PMIC to shutdown
455 			 * without warning. Turning it on at the minimal voltage
456 			 * and then setting the voltage to the requested value
457 			 * works reliably.
458 			 */
459 			if (regulator_is_enabled_regmap(rdev))
460 				break;
461 
462 			v_out = regulator_get_voltage_sel_regmap(rdev);
463 			if (v_out < 0)
464 				return v_out;
465 
466 			if (v_out == 0)
467 				break;
468 
469 			ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
470 			/*
471 			 * A small pause is needed between
472 			 * setting the voltage and enabling the LDO to give the
473 			 * internal state machine time to process the request.
474 			 */
475 			usleep_range(1000, 5000);
476 			ret |= regulator_enable_regmap(rdev);
477 			ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
478 
479 			return ret;
480 		}
481 		break;
482 	default:
483 		/* No quirks */
484 		break;
485 	}
486 
487 	return regulator_enable_regmap(rdev);
488 };
489 
490 static const struct regulator_ops axp20x_ops_fixed = {
491 	.list_voltage		= regulator_list_voltage_linear,
492 };
493 
494 static const struct regulator_ops axp20x_ops_range = {
495 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
496 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
497 	.list_voltage		= regulator_list_voltage_linear_range,
498 	.enable			= regulator_enable_regmap,
499 	.disable		= regulator_disable_regmap,
500 	.is_enabled		= regulator_is_enabled_regmap,
501 };
502 
503 static const struct regulator_ops axp20x_ops = {
504 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
505 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
506 	.list_voltage		= regulator_list_voltage_linear,
507 	.enable			= axp20x_regulator_enable_regmap,
508 	.disable		= regulator_disable_regmap,
509 	.is_enabled		= regulator_is_enabled_regmap,
510 	.set_ramp_delay		= axp20x_set_ramp_delay,
511 };
512 
513 static const struct regulator_ops axp20x_ops_sw = {
514 	.enable			= regulator_enable_regmap,
515 	.disable		= regulator_disable_regmap,
516 	.is_enabled		= regulator_is_enabled_regmap,
517 };
518 
519 static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
520 	REGULATOR_LINEAR_RANGE(1250000,
521 			       AXP20X_LDO4_V_OUT_1250mV_START,
522 			       AXP20X_LDO4_V_OUT_1250mV_END,
523 			       0),
524 	REGULATOR_LINEAR_RANGE(1300000,
525 			       AXP20X_LDO4_V_OUT_1300mV_START,
526 			       AXP20X_LDO4_V_OUT_1300mV_END,
527 			       100000),
528 	REGULATOR_LINEAR_RANGE(2500000,
529 			       AXP20X_LDO4_V_OUT_2500mV_START,
530 			       AXP20X_LDO4_V_OUT_2500mV_END,
531 			       0),
532 	REGULATOR_LINEAR_RANGE(2700000,
533 			       AXP20X_LDO4_V_OUT_2700mV_START,
534 			       AXP20X_LDO4_V_OUT_2700mV_END,
535 			       100000),
536 	REGULATOR_LINEAR_RANGE(3000000,
537 			       AXP20X_LDO4_V_OUT_3000mV_START,
538 			       AXP20X_LDO4_V_OUT_3000mV_END,
539 			       100000),
540 };
541 
542 static const struct regulator_desc axp20x_regulators[] = {
543 	AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
544 		 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
545 		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
546 	AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
547 		 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
548 		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
549 	AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
550 	AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
551 		 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK,
552 		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
553 	AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
554 		 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
555 		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
556 	AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
557 			axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
558 			AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK,
559 			AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
560 	AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
561 		    AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
562 		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
563 		    AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
564 };
565 
566 static const struct regulator_desc axp22x_regulators[] = {
567 	AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
568 		 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
569 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
570 	AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
571 		 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
572 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
573 	AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
574 		 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
575 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
576 	AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
577 		 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
578 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
579 	AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
580 		 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
581 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
582 	/* secondary switchable output of DCDC1 */
583 	AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
584 		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
585 	/* LDO regulator internally chained to DCDC5 */
586 	AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
587 		 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
588 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
589 	AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
590 		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
591 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
592 	AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
593 		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
594 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
595 	AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
596 		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
597 		 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
598 	AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
599 		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
600 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
601 	AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
602 		 AXP22X_DLDO2_V_OUT, AXP22X_PWR_OUT_DLDO2_MASK,
603 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
604 	AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
605 		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
606 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
607 	AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
608 		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
609 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
610 	AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
611 		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
612 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
613 	AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
614 		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
615 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
616 	AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
617 		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
618 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
619 	/* Note the datasheet only guarantees reliable operation up to
620 	 * 3.3V, this needs to be enforced via dts provided constraints */
621 	AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
622 		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
623 		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
624 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
625 	/* Note the datasheet only guarantees reliable operation up to
626 	 * 3.3V, this needs to be enforced via dts provided constraints */
627 	AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
628 		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
629 		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
630 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
631 	AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
632 };
633 
634 static const struct regulator_desc axp22x_drivevbus_regulator = {
635 	.name		= "drivevbus",
636 	.supply_name	= "drivevbus",
637 	.of_match	= of_match_ptr("drivevbus"),
638 	.regulators_node = of_match_ptr("regulators"),
639 	.type		= REGULATOR_VOLTAGE,
640 	.owner		= THIS_MODULE,
641 	.enable_reg	= AXP20X_VBUS_IPSOUT_MGMT,
642 	.enable_mask	= AXP20X_VBUS_IPSOUT_MGMT_MASK,
643 	.ops		= &axp20x_ops_sw,
644 };
645 
646 /* DCDC ranges shared with AXP813 */
647 static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
648 	REGULATOR_LINEAR_RANGE(500000,
649 			       AXP803_DCDC234_500mV_START,
650 			       AXP803_DCDC234_500mV_END,
651 			       10000),
652 	REGULATOR_LINEAR_RANGE(1220000,
653 			       AXP803_DCDC234_1220mV_START,
654 			       AXP803_DCDC234_1220mV_END,
655 			       20000),
656 };
657 
658 static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
659 	REGULATOR_LINEAR_RANGE(800000,
660 			       AXP803_DCDC5_800mV_START,
661 			       AXP803_DCDC5_800mV_END,
662 			       10000),
663 	REGULATOR_LINEAR_RANGE(1140000,
664 			       AXP803_DCDC5_1140mV_START,
665 			       AXP803_DCDC5_1140mV_END,
666 			       20000),
667 };
668 
669 static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
670 	REGULATOR_LINEAR_RANGE(600000,
671 			       AXP803_DCDC6_600mV_START,
672 			       AXP803_DCDC6_600mV_END,
673 			       10000),
674 	REGULATOR_LINEAR_RANGE(1120000,
675 			       AXP803_DCDC6_1120mV_START,
676 			       AXP803_DCDC6_1120mV_END,
677 			       20000),
678 };
679 
680 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
681 static const struct regulator_linear_range axp803_dldo2_ranges[] = {
682 	REGULATOR_LINEAR_RANGE(700000,
683 			       AXP803_DLDO2_700mV_START,
684 			       AXP803_DLDO2_700mV_END,
685 			       100000),
686 	REGULATOR_LINEAR_RANGE(3400000,
687 			       AXP803_DLDO2_3400mV_START,
688 			       AXP803_DLDO2_3400mV_END,
689 			       200000),
690 };
691 
692 static const struct regulator_desc axp803_regulators[] = {
693 	AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
694 		 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
695 		 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
696 	AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
697 			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
698 			AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
699 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
700 	AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
701 			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
702 			AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
703 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
704 	AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
705 			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
706 			AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
707 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
708 	AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
709 			axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
710 			AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
711 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
712 	AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
713 			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
714 			AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
715 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
716 	/* secondary switchable output of DCDC1 */
717 	AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
718 		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
719 	AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
720 		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
721 		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
722 	AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
723 		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
724 		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
725 	AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
726 		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
727 		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
728 	AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
729 		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
730 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
731 	AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
732 			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
733 			AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
734 			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
735 	AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
736 		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
737 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
738 	AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
739 		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
740 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
741 	AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
742 		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
743 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
744 	AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
745 		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
746 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
747 	AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
748 		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
749 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
750 	AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
751 		 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
752 		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
753 	AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
754 		 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
755 		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
756 	AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
757 		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
758 		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
759 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
760 	AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
761 		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
762 		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
763 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
764 	AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
765 };
766 
767 static const struct regulator_linear_range axp806_dcdca_ranges[] = {
768 	REGULATOR_LINEAR_RANGE(600000,
769 			       AXP806_DCDCA_600mV_START,
770 			       AXP806_DCDCA_600mV_END,
771 			       10000),
772 	REGULATOR_LINEAR_RANGE(1120000,
773 			       AXP806_DCDCA_1120mV_START,
774 			       AXP806_DCDCA_1120mV_END,
775 			       20000),
776 };
777 
778 static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
779 	REGULATOR_LINEAR_RANGE(600000,
780 			       AXP806_DCDCD_600mV_START,
781 			       AXP806_DCDCD_600mV_END,
782 			       20000),
783 	REGULATOR_LINEAR_RANGE(1600000,
784 			       AXP806_DCDCD_600mV_START,
785 			       AXP806_DCDCD_600mV_END,
786 			       100000),
787 };
788 
789 static const struct regulator_desc axp806_regulators[] = {
790 	AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
791 			axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
792 			AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
793 			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
794 	AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
795 		 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
796 		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
797 	AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
798 			axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
799 			AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
800 			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
801 	AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
802 			axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
803 			AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
804 			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
805 	AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
806 		 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
807 		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
808 	AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
809 		 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
810 		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
811 	AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
812 		 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
813 		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
814 	AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
815 		 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
816 		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
817 	AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
818 		 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
819 		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
820 	AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
821 		 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
822 		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
823 	AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
824 		 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
825 		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
826 	AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
827 		 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
828 		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
829 	AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
830 		 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
831 		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
832 	AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
833 			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
834 			AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
835 			AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
836 	AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
837 		 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
838 		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
839 	AXP_DESC_SW(AXP806, SW, "sw", "swin",
840 		    AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
841 };
842 
843 static const struct regulator_linear_range axp809_dcdc4_ranges[] = {
844 	REGULATOR_LINEAR_RANGE(600000,
845 			       AXP809_DCDC4_600mV_START,
846 			       AXP809_DCDC4_600mV_END,
847 			       20000),
848 	REGULATOR_LINEAR_RANGE(1800000,
849 			       AXP809_DCDC4_1800mV_START,
850 			       AXP809_DCDC4_1800mV_END,
851 			       100000),
852 };
853 
854 static const struct regulator_desc axp809_regulators[] = {
855 	AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
856 		 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
857 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
858 	AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
859 		 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
860 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
861 	AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
862 		 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
863 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
864 	AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
865 			axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
866 			AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
867 			AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
868 	AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
869 		 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
870 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
871 	/* secondary switchable output of DCDC1 */
872 	AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
873 		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
874 	/* LDO regulator internally chained to DCDC5 */
875 	AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
876 		 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
877 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
878 	AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
879 		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
880 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
881 	AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
882 		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
883 		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
884 	AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
885 		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
886 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
887 	AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
888 			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
889 			AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
890 			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
891 	AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
892 		 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
893 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
894 	AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
895 		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
896 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
897 	AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
898 		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
899 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
900 	AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
901 		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
902 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
903 	/*
904 	 * Note the datasheet only guarantees reliable operation up to
905 	 * 3.3V, this needs to be enforced via dts provided constraints
906 	 */
907 	AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
908 		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
909 		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
910 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
911 	/*
912 	 * Note the datasheet only guarantees reliable operation up to
913 	 * 3.3V, this needs to be enforced via dts provided constraints
914 	 */
915 	AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
916 		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
917 		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
918 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
919 	AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
920 	AXP_DESC_SW(AXP809, SW, "sw", "swin",
921 		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
922 };
923 
924 static const struct regulator_desc axp813_regulators[] = {
925 	AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
926 		 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
927 		 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
928 	AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
929 			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
930 			AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
931 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
932 	AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
933 			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
934 			AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
935 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
936 	AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
937 			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
938 			AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
939 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
940 	AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
941 			axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
942 			AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
943 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
944 	AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
945 			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
946 			AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
947 			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
948 	AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
949 			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
950 			AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
951 			AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
952 	AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
953 		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
954 		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
955 	AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
956 		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
957 		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
958 	AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
959 		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
960 		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
961 	AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
962 		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
963 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
964 	AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
965 			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
966 			AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
967 			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
968 	AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
969 		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
970 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
971 	AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
972 		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
973 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
974 	AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
975 		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
976 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
977 	AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
978 		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
979 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
980 	AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
981 		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
982 		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
983 	/* to do / check ... */
984 	AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
985 		 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
986 		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
987 	AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
988 		 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
989 		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
990 	/*
991 	 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
992 	 *
993 	 * This means FLDO3 effectively switches supplies at runtime,
994 	 * something the regulator subsystem does not support.
995 	 */
996 	AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
997 	AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
998 		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
999 		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
1000 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1001 	AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
1002 		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1003 		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1004 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1005 	AXP_DESC_SW(AXP813, SW, "sw", "swin",
1006 		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1007 };
1008 
1009 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1010 {
1011 	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1012 	unsigned int reg = AXP20X_DCDC_FREQ;
1013 	u32 min, max, def, step;
1014 
1015 	switch (axp20x->variant) {
1016 	case AXP202_ID:
1017 	case AXP209_ID:
1018 		min = 750;
1019 		max = 1875;
1020 		def = 1500;
1021 		step = 75;
1022 		break;
1023 	case AXP803_ID:
1024 	case AXP813_ID:
1025 		/*
1026 		 * AXP803/AXP813 DCDC work frequency setting has the same
1027 		 * range and step as AXP22X, but at a different register.
1028 		 * (See include/linux/mfd/axp20x.h)
1029 		 */
1030 		reg = AXP803_DCDC_FREQ_CTRL;
1031 		/* Fall through to the check below.*/
1032 	case AXP806_ID:
1033 		/*
1034 		 * AXP806 also have DCDC work frequency setting register at a
1035 		 * different position.
1036 		 */
1037 		if (axp20x->variant == AXP806_ID)
1038 			reg = AXP806_DCDC_FREQ_CTRL;
1039 		/* Fall through */
1040 	case AXP221_ID:
1041 	case AXP223_ID:
1042 	case AXP809_ID:
1043 		min = 1800;
1044 		max = 4050;
1045 		def = 3000;
1046 		step = 150;
1047 		break;
1048 	default:
1049 		dev_err(&pdev->dev,
1050 			"Setting DCDC frequency for unsupported AXP variant\n");
1051 		return -EINVAL;
1052 	}
1053 
1054 	if (dcdcfreq == 0)
1055 		dcdcfreq = def;
1056 
1057 	if (dcdcfreq < min) {
1058 		dcdcfreq = min;
1059 		dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1060 			 min);
1061 	}
1062 
1063 	if (dcdcfreq > max) {
1064 		dcdcfreq = max;
1065 		dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1066 			 max);
1067 	}
1068 
1069 	dcdcfreq = (dcdcfreq - min) / step;
1070 
1071 	return regmap_update_bits(axp20x->regmap, reg,
1072 				  AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1073 }
1074 
1075 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1076 {
1077 	struct device_node *np, *regulators;
1078 	int ret;
1079 	u32 dcdcfreq = 0;
1080 
1081 	np = of_node_get(pdev->dev.parent->of_node);
1082 	if (!np)
1083 		return 0;
1084 
1085 	regulators = of_get_child_by_name(np, "regulators");
1086 	if (!regulators) {
1087 		dev_warn(&pdev->dev, "regulators node not found\n");
1088 	} else {
1089 		of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1090 		ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1091 		if (ret < 0) {
1092 			dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1093 			return ret;
1094 		}
1095 
1096 		of_node_put(regulators);
1097 	}
1098 
1099 	return 0;
1100 }
1101 
1102 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1103 {
1104 	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1105 	unsigned int reg = AXP20X_DCDC_MODE;
1106 	unsigned int mask;
1107 
1108 	switch (axp20x->variant) {
1109 	case AXP202_ID:
1110 	case AXP209_ID:
1111 		if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1112 			return -EINVAL;
1113 
1114 		mask = AXP20X_WORKMODE_DCDC2_MASK;
1115 		if (id == AXP20X_DCDC3)
1116 			mask = AXP20X_WORKMODE_DCDC3_MASK;
1117 
1118 		workmode <<= ffs(mask) - 1;
1119 		break;
1120 
1121 	case AXP806_ID:
1122 		reg = AXP806_DCDC_MODE_CTRL2;
1123 		/*
1124 		 * AXP806 DCDC regulator IDs have the same range as AXP22X.
1125 		 * Fall through to the check below.
1126 		 * (See include/linux/mfd/axp20x.h)
1127 		 */
1128 	case AXP221_ID:
1129 	case AXP223_ID:
1130 	case AXP809_ID:
1131 		if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1132 			return -EINVAL;
1133 
1134 		mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1135 		workmode <<= id - AXP22X_DCDC1;
1136 		break;
1137 
1138 	case AXP803_ID:
1139 		if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1140 			return -EINVAL;
1141 
1142 		mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1143 		workmode <<= id - AXP803_DCDC1;
1144 		break;
1145 
1146 	case AXP813_ID:
1147 		if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1148 			return -EINVAL;
1149 
1150 		mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1151 		workmode <<= id - AXP813_DCDC1;
1152 		break;
1153 
1154 	default:
1155 		/* should not happen */
1156 		WARN_ON(1);
1157 		return -EINVAL;
1158 	}
1159 
1160 	return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1161 }
1162 
1163 /*
1164  * This function checks whether a regulator is part of a poly-phase
1165  * output setup based on the registers settings. Returns true if it is.
1166  */
1167 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1168 {
1169 	u32 reg = 0;
1170 
1171 	/*
1172 	 * Currently in our supported AXP variants, only AXP803, AXP806,
1173 	 * and AXP813 have polyphase regulators.
1174 	 */
1175 	switch (axp20x->variant) {
1176 	case AXP803_ID:
1177 	case AXP813_ID:
1178 		regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
1179 
1180 		switch (id) {
1181 		case AXP803_DCDC3:
1182 			return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1183 		case AXP803_DCDC6:
1184 			return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1185 		}
1186 		break;
1187 
1188 	case AXP806_ID:
1189 		regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
1190 
1191 		switch (id) {
1192 		case AXP806_DCDCB:
1193 			return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1194 				AXP806_DCDCAB_POLYPHASE_DUAL) ||
1195 				((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1196 				AXP806_DCDCABC_POLYPHASE_TRI));
1197 		case AXP806_DCDCC:
1198 			return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1199 				AXP806_DCDCABC_POLYPHASE_TRI);
1200 		case AXP806_DCDCE:
1201 			return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1202 		}
1203 		break;
1204 
1205 	default:
1206 		return false;
1207 	}
1208 
1209 	return false;
1210 }
1211 
1212 static int axp20x_regulator_probe(struct platform_device *pdev)
1213 {
1214 	struct regulator_dev *rdev;
1215 	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1216 	const struct regulator_desc *regulators;
1217 	struct regulator_config config = {
1218 		.dev = pdev->dev.parent,
1219 		.regmap = axp20x->regmap,
1220 		.driver_data = axp20x,
1221 	};
1222 	int ret, i, nregulators;
1223 	u32 workmode;
1224 	const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1225 	const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1226 	bool drivevbus = false;
1227 
1228 	switch (axp20x->variant) {
1229 	case AXP202_ID:
1230 	case AXP209_ID:
1231 		regulators = axp20x_regulators;
1232 		nregulators = AXP20X_REG_ID_MAX;
1233 		break;
1234 	case AXP221_ID:
1235 	case AXP223_ID:
1236 		regulators = axp22x_regulators;
1237 		nregulators = AXP22X_REG_ID_MAX;
1238 		drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1239 						  "x-powers,drive-vbus-en");
1240 		break;
1241 	case AXP803_ID:
1242 		regulators = axp803_regulators;
1243 		nregulators = AXP803_REG_ID_MAX;
1244 		drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1245 						  "x-powers,drive-vbus-en");
1246 		break;
1247 	case AXP806_ID:
1248 		regulators = axp806_regulators;
1249 		nregulators = AXP806_REG_ID_MAX;
1250 		break;
1251 	case AXP809_ID:
1252 		regulators = axp809_regulators;
1253 		nregulators = AXP809_REG_ID_MAX;
1254 		break;
1255 	case AXP813_ID:
1256 		regulators = axp813_regulators;
1257 		nregulators = AXP813_REG_ID_MAX;
1258 		drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1259 						  "x-powers,drive-vbus-en");
1260 		break;
1261 	default:
1262 		dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1263 			axp20x->variant);
1264 		return -EINVAL;
1265 	}
1266 
1267 	/* This only sets the dcdc freq. Ignore any errors */
1268 	axp20x_regulator_parse_dt(pdev);
1269 
1270 	for (i = 0; i < nregulators; i++) {
1271 		const struct regulator_desc *desc = &regulators[i];
1272 		struct regulator_desc *new_desc;
1273 
1274 		/*
1275 		 * If this regulator is a slave in a poly-phase setup,
1276 		 * skip it, as its controls are bound to the master
1277 		 * regulator and won't work.
1278 		 */
1279 		if (axp20x_is_polyphase_slave(axp20x, i))
1280 			continue;
1281 
1282 		/* Support for AXP813's FLDO3 is not implemented */
1283 		if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1284 			continue;
1285 
1286 		/*
1287 		 * Regulators DC1SW and DC5LDO are connected internally,
1288 		 * so we have to handle their supply names separately.
1289 		 *
1290 		 * We always register the regulators in proper sequence,
1291 		 * so the supply names are correctly read. See the last
1292 		 * part of this loop to see where we save the DT defined
1293 		 * name.
1294 		 */
1295 		if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1296 		    (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1297 		    (regulators == axp809_regulators && i == AXP809_DC1SW)) {
1298 			new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1299 						GFP_KERNEL);
1300 			if (!new_desc)
1301 				return -ENOMEM;
1302 
1303 			*new_desc = regulators[i];
1304 			new_desc->supply_name = dcdc1_name;
1305 			desc = new_desc;
1306 		}
1307 
1308 		if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1309 		    (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
1310 			new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1311 						GFP_KERNEL);
1312 			if (!new_desc)
1313 				return -ENOMEM;
1314 
1315 			*new_desc = regulators[i];
1316 			new_desc->supply_name = dcdc5_name;
1317 			desc = new_desc;
1318 		}
1319 
1320 		rdev = devm_regulator_register(&pdev->dev, desc, &config);
1321 		if (IS_ERR(rdev)) {
1322 			dev_err(&pdev->dev, "Failed to register %s\n",
1323 				regulators[i].name);
1324 
1325 			return PTR_ERR(rdev);
1326 		}
1327 
1328 		ret = of_property_read_u32(rdev->dev.of_node,
1329 					   "x-powers,dcdc-workmode",
1330 					   &workmode);
1331 		if (!ret) {
1332 			if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1333 				dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1334 					rdev->desc->name);
1335 		}
1336 
1337 		/*
1338 		 * Save AXP22X DCDC1 / DCDC5 regulator names for later.
1339 		 */
1340 		if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1341 		    (regulators == axp809_regulators && i == AXP809_DCDC1))
1342 			of_property_read_string(rdev->dev.of_node,
1343 						"regulator-name",
1344 						&dcdc1_name);
1345 
1346 		if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1347 		    (regulators == axp809_regulators && i == AXP809_DCDC5))
1348 			of_property_read_string(rdev->dev.of_node,
1349 						"regulator-name",
1350 						&dcdc5_name);
1351 	}
1352 
1353 	if (drivevbus) {
1354 		/* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1355 		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1356 				   AXP22X_MISC_N_VBUSEN_FUNC, 0);
1357 		rdev = devm_regulator_register(&pdev->dev,
1358 					       &axp22x_drivevbus_regulator,
1359 					       &config);
1360 		if (IS_ERR(rdev)) {
1361 			dev_err(&pdev->dev, "Failed to register drivevbus\n");
1362 			return PTR_ERR(rdev);
1363 		}
1364 	}
1365 
1366 	return 0;
1367 }
1368 
1369 static struct platform_driver axp20x_regulator_driver = {
1370 	.probe	= axp20x_regulator_probe,
1371 	.driver	= {
1372 		.name		= "axp20x-regulator",
1373 	},
1374 };
1375 
1376 module_platform_driver(axp20x_regulator_driver);
1377 
1378 MODULE_LICENSE("GPL v2");
1379 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1380 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1381 MODULE_ALIAS("platform:axp20x-regulator");
1382