1 /* 2 * AXP20x regulators driver. 3 * 4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General 7 * Public License. See the file "COPYING" in the main directory of this 8 * archive for more details. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/mfd/axp20x.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/regulator/machine.h> 28 #include <linux/regulator/of_regulator.h> 29 30 #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0) 31 #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0) 32 33 #define AXP20X_IO_ENABLED 0x03 34 #define AXP20X_IO_DISABLED 0x07 35 36 #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2) 37 #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1) 38 39 #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0) 40 41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2) 42 43 #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0) 44 #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0) 45 #define AXP20X_LDO24_V_OUT_MASK GENMASK(7, 4) 46 #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0) 47 #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4) 48 49 #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0) 50 #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1) 51 #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2) 52 #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3) 53 #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4) 54 #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6) 55 56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0) 57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \ 58 ((x) << 0) 59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1) 60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \ 61 ((x) << 1) 62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2) 63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2) 64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3) 65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3) 66 67 #define AXP20X_LDO4_V_OUT_1250mV_START 0x0 68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0 69 #define AXP20X_LDO4_V_OUT_1250mV_END \ 70 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS) 71 #define AXP20X_LDO4_V_OUT_1300mV_START 0x1 72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7 73 #define AXP20X_LDO4_V_OUT_1300mV_END \ 74 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS) 75 #define AXP20X_LDO4_V_OUT_2500mV_START 0x9 76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0 77 #define AXP20X_LDO4_V_OUT_2500mV_END \ 78 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS) 79 #define AXP20X_LDO4_V_OUT_2700mV_START 0xa 80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1 81 #define AXP20X_LDO4_V_OUT_2700mV_END \ 82 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS) 83 #define AXP20X_LDO4_V_OUT_3000mV_START 0xc 84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3 85 #define AXP20X_LDO4_V_OUT_3000mV_END \ 86 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS) 87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16 88 89 #define AXP22X_IO_ENABLED 0x03 90 #define AXP22X_IO_DISABLED 0x04 91 92 #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x) 93 94 #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) 95 96 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0) 97 #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0) 98 #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0) 99 #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0) 100 #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0) 101 #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0) 102 #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0) 103 #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0) 104 #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0) 105 #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0) 106 #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0) 107 #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0) 108 #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0) 109 #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0) 110 #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0) 111 #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0) 112 #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0) 113 #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0) 114 115 #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0) 116 #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1) 117 #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2) 118 #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3) 119 #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4) 120 #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5) 121 #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6) 122 #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7) 123 124 #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6) 125 #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7) 126 127 #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0) 128 #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1) 129 #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2) 130 #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3) 131 #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4) 132 #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5) 133 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6) 134 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7) 135 136 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) 137 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) 138 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) 139 #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3) 140 #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4) 141 #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5) 142 143 #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2) 144 #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3) 145 146 #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0) 147 #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0) 148 #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0) 149 #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0) 150 #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0) 151 #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0) 152 153 #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0) 154 #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0) 155 156 #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6) 157 #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5) 158 159 #define AXP803_DCDC234_500mV_START 0x00 160 #define AXP803_DCDC234_500mV_STEPS 70 161 #define AXP803_DCDC234_500mV_END \ 162 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS) 163 #define AXP803_DCDC234_1220mV_START 0x47 164 #define AXP803_DCDC234_1220mV_STEPS 4 165 #define AXP803_DCDC234_1220mV_END \ 166 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS) 167 #define AXP803_DCDC234_NUM_VOLTAGES 76 168 169 #define AXP803_DCDC5_800mV_START 0x00 170 #define AXP803_DCDC5_800mV_STEPS 32 171 #define AXP803_DCDC5_800mV_END \ 172 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS) 173 #define AXP803_DCDC5_1140mV_START 0x21 174 #define AXP803_DCDC5_1140mV_STEPS 35 175 #define AXP803_DCDC5_1140mV_END \ 176 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS) 177 #define AXP803_DCDC5_NUM_VOLTAGES 68 178 179 #define AXP803_DCDC6_600mV_START 0x00 180 #define AXP803_DCDC6_600mV_STEPS 50 181 #define AXP803_DCDC6_600mV_END \ 182 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS) 183 #define AXP803_DCDC6_1120mV_START 0x33 184 #define AXP803_DCDC6_1120mV_STEPS 14 185 #define AXP803_DCDC6_1120mV_END \ 186 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) 187 #define AXP803_DCDC6_NUM_VOLTAGES 72 188 189 #define AXP803_DLDO2_700mV_START 0x00 190 #define AXP803_DLDO2_700mV_STEPS 26 191 #define AXP803_DLDO2_700mV_END \ 192 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS) 193 #define AXP803_DLDO2_3400mV_START 0x1b 194 #define AXP803_DLDO2_3400mV_STEPS 4 195 #define AXP803_DLDO2_3400mV_END \ 196 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS) 197 #define AXP803_DLDO2_NUM_VOLTAGES 32 198 199 #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0) 200 #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0) 201 #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0) 202 #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0) 203 #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0) 204 #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0) 205 #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0) 206 #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0) 207 #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0) 208 #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0) 209 #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0) 210 #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0) 211 #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0) 212 #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0) 213 #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0) 214 215 #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0) 216 #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1) 217 #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2) 218 #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3) 219 #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4) 220 #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5) 221 #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6) 222 #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7) 223 #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0) 224 #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1) 225 #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2) 226 #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3) 227 #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4) 228 #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5) 229 #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6) 230 #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7) 231 232 #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40 233 #define AXP806_DCDCABC_POLYPHASE_TRI 0x80 234 #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6) 235 236 #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5) 237 238 #define AXP806_DCDCA_600mV_START 0x00 239 #define AXP806_DCDCA_600mV_STEPS 50 240 #define AXP806_DCDCA_600mV_END \ 241 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS) 242 #define AXP806_DCDCA_1120mV_START 0x33 243 #define AXP806_DCDCA_1120mV_STEPS 14 244 #define AXP806_DCDCA_1120mV_END \ 245 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS) 246 #define AXP806_DCDCA_NUM_VOLTAGES 72 247 248 #define AXP806_DCDCD_600mV_START 0x00 249 #define AXP806_DCDCD_600mV_STEPS 45 250 #define AXP806_DCDCD_600mV_END \ 251 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS) 252 #define AXP806_DCDCD_1600mV_START 0x2e 253 #define AXP806_DCDCD_1600mV_STEPS 17 254 #define AXP806_DCDCD_1600mV_END \ 255 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS) 256 #define AXP806_DCDCD_NUM_VOLTAGES 64 257 258 #define AXP809_DCDC4_600mV_START 0x00 259 #define AXP809_DCDC4_600mV_STEPS 47 260 #define AXP809_DCDC4_600mV_END \ 261 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS) 262 #define AXP809_DCDC4_1800mV_START 0x30 263 #define AXP809_DCDC4_1800mV_STEPS 8 264 #define AXP809_DCDC4_1800mV_END \ 265 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS) 266 #define AXP809_DCDC4_NUM_VOLTAGES 57 267 268 #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0) 269 270 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6) 271 272 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 273 _vmask, _ereg, _emask, _enable_val, _disable_val) \ 274 [_family##_##_id] = { \ 275 .name = (_match), \ 276 .supply_name = (_supply), \ 277 .of_match = of_match_ptr(_match), \ 278 .regulators_node = of_match_ptr("regulators"), \ 279 .type = REGULATOR_VOLTAGE, \ 280 .id = _family##_##_id, \ 281 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 282 .owner = THIS_MODULE, \ 283 .min_uV = (_min) * 1000, \ 284 .uV_step = (_step) * 1000, \ 285 .vsel_reg = (_vreg), \ 286 .vsel_mask = (_vmask), \ 287 .enable_reg = (_ereg), \ 288 .enable_mask = (_emask), \ 289 .enable_val = (_enable_val), \ 290 .disable_val = (_disable_val), \ 291 .ops = &axp20x_ops, \ 292 } 293 294 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 295 _vmask, _ereg, _emask) \ 296 [_family##_##_id] = { \ 297 .name = (_match), \ 298 .supply_name = (_supply), \ 299 .of_match = of_match_ptr(_match), \ 300 .regulators_node = of_match_ptr("regulators"), \ 301 .type = REGULATOR_VOLTAGE, \ 302 .id = _family##_##_id, \ 303 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 304 .owner = THIS_MODULE, \ 305 .min_uV = (_min) * 1000, \ 306 .uV_step = (_step) * 1000, \ 307 .vsel_reg = (_vreg), \ 308 .vsel_mask = (_vmask), \ 309 .enable_reg = (_ereg), \ 310 .enable_mask = (_emask), \ 311 .ops = &axp20x_ops, \ 312 } 313 314 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ 315 [_family##_##_id] = { \ 316 .name = (_match), \ 317 .supply_name = (_supply), \ 318 .of_match = of_match_ptr(_match), \ 319 .regulators_node = of_match_ptr("regulators"), \ 320 .type = REGULATOR_VOLTAGE, \ 321 .id = _family##_##_id, \ 322 .owner = THIS_MODULE, \ 323 .enable_reg = (_ereg), \ 324 .enable_mask = (_emask), \ 325 .ops = &axp20x_ops_sw, \ 326 } 327 328 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ 329 [_family##_##_id] = { \ 330 .name = (_match), \ 331 .supply_name = (_supply), \ 332 .of_match = of_match_ptr(_match), \ 333 .regulators_node = of_match_ptr("regulators"), \ 334 .type = REGULATOR_VOLTAGE, \ 335 .id = _family##_##_id, \ 336 .n_voltages = 1, \ 337 .owner = THIS_MODULE, \ 338 .min_uV = (_volt) * 1000, \ 339 .ops = &axp20x_ops_fixed \ 340 } 341 342 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ 343 _vreg, _vmask, _ereg, _emask) \ 344 [_family##_##_id] = { \ 345 .name = (_match), \ 346 .supply_name = (_supply), \ 347 .of_match = of_match_ptr(_match), \ 348 .regulators_node = of_match_ptr("regulators"), \ 349 .type = REGULATOR_VOLTAGE, \ 350 .id = _family##_##_id, \ 351 .n_voltages = (_n_voltages), \ 352 .owner = THIS_MODULE, \ 353 .vsel_reg = (_vreg), \ 354 .vsel_mask = (_vmask), \ 355 .enable_reg = (_ereg), \ 356 .enable_mask = (_emask), \ 357 .linear_ranges = (_ranges), \ 358 .n_linear_ranges = ARRAY_SIZE(_ranges), \ 359 .ops = &axp20x_ops_range, \ 360 } 361 362 static const int axp209_dcdc2_ldo3_slew_rates[] = { 363 1600, 364 800, 365 }; 366 367 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) 368 { 369 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 370 const struct regulator_desc *desc = rdev->desc; 371 u8 reg, mask, enable, cfg = 0xff; 372 const int *slew_rates; 373 int rate_count = 0; 374 375 if (!rdev) 376 return -EINVAL; 377 378 switch (axp20x->variant) { 379 case AXP209_ID: 380 if (desc->id == AXP20X_DCDC2) { 381 slew_rates = axp209_dcdc2_ldo3_slew_rates; 382 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 383 reg = AXP20X_DCDC2_LDO3_V_RAMP; 384 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | 385 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; 386 enable = (ramp > 0) ? 387 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 388 !AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN; 389 break; 390 } 391 392 if (desc->id == AXP20X_LDO3) { 393 slew_rates = axp209_dcdc2_ldo3_slew_rates; 394 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 395 reg = AXP20X_DCDC2_LDO3_V_RAMP; 396 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | 397 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; 398 enable = (ramp > 0) ? 399 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 400 !AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN; 401 break; 402 } 403 404 if (rate_count > 0) 405 break; 406 407 /* fall through */ 408 default: 409 /* Not supported for this regulator */ 410 return -ENOTSUPP; 411 } 412 413 if (ramp == 0) { 414 cfg = enable; 415 } else { 416 int i; 417 418 for (i = 0; i < rate_count; i++) { 419 if (ramp <= slew_rates[i]) 420 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i); 421 else 422 break; 423 } 424 425 if (cfg == 0xff) { 426 dev_err(axp20x->dev, "unsupported ramp value %d", ramp); 427 return -EINVAL; 428 } 429 430 cfg |= enable; 431 } 432 433 return regmap_update_bits(axp20x->regmap, reg, mask, cfg); 434 } 435 436 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) 437 { 438 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 439 const struct regulator_desc *desc = rdev->desc; 440 441 if (!rdev) 442 return -EINVAL; 443 444 switch (axp20x->variant) { 445 case AXP209_ID: 446 if ((desc->id == AXP20X_LDO3) && 447 rdev->constraints && rdev->constraints->soft_start) { 448 int v_out; 449 int ret; 450 451 /* 452 * On some boards, the LDO3 can be overloaded when 453 * turning on, causing the entire PMIC to shutdown 454 * without warning. Turning it on at the minimal voltage 455 * and then setting the voltage to the requested value 456 * works reliably. 457 */ 458 if (regulator_is_enabled_regmap(rdev)) 459 break; 460 461 v_out = regulator_get_voltage_sel_regmap(rdev); 462 if (v_out < 0) 463 return v_out; 464 465 if (v_out == 0) 466 break; 467 468 ret = regulator_set_voltage_sel_regmap(rdev, 0x00); 469 /* 470 * A small pause is needed between 471 * setting the voltage and enabling the LDO to give the 472 * internal state machine time to process the request. 473 */ 474 usleep_range(1000, 5000); 475 ret |= regulator_enable_regmap(rdev); 476 ret |= regulator_set_voltage_sel_regmap(rdev, v_out); 477 478 return ret; 479 } 480 break; 481 default: 482 /* No quirks */ 483 break; 484 } 485 486 return regulator_enable_regmap(rdev); 487 }; 488 489 static const struct regulator_ops axp20x_ops_fixed = { 490 .list_voltage = regulator_list_voltage_linear, 491 }; 492 493 static const struct regulator_ops axp20x_ops_range = { 494 .set_voltage_sel = regulator_set_voltage_sel_regmap, 495 .get_voltage_sel = regulator_get_voltage_sel_regmap, 496 .list_voltage = regulator_list_voltage_linear_range, 497 .enable = regulator_enable_regmap, 498 .disable = regulator_disable_regmap, 499 .is_enabled = regulator_is_enabled_regmap, 500 }; 501 502 static const struct regulator_ops axp20x_ops = { 503 .set_voltage_sel = regulator_set_voltage_sel_regmap, 504 .get_voltage_sel = regulator_get_voltage_sel_regmap, 505 .list_voltage = regulator_list_voltage_linear, 506 .enable = axp20x_regulator_enable_regmap, 507 .disable = regulator_disable_regmap, 508 .is_enabled = regulator_is_enabled_regmap, 509 .set_ramp_delay = axp20x_set_ramp_delay, 510 }; 511 512 static const struct regulator_ops axp20x_ops_sw = { 513 .enable = regulator_enable_regmap, 514 .disable = regulator_disable_regmap, 515 .is_enabled = regulator_is_enabled_regmap, 516 }; 517 518 static const struct regulator_linear_range axp20x_ldo4_ranges[] = { 519 REGULATOR_LINEAR_RANGE(1250000, 520 AXP20X_LDO4_V_OUT_1250mV_START, 521 AXP20X_LDO4_V_OUT_1250mV_END, 522 0), 523 REGULATOR_LINEAR_RANGE(1300000, 524 AXP20X_LDO4_V_OUT_1300mV_START, 525 AXP20X_LDO4_V_OUT_1300mV_END, 526 100000), 527 REGULATOR_LINEAR_RANGE(2500000, 528 AXP20X_LDO4_V_OUT_2500mV_START, 529 AXP20X_LDO4_V_OUT_2500mV_END, 530 0), 531 REGULATOR_LINEAR_RANGE(2700000, 532 AXP20X_LDO4_V_OUT_2700mV_START, 533 AXP20X_LDO4_V_OUT_2700mV_END, 534 100000), 535 REGULATOR_LINEAR_RANGE(3000000, 536 AXP20X_LDO4_V_OUT_3000mV_START, 537 AXP20X_LDO4_V_OUT_3000mV_END, 538 100000), 539 }; 540 541 static const struct regulator_desc axp20x_regulators[] = { 542 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, 543 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK, 544 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK), 545 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, 546 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK, 547 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK), 548 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), 549 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, 550 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK, 551 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK), 552 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, 553 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK, 554 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK), 555 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", 556 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES, 557 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK, 558 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK), 559 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, 560 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK, 561 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 562 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), 563 }; 564 565 static const struct regulator_desc axp22x_regulators[] = { 566 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 567 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 568 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 569 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 570 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 571 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 572 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 573 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 574 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 575 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, 576 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT, 577 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 578 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 579 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 580 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 581 /* secondary switchable output of DCDC1 */ 582 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, 583 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 584 /* LDO regulator internally chained to DCDC5 */ 585 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 586 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 587 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 588 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 589 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 590 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 591 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 592 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 593 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 594 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 595 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 596 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK), 597 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 598 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 599 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 600 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 601 AXP22X_DLDO2_V_OUT, AXP22X_PWR_OUT_DLDO2_MASK, 602 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 603 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 604 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 605 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 606 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 607 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 608 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 609 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 610 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 611 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 612 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 613 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 614 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 615 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 616 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 617 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 618 /* Note the datasheet only guarantees reliable operation up to 619 * 3.3V, this needs to be enforced via dts provided constraints */ 620 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 621 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 622 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 623 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 624 /* Note the datasheet only guarantees reliable operation up to 625 * 3.3V, this needs to be enforced via dts provided constraints */ 626 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 627 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 628 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 629 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 630 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), 631 }; 632 633 static const struct regulator_desc axp22x_drivevbus_regulator = { 634 .name = "drivevbus", 635 .supply_name = "drivevbus", 636 .of_match = of_match_ptr("drivevbus"), 637 .regulators_node = of_match_ptr("regulators"), 638 .type = REGULATOR_VOLTAGE, 639 .owner = THIS_MODULE, 640 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT, 641 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK, 642 .ops = &axp20x_ops_sw, 643 }; 644 645 /* DCDC ranges shared with AXP813 */ 646 static const struct regulator_linear_range axp803_dcdc234_ranges[] = { 647 REGULATOR_LINEAR_RANGE(500000, 648 AXP803_DCDC234_500mV_START, 649 AXP803_DCDC234_500mV_END, 650 10000), 651 REGULATOR_LINEAR_RANGE(1220000, 652 AXP803_DCDC234_1220mV_START, 653 AXP803_DCDC234_1220mV_END, 654 20000), 655 }; 656 657 static const struct regulator_linear_range axp803_dcdc5_ranges[] = { 658 REGULATOR_LINEAR_RANGE(800000, 659 AXP803_DCDC5_800mV_START, 660 AXP803_DCDC5_800mV_END, 661 10000), 662 REGULATOR_LINEAR_RANGE(1140000, 663 AXP803_DCDC5_1140mV_START, 664 AXP803_DCDC5_1140mV_END, 665 20000), 666 }; 667 668 static const struct regulator_linear_range axp803_dcdc6_ranges[] = { 669 REGULATOR_LINEAR_RANGE(600000, 670 AXP803_DCDC6_600mV_START, 671 AXP803_DCDC6_600mV_END, 672 10000), 673 REGULATOR_LINEAR_RANGE(1120000, 674 AXP803_DCDC6_1120mV_START, 675 AXP803_DCDC6_1120mV_END, 676 20000), 677 }; 678 679 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */ 680 static const struct regulator_linear_range axp803_dldo2_ranges[] = { 681 REGULATOR_LINEAR_RANGE(700000, 682 AXP803_DLDO2_700mV_START, 683 AXP803_DLDO2_700mV_END, 684 100000), 685 REGULATOR_LINEAR_RANGE(3400000, 686 AXP803_DLDO2_3400mV_START, 687 AXP803_DLDO2_3400mV_END, 688 200000), 689 }; 690 691 static const struct regulator_desc axp803_regulators[] = { 692 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 693 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 694 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 695 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", 696 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 697 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 698 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 699 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", 700 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 701 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 702 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 703 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", 704 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 705 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 706 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 707 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", 708 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 709 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 710 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 711 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", 712 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 713 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 714 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 715 /* secondary switchable output of DCDC1 */ 716 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, 717 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 718 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 719 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 720 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 721 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 722 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT, 723 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 724 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 725 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 726 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 727 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 728 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 729 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 730 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", 731 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 732 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT, 733 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 734 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 735 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 736 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 737 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 738 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 739 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 740 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 741 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 742 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 743 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 744 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 745 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 746 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 747 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT, 748 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 749 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 750 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 751 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 752 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 753 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 754 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 755 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 756 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 757 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 758 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 759 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 760 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 761 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 762 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 763 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000), 764 }; 765 766 static const struct regulator_linear_range axp806_dcdca_ranges[] = { 767 REGULATOR_LINEAR_RANGE(600000, 768 AXP806_DCDCA_600mV_START, 769 AXP806_DCDCA_600mV_END, 770 10000), 771 REGULATOR_LINEAR_RANGE(1120000, 772 AXP806_DCDCA_1120mV_START, 773 AXP806_DCDCA_1120mV_END, 774 20000), 775 }; 776 777 static const struct regulator_linear_range axp806_dcdcd_ranges[] = { 778 REGULATOR_LINEAR_RANGE(600000, 779 AXP806_DCDCD_600mV_START, 780 AXP806_DCDCD_600mV_END, 781 20000), 782 REGULATOR_LINEAR_RANGE(1600000, 783 AXP806_DCDCD_600mV_START, 784 AXP806_DCDCD_600mV_END, 785 100000), 786 }; 787 788 static const struct regulator_desc axp806_regulators[] = { 789 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", 790 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 791 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, 792 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), 793 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, 794 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL, 795 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), 796 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", 797 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 798 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK, 799 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK), 800 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", 801 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES, 802 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK, 803 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK), 804 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100, 805 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK, 806 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK), 807 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 808 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK, 809 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK), 810 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100, 811 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK, 812 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK), 813 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 814 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK, 815 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK), 816 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100, 817 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, 818 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), 819 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, 820 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL, 821 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), 822 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, 823 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, 824 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK), 825 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100, 826 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK, 827 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK), 828 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 829 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK, 830 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK), 831 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", 832 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 833 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK, 834 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK), 835 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100, 836 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK, 837 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK), 838 AXP_DESC_SW(AXP806, SW, "sw", "swin", 839 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK), 840 }; 841 842 static const struct regulator_linear_range axp809_dcdc4_ranges[] = { 843 REGULATOR_LINEAR_RANGE(600000, 844 AXP809_DCDC4_600mV_START, 845 AXP809_DCDC4_600mV_END, 846 20000), 847 REGULATOR_LINEAR_RANGE(1800000, 848 AXP809_DCDC4_1800mV_START, 849 AXP809_DCDC4_1800mV_END, 850 100000), 851 }; 852 853 static const struct regulator_desc axp809_regulators[] = { 854 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 855 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 856 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 857 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 858 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 859 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 860 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 861 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 862 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 863 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", 864 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES, 865 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 866 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 867 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 868 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 869 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 870 /* secondary switchable output of DCDC1 */ 871 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, 872 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 873 /* LDO regulator internally chained to DCDC5 */ 874 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 875 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 876 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 877 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 878 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 879 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 880 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 881 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 882 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 883 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 884 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 885 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK), 886 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", 887 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 888 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 889 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 890 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 891 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 892 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 893 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 894 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 895 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 896 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 897 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 898 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 899 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 900 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 901 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 902 /* 903 * Note the datasheet only guarantees reliable operation up to 904 * 3.3V, this needs to be enforced via dts provided constraints 905 */ 906 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 907 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 908 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 909 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 910 /* 911 * Note the datasheet only guarantees reliable operation up to 912 * 3.3V, this needs to be enforced via dts provided constraints 913 */ 914 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 915 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 916 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 917 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 918 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), 919 AXP_DESC_SW(AXP809, SW, "sw", "swin", 920 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK), 921 }; 922 923 static const struct regulator_desc axp813_regulators[] = { 924 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 925 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 926 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 927 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2", 928 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 929 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 930 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 931 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3", 932 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 933 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 934 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 935 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4", 936 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 937 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 938 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 939 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5", 940 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 941 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 942 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 943 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6", 944 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 945 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 946 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 947 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7", 948 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 949 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK, 950 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK), 951 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 952 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 953 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 954 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 955 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT, 956 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 957 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 958 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 959 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 960 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 961 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 962 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 963 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", 964 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 965 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT, 966 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 967 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 968 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 969 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 970 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 971 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 972 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 973 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 974 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 975 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 976 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 977 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 978 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 979 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 980 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT, 981 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 982 /* to do / check ... */ 983 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 984 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 985 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 986 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 987 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 988 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 989 /* 990 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2 991 * 992 * This means FLDO3 effectively switches supplies at runtime, 993 * something the regulator subsystem does not support. 994 */ 995 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800), 996 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 997 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 998 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 999 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1000 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 1001 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 1002 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 1003 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1004 AXP_DESC_SW(AXP813, SW, "sw", "swin", 1005 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 1006 }; 1007 1008 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) 1009 { 1010 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1011 unsigned int reg = AXP20X_DCDC_FREQ; 1012 u32 min, max, def, step; 1013 1014 switch (axp20x->variant) { 1015 case AXP202_ID: 1016 case AXP209_ID: 1017 min = 750; 1018 max = 1875; 1019 def = 1500; 1020 step = 75; 1021 break; 1022 case AXP803_ID: 1023 case AXP813_ID: 1024 /* 1025 * AXP803/AXP813 DCDC work frequency setting has the same 1026 * range and step as AXP22X, but at a different register. 1027 * (See include/linux/mfd/axp20x.h) 1028 */ 1029 reg = AXP803_DCDC_FREQ_CTRL; 1030 /* Fall through to the check below.*/ 1031 case AXP806_ID: 1032 /* 1033 * AXP806 also have DCDC work frequency setting register at a 1034 * different position. 1035 */ 1036 if (axp20x->variant == AXP806_ID) 1037 reg = AXP806_DCDC_FREQ_CTRL; 1038 /* Fall through */ 1039 case AXP221_ID: 1040 case AXP223_ID: 1041 case AXP809_ID: 1042 min = 1800; 1043 max = 4050; 1044 def = 3000; 1045 step = 150; 1046 break; 1047 default: 1048 dev_err(&pdev->dev, 1049 "Setting DCDC frequency for unsupported AXP variant\n"); 1050 return -EINVAL; 1051 } 1052 1053 if (dcdcfreq == 0) 1054 dcdcfreq = def; 1055 1056 if (dcdcfreq < min) { 1057 dcdcfreq = min; 1058 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", 1059 min); 1060 } 1061 1062 if (dcdcfreq > max) { 1063 dcdcfreq = max; 1064 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", 1065 max); 1066 } 1067 1068 dcdcfreq = (dcdcfreq - min) / step; 1069 1070 return regmap_update_bits(axp20x->regmap, reg, 1071 AXP20X_FREQ_DCDC_MASK, dcdcfreq); 1072 } 1073 1074 static int axp20x_regulator_parse_dt(struct platform_device *pdev) 1075 { 1076 struct device_node *np, *regulators; 1077 int ret; 1078 u32 dcdcfreq = 0; 1079 1080 np = of_node_get(pdev->dev.parent->of_node); 1081 if (!np) 1082 return 0; 1083 1084 regulators = of_get_child_by_name(np, "regulators"); 1085 if (!regulators) { 1086 dev_warn(&pdev->dev, "regulators node not found\n"); 1087 } else { 1088 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); 1089 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); 1090 if (ret < 0) { 1091 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); 1092 return ret; 1093 } 1094 1095 of_node_put(regulators); 1096 } 1097 1098 return 0; 1099 } 1100 1101 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) 1102 { 1103 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 1104 unsigned int reg = AXP20X_DCDC_MODE; 1105 unsigned int mask; 1106 1107 switch (axp20x->variant) { 1108 case AXP202_ID: 1109 case AXP209_ID: 1110 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) 1111 return -EINVAL; 1112 1113 mask = AXP20X_WORKMODE_DCDC2_MASK; 1114 if (id == AXP20X_DCDC3) 1115 mask = AXP20X_WORKMODE_DCDC3_MASK; 1116 1117 workmode <<= ffs(mask) - 1; 1118 break; 1119 1120 case AXP806_ID: 1121 reg = AXP806_DCDC_MODE_CTRL2; 1122 /* 1123 * AXP806 DCDC regulator IDs have the same range as AXP22X. 1124 * Fall through to the check below. 1125 * (See include/linux/mfd/axp20x.h) 1126 */ 1127 case AXP221_ID: 1128 case AXP223_ID: 1129 case AXP809_ID: 1130 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) 1131 return -EINVAL; 1132 1133 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); 1134 workmode <<= id - AXP22X_DCDC1; 1135 break; 1136 1137 case AXP803_ID: 1138 if (id < AXP803_DCDC1 || id > AXP803_DCDC6) 1139 return -EINVAL; 1140 1141 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); 1142 workmode <<= id - AXP803_DCDC1; 1143 break; 1144 1145 case AXP813_ID: 1146 if (id < AXP813_DCDC1 || id > AXP813_DCDC7) 1147 return -EINVAL; 1148 1149 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1); 1150 workmode <<= id - AXP813_DCDC1; 1151 break; 1152 1153 default: 1154 /* should not happen */ 1155 WARN_ON(1); 1156 return -EINVAL; 1157 } 1158 1159 return regmap_update_bits(rdev->regmap, reg, mask, workmode); 1160 } 1161 1162 /* 1163 * This function checks whether a regulator is part of a poly-phase 1164 * output setup based on the registers settings. Returns true if it is. 1165 */ 1166 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id) 1167 { 1168 u32 reg = 0; 1169 1170 /* 1171 * Currently in our supported AXP variants, only AXP803, AXP806, 1172 * and AXP813 have polyphase regulators. 1173 */ 1174 switch (axp20x->variant) { 1175 case AXP803_ID: 1176 case AXP813_ID: 1177 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); 1178 1179 switch (id) { 1180 case AXP803_DCDC3: 1181 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); 1182 case AXP803_DCDC6: 1183 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); 1184 } 1185 break; 1186 1187 case AXP806_ID: 1188 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); 1189 1190 switch (id) { 1191 case AXP806_DCDCB: 1192 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1193 AXP806_DCDCAB_POLYPHASE_DUAL) || 1194 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1195 AXP806_DCDCABC_POLYPHASE_TRI)); 1196 case AXP806_DCDCC: 1197 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1198 AXP806_DCDCABC_POLYPHASE_TRI); 1199 case AXP806_DCDCE: 1200 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); 1201 } 1202 break; 1203 1204 default: 1205 return false; 1206 } 1207 1208 return false; 1209 } 1210 1211 static int axp20x_regulator_probe(struct platform_device *pdev) 1212 { 1213 struct regulator_dev *rdev; 1214 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1215 const struct regulator_desc *regulators; 1216 struct regulator_config config = { 1217 .dev = pdev->dev.parent, 1218 .regmap = axp20x->regmap, 1219 .driver_data = axp20x, 1220 }; 1221 int ret, i, nregulators; 1222 u32 workmode; 1223 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name; 1224 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name; 1225 bool drivevbus = false; 1226 1227 switch (axp20x->variant) { 1228 case AXP202_ID: 1229 case AXP209_ID: 1230 regulators = axp20x_regulators; 1231 nregulators = AXP20X_REG_ID_MAX; 1232 break; 1233 case AXP221_ID: 1234 case AXP223_ID: 1235 regulators = axp22x_regulators; 1236 nregulators = AXP22X_REG_ID_MAX; 1237 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1238 "x-powers,drive-vbus-en"); 1239 break; 1240 case AXP803_ID: 1241 regulators = axp803_regulators; 1242 nregulators = AXP803_REG_ID_MAX; 1243 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1244 "x-powers,drive-vbus-en"); 1245 break; 1246 case AXP806_ID: 1247 regulators = axp806_regulators; 1248 nregulators = AXP806_REG_ID_MAX; 1249 break; 1250 case AXP809_ID: 1251 regulators = axp809_regulators; 1252 nregulators = AXP809_REG_ID_MAX; 1253 break; 1254 case AXP813_ID: 1255 regulators = axp813_regulators; 1256 nregulators = AXP813_REG_ID_MAX; 1257 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1258 "x-powers,drive-vbus-en"); 1259 break; 1260 default: 1261 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n", 1262 axp20x->variant); 1263 return -EINVAL; 1264 } 1265 1266 /* This only sets the dcdc freq. Ignore any errors */ 1267 axp20x_regulator_parse_dt(pdev); 1268 1269 for (i = 0; i < nregulators; i++) { 1270 const struct regulator_desc *desc = ®ulators[i]; 1271 struct regulator_desc *new_desc; 1272 1273 /* 1274 * If this regulator is a slave in a poly-phase setup, 1275 * skip it, as its controls are bound to the master 1276 * regulator and won't work. 1277 */ 1278 if (axp20x_is_polyphase_slave(axp20x, i)) 1279 continue; 1280 1281 /* Support for AXP813's FLDO3 is not implemented */ 1282 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3) 1283 continue; 1284 1285 /* 1286 * Regulators DC1SW and DC5LDO are connected internally, 1287 * so we have to handle their supply names separately. 1288 * 1289 * We always register the regulators in proper sequence, 1290 * so the supply names are correctly read. See the last 1291 * part of this loop to see where we save the DT defined 1292 * name. 1293 */ 1294 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || 1295 (regulators == axp803_regulators && i == AXP803_DC1SW) || 1296 (regulators == axp809_regulators && i == AXP809_DC1SW)) { 1297 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1298 GFP_KERNEL); 1299 if (!new_desc) 1300 return -ENOMEM; 1301 1302 *new_desc = regulators[i]; 1303 new_desc->supply_name = dcdc1_name; 1304 desc = new_desc; 1305 } 1306 1307 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) || 1308 (regulators == axp809_regulators && i == AXP809_DC5LDO)) { 1309 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1310 GFP_KERNEL); 1311 if (!new_desc) 1312 return -ENOMEM; 1313 1314 *new_desc = regulators[i]; 1315 new_desc->supply_name = dcdc5_name; 1316 desc = new_desc; 1317 } 1318 1319 rdev = devm_regulator_register(&pdev->dev, desc, &config); 1320 if (IS_ERR(rdev)) { 1321 dev_err(&pdev->dev, "Failed to register %s\n", 1322 regulators[i].name); 1323 1324 return PTR_ERR(rdev); 1325 } 1326 1327 ret = of_property_read_u32(rdev->dev.of_node, 1328 "x-powers,dcdc-workmode", 1329 &workmode); 1330 if (!ret) { 1331 if (axp20x_set_dcdc_workmode(rdev, i, workmode)) 1332 dev_err(&pdev->dev, "Failed to set workmode on %s\n", 1333 rdev->desc->name); 1334 } 1335 1336 /* 1337 * Save AXP22X DCDC1 / DCDC5 regulator names for later. 1338 */ 1339 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) || 1340 (regulators == axp809_regulators && i == AXP809_DCDC1)) 1341 of_property_read_string(rdev->dev.of_node, 1342 "regulator-name", 1343 &dcdc1_name); 1344 1345 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) || 1346 (regulators == axp809_regulators && i == AXP809_DCDC5)) 1347 of_property_read_string(rdev->dev.of_node, 1348 "regulator-name", 1349 &dcdc5_name); 1350 } 1351 1352 if (drivevbus) { 1353 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */ 1354 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP, 1355 AXP22X_MISC_N_VBUSEN_FUNC, 0); 1356 rdev = devm_regulator_register(&pdev->dev, 1357 &axp22x_drivevbus_regulator, 1358 &config); 1359 if (IS_ERR(rdev)) { 1360 dev_err(&pdev->dev, "Failed to register drivevbus\n"); 1361 return PTR_ERR(rdev); 1362 } 1363 } 1364 1365 return 0; 1366 } 1367 1368 static struct platform_driver axp20x_regulator_driver = { 1369 .probe = axp20x_regulator_probe, 1370 .driver = { 1371 .name = "axp20x-regulator", 1372 }, 1373 }; 1374 1375 module_platform_driver(axp20x_regulator_driver); 1376 1377 MODULE_LICENSE("GPL v2"); 1378 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 1379 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); 1380 MODULE_ALIAS("platform:axp20x-regulator"); 1381