1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License Terms: GNU General Public License v2 5 * 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson 7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson 9 * 10 * AB8500 peripheral regulators 11 * 12 * AB8500 supports the following regulators: 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 14 * 15 * AB8505 supports the following regulators: 16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 17 */ 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/err.h> 22 #include <linux/platform_device.h> 23 #include <linux/mfd/abx500.h> 24 #include <linux/mfd/abx500/ab8500.h> 25 #include <linux/of.h> 26 #include <linux/regulator/of_regulator.h> 27 #include <linux/regulator/driver.h> 28 #include <linux/regulator/machine.h> 29 #include <linux/regulator/ab8500.h> 30 #include <linux/slab.h> 31 32 /** 33 * struct ab8500_shared_mode - is used when mode is shared between 34 * two regulators. 35 * @shared_regulator: pointer to the other sharing regulator 36 * @lp_mode_req: low power mode requested by this regulator 37 */ 38 struct ab8500_shared_mode { 39 struct ab8500_regulator_info *shared_regulator; 40 bool lp_mode_req; 41 }; 42 43 /** 44 * struct ab8500_regulator_info - ab8500 regulator information 45 * @dev: device pointer 46 * @desc: regulator description 47 * @regulator_dev: regulator device 48 * @shared_mode: used when mode is shared between two regulators 49 * @load_lp_uA: maximum load in idle (low power) mode 50 * @update_bank: bank to control on/off 51 * @update_reg: register to control on/off 52 * @update_mask: mask to enable/disable and set mode of regulator 53 * @update_val: bits holding the regulator current mode 54 * @update_val_idle: bits to enable the regulator in idle (low power) mode 55 * @update_val_normal: bits to enable the regulator in normal (high power) mode 56 * @mode_bank: bank with location of mode register 57 * @mode_reg: mode register 58 * @mode_mask: mask for setting mode 59 * @mode_val_idle: mode setting for low power 60 * @mode_val_normal: mode setting for normal power 61 * @voltage_bank: bank to control regulator voltage 62 * @voltage_reg: register to control regulator voltage 63 * @voltage_mask: mask to control regulator voltage 64 */ 65 struct ab8500_regulator_info { 66 struct device *dev; 67 struct regulator_desc desc; 68 struct regulator_dev *regulator; 69 struct ab8500_shared_mode *shared_mode; 70 int load_lp_uA; 71 u8 update_bank; 72 u8 update_reg; 73 u8 update_mask; 74 u8 update_val; 75 u8 update_val_idle; 76 u8 update_val_normal; 77 u8 mode_bank; 78 u8 mode_reg; 79 u8 mode_mask; 80 u8 mode_val_idle; 81 u8 mode_val_normal; 82 u8 voltage_bank; 83 u8 voltage_reg; 84 u8 voltage_mask; 85 struct { 86 u8 voltage_limit; 87 u8 voltage_bank; 88 u8 voltage_reg; 89 u8 voltage_mask; 90 } expand_register; 91 }; 92 93 /* voltage tables for the vauxn/vintcore supplies */ 94 static const unsigned int ldo_vauxn_voltages[] = { 95 1100000, 96 1200000, 97 1300000, 98 1400000, 99 1500000, 100 1800000, 101 1850000, 102 1900000, 103 2500000, 104 2650000, 105 2700000, 106 2750000, 107 2800000, 108 2900000, 109 3000000, 110 3300000, 111 }; 112 113 static const unsigned int ldo_vaux3_voltages[] = { 114 1200000, 115 1500000, 116 1800000, 117 2100000, 118 2500000, 119 2750000, 120 2790000, 121 2910000, 122 }; 123 124 static const unsigned int ldo_vaux56_voltages[] = { 125 1800000, 126 1050000, 127 1100000, 128 1200000, 129 1500000, 130 2200000, 131 2500000, 132 2790000, 133 }; 134 135 static const unsigned int ldo_vintcore_voltages[] = { 136 1200000, 137 1225000, 138 1250000, 139 1275000, 140 1300000, 141 1325000, 142 1350000, 143 }; 144 145 static const unsigned int ldo_sdio_voltages[] = { 146 1160000, 147 1050000, 148 1100000, 149 1500000, 150 1800000, 151 2200000, 152 2910000, 153 3050000, 154 }; 155 156 static const unsigned int fixed_1200000_voltage[] = { 157 1200000, 158 }; 159 160 static const unsigned int fixed_1800000_voltage[] = { 161 1800000, 162 }; 163 164 static const unsigned int fixed_2000000_voltage[] = { 165 2000000, 166 }; 167 168 static const unsigned int fixed_2050000_voltage[] = { 169 2050000, 170 }; 171 172 static const unsigned int fixed_3300000_voltage[] = { 173 3300000, 174 }; 175 176 static const unsigned int ldo_vana_voltages[] = { 177 1050000, 178 1075000, 179 1100000, 180 1125000, 181 1150000, 182 1175000, 183 1200000, 184 1225000, 185 }; 186 187 static const unsigned int ldo_vaudio_voltages[] = { 188 2000000, 189 2100000, 190 2200000, 191 2300000, 192 2400000, 193 2500000, 194 2600000, 195 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */ 196 }; 197 198 static const unsigned int ldo_vdmic_voltages[] = { 199 1800000, 200 1900000, 201 2000000, 202 2850000, 203 }; 204 205 static DEFINE_MUTEX(shared_mode_mutex); 206 static struct ab8500_shared_mode ldo_anamic1_shared; 207 static struct ab8500_shared_mode ldo_anamic2_shared; 208 209 static int ab8500_regulator_enable(struct regulator_dev *rdev) 210 { 211 int ret; 212 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 213 214 if (info == NULL) { 215 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 216 return -EINVAL; 217 } 218 219 ret = abx500_mask_and_set_register_interruptible(info->dev, 220 info->update_bank, info->update_reg, 221 info->update_mask, info->update_val); 222 if (ret < 0) { 223 dev_err(rdev_get_dev(rdev), 224 "couldn't set enable bits for regulator\n"); 225 return ret; 226 } 227 228 dev_vdbg(rdev_get_dev(rdev), 229 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 230 info->desc.name, info->update_bank, info->update_reg, 231 info->update_mask, info->update_val); 232 233 return ret; 234 } 235 236 static int ab8500_regulator_disable(struct regulator_dev *rdev) 237 { 238 int ret; 239 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 240 241 if (info == NULL) { 242 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 243 return -EINVAL; 244 } 245 246 ret = abx500_mask_and_set_register_interruptible(info->dev, 247 info->update_bank, info->update_reg, 248 info->update_mask, 0x0); 249 if (ret < 0) { 250 dev_err(rdev_get_dev(rdev), 251 "couldn't set disable bits for regulator\n"); 252 return ret; 253 } 254 255 dev_vdbg(rdev_get_dev(rdev), 256 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 257 info->desc.name, info->update_bank, info->update_reg, 258 info->update_mask, 0x0); 259 260 return ret; 261 } 262 263 static int ab8500_regulator_is_enabled(struct regulator_dev *rdev) 264 { 265 int ret; 266 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 267 u8 regval; 268 269 if (info == NULL) { 270 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 271 return -EINVAL; 272 } 273 274 ret = abx500_get_register_interruptible(info->dev, 275 info->update_bank, info->update_reg, ®val); 276 if (ret < 0) { 277 dev_err(rdev_get_dev(rdev), 278 "couldn't read 0x%x register\n", info->update_reg); 279 return ret; 280 } 281 282 dev_vdbg(rdev_get_dev(rdev), 283 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," 284 " 0x%x\n", 285 info->desc.name, info->update_bank, info->update_reg, 286 info->update_mask, regval); 287 288 if (regval & info->update_mask) 289 return 1; 290 else 291 return 0; 292 } 293 294 static unsigned int ab8500_regulator_get_optimum_mode( 295 struct regulator_dev *rdev, int input_uV, 296 int output_uV, int load_uA) 297 { 298 unsigned int mode; 299 300 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 301 302 if (info == NULL) { 303 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 304 return -EINVAL; 305 } 306 307 if (load_uA <= info->load_lp_uA) 308 mode = REGULATOR_MODE_IDLE; 309 else 310 mode = REGULATOR_MODE_NORMAL; 311 312 return mode; 313 } 314 315 static int ab8500_regulator_set_mode(struct regulator_dev *rdev, 316 unsigned int mode) 317 { 318 int ret = 0; 319 u8 bank, reg, mask, val; 320 bool lp_mode_req = false; 321 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 322 323 if (info == NULL) { 324 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 325 return -EINVAL; 326 } 327 328 if (info->mode_mask) { 329 bank = info->mode_bank; 330 reg = info->mode_reg; 331 mask = info->mode_mask; 332 } else { 333 bank = info->update_bank; 334 reg = info->update_reg; 335 mask = info->update_mask; 336 } 337 338 if (info->shared_mode) 339 mutex_lock(&shared_mode_mutex); 340 341 switch (mode) { 342 case REGULATOR_MODE_NORMAL: 343 if (info->shared_mode) 344 lp_mode_req = false; 345 346 if (info->mode_mask) 347 val = info->mode_val_normal; 348 else 349 val = info->update_val_normal; 350 break; 351 case REGULATOR_MODE_IDLE: 352 if (info->shared_mode) { 353 struct ab8500_regulator_info *shared_regulator; 354 355 shared_regulator = info->shared_mode->shared_regulator; 356 if (!shared_regulator->shared_mode->lp_mode_req) { 357 /* Other regulator prevent LP mode */ 358 info->shared_mode->lp_mode_req = true; 359 goto out_unlock; 360 } 361 362 lp_mode_req = true; 363 } 364 365 if (info->mode_mask) 366 val = info->mode_val_idle; 367 else 368 val = info->update_val_idle; 369 break; 370 default: 371 ret = -EINVAL; 372 goto out_unlock; 373 } 374 375 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) { 376 ret = abx500_mask_and_set_register_interruptible(info->dev, 377 bank, reg, mask, val); 378 if (ret < 0) { 379 dev_err(rdev_get_dev(rdev), 380 "couldn't set regulator mode\n"); 381 goto out_unlock; 382 } 383 384 dev_vdbg(rdev_get_dev(rdev), 385 "%s-set_mode (bank, reg, mask, value): " 386 "0x%x, 0x%x, 0x%x, 0x%x\n", 387 info->desc.name, bank, reg, 388 mask, val); 389 } 390 391 if (!info->mode_mask) 392 info->update_val = val; 393 394 if (info->shared_mode) 395 info->shared_mode->lp_mode_req = lp_mode_req; 396 397 out_unlock: 398 if (info->shared_mode) 399 mutex_unlock(&shared_mode_mutex); 400 401 return ret; 402 } 403 404 static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev) 405 { 406 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 407 int ret; 408 u8 val; 409 u8 val_normal; 410 u8 val_idle; 411 412 if (info == NULL) { 413 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 414 return -EINVAL; 415 } 416 417 /* Need special handling for shared mode */ 418 if (info->shared_mode) { 419 if (info->shared_mode->lp_mode_req) 420 return REGULATOR_MODE_IDLE; 421 else 422 return REGULATOR_MODE_NORMAL; 423 } 424 425 if (info->mode_mask) { 426 /* Dedicated register for handling mode */ 427 ret = abx500_get_register_interruptible(info->dev, 428 info->mode_bank, info->mode_reg, &val); 429 val = val & info->mode_mask; 430 431 val_normal = info->mode_val_normal; 432 val_idle = info->mode_val_idle; 433 } else { 434 /* Mode register same as enable register */ 435 val = info->update_val; 436 val_normal = info->update_val_normal; 437 val_idle = info->update_val_idle; 438 } 439 440 if (val == val_normal) 441 ret = REGULATOR_MODE_NORMAL; 442 else if (val == val_idle) 443 ret = REGULATOR_MODE_IDLE; 444 else 445 ret = -EINVAL; 446 447 return ret; 448 } 449 450 static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev) 451 { 452 int ret, voltage_shift; 453 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 454 u8 regval; 455 456 if (info == NULL) { 457 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 458 return -EINVAL; 459 } 460 461 voltage_shift = ffs(info->voltage_mask) - 1; 462 463 ret = abx500_get_register_interruptible(info->dev, 464 info->voltage_bank, info->voltage_reg, ®val); 465 if (ret < 0) { 466 dev_err(rdev_get_dev(rdev), 467 "couldn't read voltage reg for regulator\n"); 468 return ret; 469 } 470 471 dev_vdbg(rdev_get_dev(rdev), 472 "%s-get_voltage (bank, reg, mask, shift, value): " 473 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", 474 info->desc.name, info->voltage_bank, 475 info->voltage_reg, info->voltage_mask, 476 voltage_shift, regval); 477 478 return (regval & info->voltage_mask) >> voltage_shift; 479 } 480 481 static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev, 482 unsigned selector) 483 { 484 int ret, voltage_shift; 485 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 486 u8 regval; 487 488 if (info == NULL) { 489 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 490 return -EINVAL; 491 } 492 493 voltage_shift = ffs(info->voltage_mask) - 1; 494 495 /* set the registers for the request */ 496 regval = (u8)selector << voltage_shift; 497 ret = abx500_mask_and_set_register_interruptible(info->dev, 498 info->voltage_bank, info->voltage_reg, 499 info->voltage_mask, regval); 500 if (ret < 0) 501 dev_err(rdev_get_dev(rdev), 502 "couldn't set voltage reg for regulator\n"); 503 504 dev_vdbg(rdev_get_dev(rdev), 505 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," 506 " 0x%x\n", 507 info->desc.name, info->voltage_bank, info->voltage_reg, 508 info->voltage_mask, regval); 509 510 return ret; 511 } 512 513 static struct regulator_ops ab8500_regulator_volt_mode_ops = { 514 .enable = ab8500_regulator_enable, 515 .disable = ab8500_regulator_disable, 516 .is_enabled = ab8500_regulator_is_enabled, 517 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 518 .set_mode = ab8500_regulator_set_mode, 519 .get_mode = ab8500_regulator_get_mode, 520 .get_voltage_sel = ab8500_regulator_get_voltage_sel, 521 .set_voltage_sel = ab8500_regulator_set_voltage_sel, 522 .list_voltage = regulator_list_voltage_table, 523 }; 524 525 static struct regulator_ops ab8500_regulator_volt_ops = { 526 .enable = ab8500_regulator_enable, 527 .disable = ab8500_regulator_disable, 528 .is_enabled = ab8500_regulator_is_enabled, 529 .get_voltage_sel = ab8500_regulator_get_voltage_sel, 530 .set_voltage_sel = ab8500_regulator_set_voltage_sel, 531 .list_voltage = regulator_list_voltage_table, 532 }; 533 534 static struct regulator_ops ab8500_regulator_mode_ops = { 535 .enable = ab8500_regulator_enable, 536 .disable = ab8500_regulator_disable, 537 .is_enabled = ab8500_regulator_is_enabled, 538 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 539 .set_mode = ab8500_regulator_set_mode, 540 .get_mode = ab8500_regulator_get_mode, 541 .list_voltage = regulator_list_voltage_table, 542 }; 543 544 static struct regulator_ops ab8500_regulator_ops = { 545 .enable = ab8500_regulator_enable, 546 .disable = ab8500_regulator_disable, 547 .is_enabled = ab8500_regulator_is_enabled, 548 .list_voltage = regulator_list_voltage_table, 549 }; 550 551 static struct regulator_ops ab8500_regulator_anamic_mode_ops = { 552 .enable = ab8500_regulator_enable, 553 .disable = ab8500_regulator_disable, 554 .is_enabled = ab8500_regulator_is_enabled, 555 .set_mode = ab8500_regulator_set_mode, 556 .get_mode = ab8500_regulator_get_mode, 557 .list_voltage = regulator_list_voltage_table, 558 }; 559 560 /* AB8500 regulator information */ 561 static struct ab8500_regulator_info 562 ab8500_regulator_info[AB8500_NUM_REGULATORS] = { 563 /* 564 * Variable Voltage Regulators 565 * name, min mV, max mV, 566 * update bank, reg, mask, enable val 567 * volt bank, reg, mask 568 */ 569 [AB8500_LDO_AUX1] = { 570 .desc = { 571 .name = "LDO-AUX1", 572 .ops = &ab8500_regulator_volt_mode_ops, 573 .type = REGULATOR_VOLTAGE, 574 .id = AB8500_LDO_AUX1, 575 .owner = THIS_MODULE, 576 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 577 .volt_table = ldo_vauxn_voltages, 578 .enable_time = 200, 579 .supply_name = "vin", 580 }, 581 .load_lp_uA = 5000, 582 .update_bank = 0x04, 583 .update_reg = 0x09, 584 .update_mask = 0x03, 585 .update_val = 0x01, 586 .update_val_idle = 0x03, 587 .update_val_normal = 0x01, 588 .voltage_bank = 0x04, 589 .voltage_reg = 0x1f, 590 .voltage_mask = 0x0f, 591 }, 592 [AB8500_LDO_AUX2] = { 593 .desc = { 594 .name = "LDO-AUX2", 595 .ops = &ab8500_regulator_volt_mode_ops, 596 .type = REGULATOR_VOLTAGE, 597 .id = AB8500_LDO_AUX2, 598 .owner = THIS_MODULE, 599 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 600 .volt_table = ldo_vauxn_voltages, 601 .enable_time = 200, 602 .supply_name = "vin", 603 }, 604 .load_lp_uA = 5000, 605 .update_bank = 0x04, 606 .update_reg = 0x09, 607 .update_mask = 0x0c, 608 .update_val = 0x04, 609 .update_val_idle = 0x0c, 610 .update_val_normal = 0x04, 611 .voltage_bank = 0x04, 612 .voltage_reg = 0x20, 613 .voltage_mask = 0x0f, 614 }, 615 [AB8500_LDO_AUX3] = { 616 .desc = { 617 .name = "LDO-AUX3", 618 .ops = &ab8500_regulator_volt_mode_ops, 619 .type = REGULATOR_VOLTAGE, 620 .id = AB8500_LDO_AUX3, 621 .owner = THIS_MODULE, 622 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 623 .volt_table = ldo_vaux3_voltages, 624 .enable_time = 450, 625 .supply_name = "vin", 626 }, 627 .load_lp_uA = 5000, 628 .update_bank = 0x04, 629 .update_reg = 0x0a, 630 .update_mask = 0x03, 631 .update_val = 0x01, 632 .update_val_idle = 0x03, 633 .update_val_normal = 0x01, 634 .voltage_bank = 0x04, 635 .voltage_reg = 0x21, 636 .voltage_mask = 0x07, 637 }, 638 [AB8500_LDO_INTCORE] = { 639 .desc = { 640 .name = "LDO-INTCORE", 641 .ops = &ab8500_regulator_volt_mode_ops, 642 .type = REGULATOR_VOLTAGE, 643 .id = AB8500_LDO_INTCORE, 644 .owner = THIS_MODULE, 645 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 646 .volt_table = ldo_vintcore_voltages, 647 .enable_time = 750, 648 }, 649 .load_lp_uA = 5000, 650 .update_bank = 0x03, 651 .update_reg = 0x80, 652 .update_mask = 0x44, 653 .update_val = 0x44, 654 .update_val_idle = 0x44, 655 .update_val_normal = 0x04, 656 .voltage_bank = 0x03, 657 .voltage_reg = 0x80, 658 .voltage_mask = 0x38, 659 }, 660 661 /* 662 * Fixed Voltage Regulators 663 * name, fixed mV, 664 * update bank, reg, mask, enable val 665 */ 666 [AB8500_LDO_TVOUT] = { 667 .desc = { 668 .name = "LDO-TVOUT", 669 .ops = &ab8500_regulator_mode_ops, 670 .type = REGULATOR_VOLTAGE, 671 .id = AB8500_LDO_TVOUT, 672 .owner = THIS_MODULE, 673 .n_voltages = 1, 674 .volt_table = fixed_2000000_voltage, 675 .enable_time = 500, 676 }, 677 .load_lp_uA = 1000, 678 .update_bank = 0x03, 679 .update_reg = 0x80, 680 .update_mask = 0x82, 681 .update_val = 0x02, 682 .update_val_idle = 0x82, 683 .update_val_normal = 0x02, 684 }, 685 [AB8500_LDO_AUDIO] = { 686 .desc = { 687 .name = "LDO-AUDIO", 688 .ops = &ab8500_regulator_ops, 689 .type = REGULATOR_VOLTAGE, 690 .id = AB8500_LDO_AUDIO, 691 .owner = THIS_MODULE, 692 .n_voltages = 1, 693 .enable_time = 140, 694 .volt_table = fixed_2000000_voltage, 695 }, 696 .update_bank = 0x03, 697 .update_reg = 0x83, 698 .update_mask = 0x02, 699 .update_val = 0x02, 700 }, 701 [AB8500_LDO_ANAMIC1] = { 702 .desc = { 703 .name = "LDO-ANAMIC1", 704 .ops = &ab8500_regulator_ops, 705 .type = REGULATOR_VOLTAGE, 706 .id = AB8500_LDO_ANAMIC1, 707 .owner = THIS_MODULE, 708 .n_voltages = 1, 709 .enable_time = 500, 710 .volt_table = fixed_2050000_voltage, 711 }, 712 .update_bank = 0x03, 713 .update_reg = 0x83, 714 .update_mask = 0x08, 715 .update_val = 0x08, 716 }, 717 [AB8500_LDO_ANAMIC2] = { 718 .desc = { 719 .name = "LDO-ANAMIC2", 720 .ops = &ab8500_regulator_ops, 721 .type = REGULATOR_VOLTAGE, 722 .id = AB8500_LDO_ANAMIC2, 723 .owner = THIS_MODULE, 724 .n_voltages = 1, 725 .enable_time = 500, 726 .volt_table = fixed_2050000_voltage, 727 }, 728 .update_bank = 0x03, 729 .update_reg = 0x83, 730 .update_mask = 0x10, 731 .update_val = 0x10, 732 }, 733 [AB8500_LDO_DMIC] = { 734 .desc = { 735 .name = "LDO-DMIC", 736 .ops = &ab8500_regulator_ops, 737 .type = REGULATOR_VOLTAGE, 738 .id = AB8500_LDO_DMIC, 739 .owner = THIS_MODULE, 740 .n_voltages = 1, 741 .enable_time = 420, 742 .volt_table = fixed_1800000_voltage, 743 }, 744 .update_bank = 0x03, 745 .update_reg = 0x83, 746 .update_mask = 0x04, 747 .update_val = 0x04, 748 }, 749 750 /* 751 * Regulators with fixed voltage and normal/idle modes 752 */ 753 [AB8500_LDO_ANA] = { 754 .desc = { 755 .name = "LDO-ANA", 756 .ops = &ab8500_regulator_mode_ops, 757 .type = REGULATOR_VOLTAGE, 758 .id = AB8500_LDO_ANA, 759 .owner = THIS_MODULE, 760 .n_voltages = 1, 761 .enable_time = 140, 762 .volt_table = fixed_1200000_voltage, 763 }, 764 .load_lp_uA = 1000, 765 .update_bank = 0x04, 766 .update_reg = 0x06, 767 .update_mask = 0x0c, 768 .update_val = 0x04, 769 .update_val_idle = 0x0c, 770 .update_val_normal = 0x04, 771 }, 772 }; 773 774 /* AB8505 regulator information */ 775 static struct ab8500_regulator_info 776 ab8505_regulator_info[AB8505_NUM_REGULATORS] = { 777 /* 778 * Variable Voltage Regulators 779 * name, min mV, max mV, 780 * update bank, reg, mask, enable val 781 * volt bank, reg, mask 782 */ 783 [AB8505_LDO_AUX1] = { 784 .desc = { 785 .name = "LDO-AUX1", 786 .ops = &ab8500_regulator_volt_mode_ops, 787 .type = REGULATOR_VOLTAGE, 788 .id = AB8505_LDO_AUX1, 789 .owner = THIS_MODULE, 790 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 791 .volt_table = ldo_vauxn_voltages, 792 }, 793 .load_lp_uA = 5000, 794 .update_bank = 0x04, 795 .update_reg = 0x09, 796 .update_mask = 0x03, 797 .update_val = 0x01, 798 .update_val_idle = 0x03, 799 .update_val_normal = 0x01, 800 .voltage_bank = 0x04, 801 .voltage_reg = 0x1f, 802 .voltage_mask = 0x0f, 803 }, 804 [AB8505_LDO_AUX2] = { 805 .desc = { 806 .name = "LDO-AUX2", 807 .ops = &ab8500_regulator_volt_mode_ops, 808 .type = REGULATOR_VOLTAGE, 809 .id = AB8505_LDO_AUX2, 810 .owner = THIS_MODULE, 811 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 812 .volt_table = ldo_vauxn_voltages, 813 }, 814 .load_lp_uA = 5000, 815 .update_bank = 0x04, 816 .update_reg = 0x09, 817 .update_mask = 0x0c, 818 .update_val = 0x04, 819 .update_val_idle = 0x0c, 820 .update_val_normal = 0x04, 821 .voltage_bank = 0x04, 822 .voltage_reg = 0x20, 823 .voltage_mask = 0x0f, 824 }, 825 [AB8505_LDO_AUX3] = { 826 .desc = { 827 .name = "LDO-AUX3", 828 .ops = &ab8500_regulator_volt_mode_ops, 829 .type = REGULATOR_VOLTAGE, 830 .id = AB8505_LDO_AUX3, 831 .owner = THIS_MODULE, 832 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 833 .volt_table = ldo_vaux3_voltages, 834 }, 835 .load_lp_uA = 5000, 836 .update_bank = 0x04, 837 .update_reg = 0x0a, 838 .update_mask = 0x03, 839 .update_val = 0x01, 840 .update_val_idle = 0x03, 841 .update_val_normal = 0x01, 842 .voltage_bank = 0x04, 843 .voltage_reg = 0x21, 844 .voltage_mask = 0x07, 845 }, 846 [AB8505_LDO_AUX4] = { 847 .desc = { 848 .name = "LDO-AUX4", 849 .ops = &ab8500_regulator_volt_mode_ops, 850 .type = REGULATOR_VOLTAGE, 851 .id = AB8505_LDO_AUX4, 852 .owner = THIS_MODULE, 853 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 854 .volt_table = ldo_vauxn_voltages, 855 }, 856 .load_lp_uA = 5000, 857 /* values for Vaux4Regu register */ 858 .update_bank = 0x04, 859 .update_reg = 0x2e, 860 .update_mask = 0x03, 861 .update_val = 0x01, 862 .update_val_idle = 0x03, 863 .update_val_normal = 0x01, 864 /* values for Vaux4SEL register */ 865 .voltage_bank = 0x04, 866 .voltage_reg = 0x2f, 867 .voltage_mask = 0x0f, 868 }, 869 [AB8505_LDO_AUX5] = { 870 .desc = { 871 .name = "LDO-AUX5", 872 .ops = &ab8500_regulator_volt_mode_ops, 873 .type = REGULATOR_VOLTAGE, 874 .id = AB8505_LDO_AUX5, 875 .owner = THIS_MODULE, 876 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), 877 .volt_table = ldo_vaux56_voltages, 878 }, 879 .load_lp_uA = 2000, 880 /* values for CtrlVaux5 register */ 881 .update_bank = 0x01, 882 .update_reg = 0x55, 883 .update_mask = 0x18, 884 .update_val = 0x10, 885 .update_val_idle = 0x18, 886 .update_val_normal = 0x10, 887 .voltage_bank = 0x01, 888 .voltage_reg = 0x55, 889 .voltage_mask = 0x07, 890 }, 891 [AB8505_LDO_AUX6] = { 892 .desc = { 893 .name = "LDO-AUX6", 894 .ops = &ab8500_regulator_volt_mode_ops, 895 .type = REGULATOR_VOLTAGE, 896 .id = AB8505_LDO_AUX6, 897 .owner = THIS_MODULE, 898 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), 899 .volt_table = ldo_vaux56_voltages, 900 }, 901 .load_lp_uA = 2000, 902 /* values for CtrlVaux6 register */ 903 .update_bank = 0x01, 904 .update_reg = 0x56, 905 .update_mask = 0x18, 906 .update_val = 0x10, 907 .update_val_idle = 0x18, 908 .update_val_normal = 0x10, 909 .voltage_bank = 0x01, 910 .voltage_reg = 0x56, 911 .voltage_mask = 0x07, 912 }, 913 [AB8505_LDO_INTCORE] = { 914 .desc = { 915 .name = "LDO-INTCORE", 916 .ops = &ab8500_regulator_volt_mode_ops, 917 .type = REGULATOR_VOLTAGE, 918 .id = AB8505_LDO_INTCORE, 919 .owner = THIS_MODULE, 920 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 921 .volt_table = ldo_vintcore_voltages, 922 }, 923 .load_lp_uA = 5000, 924 .update_bank = 0x03, 925 .update_reg = 0x80, 926 .update_mask = 0x44, 927 .update_val = 0x04, 928 .update_val_idle = 0x44, 929 .update_val_normal = 0x04, 930 .voltage_bank = 0x03, 931 .voltage_reg = 0x80, 932 .voltage_mask = 0x38, 933 }, 934 935 /* 936 * Fixed Voltage Regulators 937 * name, fixed mV, 938 * update bank, reg, mask, enable val 939 */ 940 [AB8505_LDO_ADC] = { 941 .desc = { 942 .name = "LDO-ADC", 943 .ops = &ab8500_regulator_mode_ops, 944 .type = REGULATOR_VOLTAGE, 945 .id = AB8505_LDO_ADC, 946 .owner = THIS_MODULE, 947 .n_voltages = 1, 948 .volt_table = fixed_2000000_voltage, 949 .enable_time = 10000, 950 }, 951 .load_lp_uA = 1000, 952 .update_bank = 0x03, 953 .update_reg = 0x80, 954 .update_mask = 0x82, 955 .update_val = 0x02, 956 .update_val_idle = 0x82, 957 .update_val_normal = 0x02, 958 }, 959 [AB8505_LDO_USB] = { 960 .desc = { 961 .name = "LDO-USB", 962 .ops = &ab8500_regulator_mode_ops, 963 .type = REGULATOR_VOLTAGE, 964 .id = AB8505_LDO_USB, 965 .owner = THIS_MODULE, 966 .n_voltages = 1, 967 .volt_table = fixed_3300000_voltage, 968 }, 969 .update_bank = 0x03, 970 .update_reg = 0x82, 971 .update_mask = 0x03, 972 .update_val = 0x01, 973 .update_val_idle = 0x03, 974 .update_val_normal = 0x01, 975 }, 976 [AB8505_LDO_AUDIO] = { 977 .desc = { 978 .name = "LDO-AUDIO", 979 .ops = &ab8500_regulator_volt_ops, 980 .type = REGULATOR_VOLTAGE, 981 .id = AB8505_LDO_AUDIO, 982 .owner = THIS_MODULE, 983 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages), 984 .volt_table = ldo_vaudio_voltages, 985 }, 986 .update_bank = 0x03, 987 .update_reg = 0x83, 988 .update_mask = 0x02, 989 .update_val = 0x02, 990 .voltage_bank = 0x01, 991 .voltage_reg = 0x57, 992 .voltage_mask = 0x70, 993 }, 994 [AB8505_LDO_ANAMIC1] = { 995 .desc = { 996 .name = "LDO-ANAMIC1", 997 .ops = &ab8500_regulator_anamic_mode_ops, 998 .type = REGULATOR_VOLTAGE, 999 .id = AB8505_LDO_ANAMIC1, 1000 .owner = THIS_MODULE, 1001 .n_voltages = 1, 1002 .volt_table = fixed_2050000_voltage, 1003 }, 1004 .shared_mode = &ldo_anamic1_shared, 1005 .update_bank = 0x03, 1006 .update_reg = 0x83, 1007 .update_mask = 0x08, 1008 .update_val = 0x08, 1009 .mode_bank = 0x01, 1010 .mode_reg = 0x54, 1011 .mode_mask = 0x04, 1012 .mode_val_idle = 0x04, 1013 .mode_val_normal = 0x00, 1014 }, 1015 [AB8505_LDO_ANAMIC2] = { 1016 .desc = { 1017 .name = "LDO-ANAMIC2", 1018 .ops = &ab8500_regulator_anamic_mode_ops, 1019 .type = REGULATOR_VOLTAGE, 1020 .id = AB8505_LDO_ANAMIC2, 1021 .owner = THIS_MODULE, 1022 .n_voltages = 1, 1023 .volt_table = fixed_2050000_voltage, 1024 }, 1025 .shared_mode = &ldo_anamic2_shared, 1026 .update_bank = 0x03, 1027 .update_reg = 0x83, 1028 .update_mask = 0x10, 1029 .update_val = 0x10, 1030 .mode_bank = 0x01, 1031 .mode_reg = 0x54, 1032 .mode_mask = 0x04, 1033 .mode_val_idle = 0x04, 1034 .mode_val_normal = 0x00, 1035 }, 1036 [AB8505_LDO_AUX8] = { 1037 .desc = { 1038 .name = "LDO-AUX8", 1039 .ops = &ab8500_regulator_ops, 1040 .type = REGULATOR_VOLTAGE, 1041 .id = AB8505_LDO_AUX8, 1042 .owner = THIS_MODULE, 1043 .n_voltages = 1, 1044 .volt_table = fixed_1800000_voltage, 1045 }, 1046 .update_bank = 0x03, 1047 .update_reg = 0x83, 1048 .update_mask = 0x04, 1049 .update_val = 0x04, 1050 }, 1051 /* 1052 * Regulators with fixed voltage and normal/idle modes 1053 */ 1054 [AB8505_LDO_ANA] = { 1055 .desc = { 1056 .name = "LDO-ANA", 1057 .ops = &ab8500_regulator_volt_mode_ops, 1058 .type = REGULATOR_VOLTAGE, 1059 .id = AB8505_LDO_ANA, 1060 .owner = THIS_MODULE, 1061 .n_voltages = ARRAY_SIZE(ldo_vana_voltages), 1062 .volt_table = ldo_vana_voltages, 1063 }, 1064 .load_lp_uA = 1000, 1065 .update_bank = 0x04, 1066 .update_reg = 0x06, 1067 .update_mask = 0x0c, 1068 .update_val = 0x04, 1069 .update_val_idle = 0x0c, 1070 .update_val_normal = 0x04, 1071 .voltage_bank = 0x04, 1072 .voltage_reg = 0x29, 1073 .voltage_mask = 0x7, 1074 }, 1075 }; 1076 1077 static struct ab8500_shared_mode ldo_anamic1_shared = { 1078 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2], 1079 }; 1080 1081 static struct ab8500_shared_mode ldo_anamic2_shared = { 1082 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1], 1083 }; 1084 1085 struct ab8500_reg_init { 1086 u8 bank; 1087 u8 addr; 1088 u8 mask; 1089 }; 1090 1091 #define REG_INIT(_id, _bank, _addr, _mask) \ 1092 [_id] = { \ 1093 .bank = _bank, \ 1094 .addr = _addr, \ 1095 .mask = _mask, \ 1096 } 1097 1098 /* AB8500 register init */ 1099 static struct ab8500_reg_init ab8500_reg_init[] = { 1100 /* 1101 * 0x30, VanaRequestCtrl 1102 * 0xc0, VextSupply1RequestCtrl 1103 */ 1104 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0), 1105 /* 1106 * 0x03, VextSupply2RequestCtrl 1107 * 0x0c, VextSupply3RequestCtrl 1108 * 0x30, Vaux1RequestCtrl 1109 * 0xc0, Vaux2RequestCtrl 1110 */ 1111 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), 1112 /* 1113 * 0x03, Vaux3RequestCtrl 1114 * 0x04, SwHPReq 1115 */ 1116 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 1117 /* 1118 * 0x08, VanaSysClkReq1HPValid 1119 * 0x20, Vaux1SysClkReq1HPValid 1120 * 0x40, Vaux2SysClkReq1HPValid 1121 * 0x80, Vaux3SysClkReq1HPValid 1122 */ 1123 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8), 1124 /* 1125 * 0x10, VextSupply1SysClkReq1HPValid 1126 * 0x20, VextSupply2SysClkReq1HPValid 1127 * 0x40, VextSupply3SysClkReq1HPValid 1128 */ 1129 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70), 1130 /* 1131 * 0x08, VanaHwHPReq1Valid 1132 * 0x20, Vaux1HwHPReq1Valid 1133 * 0x40, Vaux2HwHPReq1Valid 1134 * 0x80, Vaux3HwHPReq1Valid 1135 */ 1136 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8), 1137 /* 1138 * 0x01, VextSupply1HwHPReq1Valid 1139 * 0x02, VextSupply2HwHPReq1Valid 1140 * 0x04, VextSupply3HwHPReq1Valid 1141 */ 1142 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), 1143 /* 1144 * 0x08, VanaHwHPReq2Valid 1145 * 0x20, Vaux1HwHPReq2Valid 1146 * 0x40, Vaux2HwHPReq2Valid 1147 * 0x80, Vaux3HwHPReq2Valid 1148 */ 1149 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8), 1150 /* 1151 * 0x01, VextSupply1HwHPReq2Valid 1152 * 0x02, VextSupply2HwHPReq2Valid 1153 * 0x04, VextSupply3HwHPReq2Valid 1154 */ 1155 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), 1156 /* 1157 * 0x20, VanaSwHPReqValid 1158 * 0x80, Vaux1SwHPReqValid 1159 */ 1160 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0), 1161 /* 1162 * 0x01, Vaux2SwHPReqValid 1163 * 0x02, Vaux3SwHPReqValid 1164 * 0x04, VextSupply1SwHPReqValid 1165 * 0x08, VextSupply2SwHPReqValid 1166 * 0x10, VextSupply3SwHPReqValid 1167 */ 1168 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), 1169 /* 1170 * 0x02, SysClkReq2Valid1 1171 * 0x04, SysClkReq3Valid1 1172 * 0x08, SysClkReq4Valid1 1173 * 0x10, SysClkReq5Valid1 1174 * 0x20, SysClkReq6Valid1 1175 * 0x40, SysClkReq7Valid1 1176 * 0x80, SysClkReq8Valid1 1177 */ 1178 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), 1179 /* 1180 * 0x02, SysClkReq2Valid2 1181 * 0x04, SysClkReq3Valid2 1182 * 0x08, SysClkReq4Valid2 1183 * 0x10, SysClkReq5Valid2 1184 * 0x20, SysClkReq6Valid2 1185 * 0x40, SysClkReq7Valid2 1186 * 0x80, SysClkReq8Valid2 1187 */ 1188 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), 1189 /* 1190 * 0x02, VTVoutEna 1191 * 0x04, Vintcore12Ena 1192 * 0x38, Vintcore12Sel 1193 * 0x40, Vintcore12LP 1194 * 0x80, VTVoutLP 1195 */ 1196 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe), 1197 /* 1198 * 0x02, VaudioEna 1199 * 0x04, VdmicEna 1200 * 0x08, Vamic1Ena 1201 * 0x10, Vamic2Ena 1202 */ 1203 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 1204 /* 1205 * 0x01, Vamic1_dzout 1206 * 0x02, Vamic2_dzout 1207 */ 1208 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 1209 /* 1210 * 0x03, VpllRegu (NOTE! PRCMU register bits) 1211 * 0x0c, VanaRegu 1212 */ 1213 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f), 1214 /* 1215 * 0x01, VrefDDREna 1216 * 0x02, VrefDDRSleepMode 1217 */ 1218 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03), 1219 /* 1220 * 0x03, VextSupply1Regu 1221 * 0x0c, VextSupply2Regu 1222 * 0x30, VextSupply3Regu 1223 * 0x40, ExtSupply2Bypass 1224 * 0x80, ExtSupply3Bypass 1225 */ 1226 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 1227 /* 1228 * 0x03, Vaux1Regu 1229 * 0x0c, Vaux2Regu 1230 */ 1231 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f), 1232 /* 1233 * 0x03, Vaux3Regu 1234 */ 1235 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03), 1236 /* 1237 * 0x0f, Vaux1Sel 1238 */ 1239 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f), 1240 /* 1241 * 0x0f, Vaux2Sel 1242 */ 1243 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f), 1244 /* 1245 * 0x07, Vaux3Sel 1246 */ 1247 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07), 1248 /* 1249 * 0x01, VextSupply12LP 1250 */ 1251 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01), 1252 /* 1253 * 0x04, Vaux1Disch 1254 * 0x08, Vaux2Disch 1255 * 0x10, Vaux3Disch 1256 * 0x20, Vintcore12Disch 1257 * 0x40, VTVoutDisch 1258 * 0x80, VaudioDisch 1259 */ 1260 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc), 1261 /* 1262 * 0x02, VanaDisch 1263 * 0x04, VdmicPullDownEna 1264 * 0x10, VdmicDisch 1265 */ 1266 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 1267 }; 1268 1269 /* AB8505 register init */ 1270 static struct ab8500_reg_init ab8505_reg_init[] = { 1271 /* 1272 * 0x03, VarmRequestCtrl 1273 * 0x0c, VsmpsCRequestCtrl 1274 * 0x30, VsmpsARequestCtrl 1275 * 0xc0, VsmpsBRequestCtrl 1276 */ 1277 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), 1278 /* 1279 * 0x03, VsafeRequestCtrl 1280 * 0x0c, VpllRequestCtrl 1281 * 0x30, VanaRequestCtrl 1282 */ 1283 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f), 1284 /* 1285 * 0x30, Vaux1RequestCtrl 1286 * 0xc0, Vaux2RequestCtrl 1287 */ 1288 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0), 1289 /* 1290 * 0x03, Vaux3RequestCtrl 1291 * 0x04, SwHPReq 1292 */ 1293 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 1294 /* 1295 * 0x01, VsmpsASysClkReq1HPValid 1296 * 0x02, VsmpsBSysClkReq1HPValid 1297 * 0x04, VsafeSysClkReq1HPValid 1298 * 0x08, VanaSysClkReq1HPValid 1299 * 0x10, VpllSysClkReq1HPValid 1300 * 0x20, Vaux1SysClkReq1HPValid 1301 * 0x40, Vaux2SysClkReq1HPValid 1302 * 0x80, Vaux3SysClkReq1HPValid 1303 */ 1304 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), 1305 /* 1306 * 0x01, VsmpsCSysClkReq1HPValid 1307 * 0x02, VarmSysClkReq1HPValid 1308 * 0x04, VbbSysClkReq1HPValid 1309 * 0x08, VsmpsMSysClkReq1HPValid 1310 */ 1311 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f), 1312 /* 1313 * 0x01, VsmpsAHwHPReq1Valid 1314 * 0x02, VsmpsBHwHPReq1Valid 1315 * 0x04, VsafeHwHPReq1Valid 1316 * 0x08, VanaHwHPReq1Valid 1317 * 0x10, VpllHwHPReq1Valid 1318 * 0x20, Vaux1HwHPReq1Valid 1319 * 0x40, Vaux2HwHPReq1Valid 1320 * 0x80, Vaux3HwHPReq1Valid 1321 */ 1322 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), 1323 /* 1324 * 0x08, VsmpsMHwHPReq1Valid 1325 */ 1326 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08), 1327 /* 1328 * 0x01, VsmpsAHwHPReq2Valid 1329 * 0x02, VsmpsBHwHPReq2Valid 1330 * 0x04, VsafeHwHPReq2Valid 1331 * 0x08, VanaHwHPReq2Valid 1332 * 0x10, VpllHwHPReq2Valid 1333 * 0x20, Vaux1HwHPReq2Valid 1334 * 0x40, Vaux2HwHPReq2Valid 1335 * 0x80, Vaux3HwHPReq2Valid 1336 */ 1337 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), 1338 /* 1339 * 0x08, VsmpsMHwHPReq2Valid 1340 */ 1341 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08), 1342 /* 1343 * 0x01, VsmpsCSwHPReqValid 1344 * 0x02, VarmSwHPReqValid 1345 * 0x04, VsmpsASwHPReqValid 1346 * 0x08, VsmpsBSwHPReqValid 1347 * 0x10, VsafeSwHPReqValid 1348 * 0x20, VanaSwHPReqValid 1349 * 0x40, VpllSwHPReqValid 1350 * 0x80, Vaux1SwHPReqValid 1351 */ 1352 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), 1353 /* 1354 * 0x01, Vaux2SwHPReqValid 1355 * 0x02, Vaux3SwHPReqValid 1356 * 0x20, VsmpsMSwHPReqValid 1357 */ 1358 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23), 1359 /* 1360 * 0x02, SysClkReq2Valid1 1361 * 0x04, SysClkReq3Valid1 1362 * 0x08, SysClkReq4Valid1 1363 */ 1364 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e), 1365 /* 1366 * 0x02, SysClkReq2Valid2 1367 * 0x04, SysClkReq3Valid2 1368 * 0x08, SysClkReq4Valid2 1369 */ 1370 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e), 1371 /* 1372 * 0x01, Vaux4SwHPReqValid 1373 * 0x02, Vaux4HwHPReq2Valid 1374 * 0x04, Vaux4HwHPReq1Valid 1375 * 0x08, Vaux4SysClkReq1HPValid 1376 */ 1377 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), 1378 /* 1379 * 0x02, VadcEna 1380 * 0x04, VintCore12Ena 1381 * 0x38, VintCore12Sel 1382 * 0x40, VintCore12LP 1383 * 0x80, VadcLP 1384 */ 1385 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe), 1386 /* 1387 * 0x02, VaudioEna 1388 * 0x04, VdmicEna 1389 * 0x08, Vamic1Ena 1390 * 0x10, Vamic2Ena 1391 */ 1392 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 1393 /* 1394 * 0x01, Vamic1_dzout 1395 * 0x02, Vamic2_dzout 1396 */ 1397 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 1398 /* 1399 * 0x03, VsmpsARegu 1400 * 0x0c, VsmpsASelCtrl 1401 * 0x10, VsmpsAAutoMode 1402 * 0x20, VsmpsAPWMMode 1403 */ 1404 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f), 1405 /* 1406 * 0x03, VsmpsBRegu 1407 * 0x0c, VsmpsBSelCtrl 1408 * 0x10, VsmpsBAutoMode 1409 * 0x20, VsmpsBPWMMode 1410 */ 1411 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f), 1412 /* 1413 * 0x03, VsafeRegu 1414 * 0x0c, VsafeSelCtrl 1415 * 0x10, VsafeAutoMode 1416 * 0x20, VsafePWMMode 1417 */ 1418 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f), 1419 /* 1420 * 0x03, VpllRegu (NOTE! PRCMU register bits) 1421 * 0x0c, VanaRegu 1422 */ 1423 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f), 1424 /* 1425 * 0x03, VextSupply1Regu 1426 * 0x0c, VextSupply2Regu 1427 * 0x30, VextSupply3Regu 1428 * 0x40, ExtSupply2Bypass 1429 * 0x80, ExtSupply3Bypass 1430 */ 1431 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 1432 /* 1433 * 0x03, Vaux1Regu 1434 * 0x0c, Vaux2Regu 1435 */ 1436 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f), 1437 /* 1438 * 0x0f, Vaux3Regu 1439 */ 1440 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), 1441 /* 1442 * 0x3f, VsmpsASel1 1443 */ 1444 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f), 1445 /* 1446 * 0x3f, VsmpsASel2 1447 */ 1448 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f), 1449 /* 1450 * 0x3f, VsmpsASel3 1451 */ 1452 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f), 1453 /* 1454 * 0x3f, VsmpsBSel1 1455 */ 1456 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f), 1457 /* 1458 * 0x3f, VsmpsBSel2 1459 */ 1460 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f), 1461 /* 1462 * 0x3f, VsmpsBSel3 1463 */ 1464 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f), 1465 /* 1466 * 0x7f, VsafeSel1 1467 */ 1468 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f), 1469 /* 1470 * 0x3f, VsafeSel2 1471 */ 1472 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f), 1473 /* 1474 * 0x3f, VsafeSel3 1475 */ 1476 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f), 1477 /* 1478 * 0x0f, Vaux1Sel 1479 */ 1480 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f), 1481 /* 1482 * 0x0f, Vaux2Sel 1483 */ 1484 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f), 1485 /* 1486 * 0x07, Vaux3Sel 1487 * 0x30, VRF1Sel 1488 */ 1489 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37), 1490 /* 1491 * 0x03, Vaux4RequestCtrl 1492 */ 1493 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03), 1494 /* 1495 * 0x03, Vaux4Regu 1496 */ 1497 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03), 1498 /* 1499 * 0x0f, Vaux4Sel 1500 */ 1501 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f), 1502 /* 1503 * 0x04, Vaux1Disch 1504 * 0x08, Vaux2Disch 1505 * 0x10, Vaux3Disch 1506 * 0x20, Vintcore12Disch 1507 * 0x40, VTVoutDisch 1508 * 0x80, VaudioDisch 1509 */ 1510 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc), 1511 /* 1512 * 0x02, VanaDisch 1513 * 0x04, VdmicPullDownEna 1514 * 0x10, VdmicDisch 1515 */ 1516 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 1517 /* 1518 * 0x01, Vaux4Disch 1519 */ 1520 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01), 1521 /* 1522 * 0x07, Vaux5Sel 1523 * 0x08, Vaux5LP 1524 * 0x10, Vaux5Ena 1525 * 0x20, Vaux5Disch 1526 * 0x40, Vaux5DisSfst 1527 * 0x80, Vaux5DisPulld 1528 */ 1529 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff), 1530 /* 1531 * 0x07, Vaux6Sel 1532 * 0x08, Vaux6LP 1533 * 0x10, Vaux6Ena 1534 * 0x80, Vaux6DisPulld 1535 */ 1536 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f), 1537 }; 1538 1539 static struct of_regulator_match ab8500_regulator_match[] = { 1540 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, }, 1541 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, }, 1542 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, }, 1543 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, }, 1544 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, 1545 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, 1546 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, 1547 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, 1548 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, 1549 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, 1550 }; 1551 1552 static struct of_regulator_match ab8505_regulator_match[] = { 1553 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, }, 1554 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, }, 1555 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, }, 1556 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, }, 1557 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, }, 1558 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, }, 1559 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, }, 1560 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, 1561 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, 1562 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, 1563 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, 1564 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, 1565 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, 1566 }; 1567 1568 static struct { 1569 struct ab8500_regulator_info *info; 1570 int info_size; 1571 struct ab8500_reg_init *init; 1572 int init_size; 1573 struct of_regulator_match *match; 1574 int match_size; 1575 } abx500_regulator; 1576 1577 static void abx500_get_regulator_info(struct ab8500 *ab8500) 1578 { 1579 if (is_ab8505(ab8500)) { 1580 abx500_regulator.info = ab8505_regulator_info; 1581 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info); 1582 abx500_regulator.init = ab8505_reg_init; 1583 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS; 1584 abx500_regulator.match = ab8505_regulator_match; 1585 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match); 1586 } else { 1587 abx500_regulator.info = ab8500_regulator_info; 1588 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info); 1589 abx500_regulator.init = ab8500_reg_init; 1590 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS; 1591 abx500_regulator.match = ab8500_regulator_match; 1592 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match); 1593 } 1594 } 1595 1596 static int ab8500_regulator_register(struct platform_device *pdev, 1597 struct regulator_init_data *init_data, 1598 int id, struct device_node *np) 1599 { 1600 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 1601 struct ab8500_regulator_info *info = NULL; 1602 struct regulator_config config = { }; 1603 1604 /* assign per-regulator data */ 1605 info = &abx500_regulator.info[id]; 1606 info->dev = &pdev->dev; 1607 1608 config.dev = &pdev->dev; 1609 config.init_data = init_data; 1610 config.driver_data = info; 1611 config.of_node = np; 1612 1613 /* fix for hardware before ab8500v2.0 */ 1614 if (is_ab8500_1p1_or_earlier(ab8500)) { 1615 if (info->desc.id == AB8500_LDO_AUX3) { 1616 info->desc.n_voltages = 1617 ARRAY_SIZE(ldo_vauxn_voltages); 1618 info->desc.volt_table = ldo_vauxn_voltages; 1619 info->voltage_mask = 0xf; 1620 } 1621 } 1622 1623 /* register regulator with framework */ 1624 info->regulator = devm_regulator_register(&pdev->dev, &info->desc, 1625 &config); 1626 if (IS_ERR(info->regulator)) { 1627 dev_err(&pdev->dev, "failed to register regulator %s\n", 1628 info->desc.name); 1629 return PTR_ERR(info->regulator); 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int ab8500_regulator_probe(struct platform_device *pdev) 1636 { 1637 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 1638 struct device_node *np = pdev->dev.of_node; 1639 struct of_regulator_match *match; 1640 int err, i; 1641 1642 if (!ab8500) { 1643 dev_err(&pdev->dev, "null mfd parent\n"); 1644 return -EINVAL; 1645 } 1646 1647 abx500_get_regulator_info(ab8500); 1648 1649 err = of_regulator_match(&pdev->dev, np, 1650 abx500_regulator.match, 1651 abx500_regulator.match_size); 1652 if (err < 0) { 1653 dev_err(&pdev->dev, 1654 "Error parsing regulator init data: %d\n", err); 1655 return err; 1656 } 1657 1658 match = abx500_regulator.match; 1659 for (i = 0; i < abx500_regulator.info_size; i++) { 1660 err = ab8500_regulator_register(pdev, match[i].init_data, i, 1661 match[i].of_node); 1662 if (err) 1663 return err; 1664 } 1665 1666 return 0; 1667 } 1668 1669 static struct platform_driver ab8500_regulator_driver = { 1670 .probe = ab8500_regulator_probe, 1671 .driver = { 1672 .name = "ab8500-regulator", 1673 }, 1674 }; 1675 1676 static int __init ab8500_regulator_init(void) 1677 { 1678 int ret; 1679 1680 ret = platform_driver_register(&ab8500_regulator_driver); 1681 if (ret != 0) 1682 pr_err("Failed to register ab8500 regulator: %d\n", ret); 1683 1684 return ret; 1685 } 1686 subsys_initcall(ab8500_regulator_init); 1687 1688 static void __exit ab8500_regulator_exit(void) 1689 { 1690 platform_driver_unregister(&ab8500_regulator_driver); 1691 } 1692 module_exit(ab8500_regulator_exit); 1693 1694 MODULE_LICENSE("GPL v2"); 1695 MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>"); 1696 MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>"); 1697 MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>"); 1698 MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC"); 1699 MODULE_ALIAS("platform:ab8500-regulator"); 1700