1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License Terms: GNU General Public License v2 5 * 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson 7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson 9 * 10 * AB8500 peripheral regulators 11 * 12 * AB8500 supports the following regulators: 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 14 * 15 * AB8505 supports the following regulators: 16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 17 */ 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/err.h> 22 #include <linux/platform_device.h> 23 #include <linux/mfd/abx500.h> 24 #include <linux/mfd/abx500/ab8500.h> 25 #include <linux/of.h> 26 #include <linux/regulator/of_regulator.h> 27 #include <linux/regulator/driver.h> 28 #include <linux/regulator/machine.h> 29 #include <linux/regulator/ab8500.h> 30 #include <linux/slab.h> 31 32 /** 33 * struct ab8500_shared_mode - is used when mode is shared between 34 * two regulators. 35 * @shared_regulator: pointer to the other sharing regulator 36 * @lp_mode_req: low power mode requested by this regulator 37 */ 38 struct ab8500_shared_mode { 39 struct ab8500_regulator_info *shared_regulator; 40 bool lp_mode_req; 41 }; 42 43 /** 44 * struct ab8500_regulator_info - ab8500 regulator information 45 * @dev: device pointer 46 * @desc: regulator description 47 * @regulator_dev: regulator device 48 * @shared_mode: used when mode is shared between two regulators 49 * @load_lp_uA: maximum load in idle (low power) mode 50 * @update_bank: bank to control on/off 51 * @update_reg: register to control on/off 52 * @update_mask: mask to enable/disable and set mode of regulator 53 * @update_val: bits holding the regulator current mode 54 * @update_val_idle: bits to enable the regulator in idle (low power) mode 55 * @update_val_normal: bits to enable the regulator in normal (high power) mode 56 * @mode_bank: bank with location of mode register 57 * @mode_reg: mode register 58 * @mode_mask: mask for setting mode 59 * @mode_val_idle: mode setting for low power 60 * @mode_val_normal: mode setting for normal power 61 * @voltage_bank: bank to control regulator voltage 62 * @voltage_reg: register to control regulator voltage 63 * @voltage_mask: mask to control regulator voltage 64 */ 65 struct ab8500_regulator_info { 66 struct device *dev; 67 struct regulator_desc desc; 68 struct regulator_dev *regulator; 69 struct ab8500_shared_mode *shared_mode; 70 int load_lp_uA; 71 u8 update_bank; 72 u8 update_reg; 73 u8 update_mask; 74 u8 update_val; 75 u8 update_val_idle; 76 u8 update_val_normal; 77 u8 mode_bank; 78 u8 mode_reg; 79 u8 mode_mask; 80 u8 mode_val_idle; 81 u8 mode_val_normal; 82 u8 voltage_bank; 83 u8 voltage_reg; 84 u8 voltage_mask; 85 struct { 86 u8 voltage_limit; 87 u8 voltage_bank; 88 u8 voltage_reg; 89 u8 voltage_mask; 90 } expand_register; 91 }; 92 93 /* voltage tables for the vauxn/vintcore supplies */ 94 static const unsigned int ldo_vauxn_voltages[] = { 95 1100000, 96 1200000, 97 1300000, 98 1400000, 99 1500000, 100 1800000, 101 1850000, 102 1900000, 103 2500000, 104 2650000, 105 2700000, 106 2750000, 107 2800000, 108 2900000, 109 3000000, 110 3300000, 111 }; 112 113 static const unsigned int ldo_vaux3_voltages[] = { 114 1200000, 115 1500000, 116 1800000, 117 2100000, 118 2500000, 119 2750000, 120 2790000, 121 2910000, 122 }; 123 124 static const unsigned int ldo_vaux56_voltages[] = { 125 1800000, 126 1050000, 127 1100000, 128 1200000, 129 1500000, 130 2200000, 131 2500000, 132 2790000, 133 }; 134 135 static const unsigned int ldo_vaux3_ab8540_voltages[] = { 136 1200000, 137 1500000, 138 1800000, 139 2100000, 140 2500000, 141 2750000, 142 2790000, 143 2910000, 144 3050000, 145 }; 146 147 static const unsigned int ldo_vaux56_ab8540_voltages[] = { 148 750000, 760000, 770000, 780000, 790000, 800000, 149 810000, 820000, 830000, 840000, 850000, 860000, 150 870000, 880000, 890000, 900000, 910000, 920000, 151 930000, 940000, 950000, 960000, 970000, 980000, 152 990000, 1000000, 1010000, 1020000, 1030000, 153 1040000, 1050000, 1060000, 1070000, 1080000, 154 1090000, 1100000, 1110000, 1120000, 1130000, 155 1140000, 1150000, 1160000, 1170000, 1180000, 156 1190000, 1200000, 1210000, 1220000, 1230000, 157 1240000, 1250000, 1260000, 1270000, 1280000, 158 1290000, 1300000, 1310000, 1320000, 1330000, 159 1340000, 1350000, 1360000, 1800000, 2790000, 160 }; 161 162 static const unsigned int ldo_vintcore_voltages[] = { 163 1200000, 164 1225000, 165 1250000, 166 1275000, 167 1300000, 168 1325000, 169 1350000, 170 }; 171 172 static const unsigned int ldo_sdio_voltages[] = { 173 1160000, 174 1050000, 175 1100000, 176 1500000, 177 1800000, 178 2200000, 179 2910000, 180 3050000, 181 }; 182 183 static const unsigned int fixed_1200000_voltage[] = { 184 1200000, 185 }; 186 187 static const unsigned int fixed_1800000_voltage[] = { 188 1800000, 189 }; 190 191 static const unsigned int fixed_2000000_voltage[] = { 192 2000000, 193 }; 194 195 static const unsigned int fixed_2050000_voltage[] = { 196 2050000, 197 }; 198 199 static const unsigned int fixed_3300000_voltage[] = { 200 3300000, 201 }; 202 203 static const unsigned int ldo_vana_voltages[] = { 204 1050000, 205 1075000, 206 1100000, 207 1125000, 208 1150000, 209 1175000, 210 1200000, 211 1225000, 212 }; 213 214 static const unsigned int ldo_vaudio_voltages[] = { 215 2000000, 216 2100000, 217 2200000, 218 2300000, 219 2400000, 220 2500000, 221 2600000, 222 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */ 223 }; 224 225 static const unsigned int ldo_vdmic_voltages[] = { 226 1800000, 227 1900000, 228 2000000, 229 2850000, 230 }; 231 232 static DEFINE_MUTEX(shared_mode_mutex); 233 static struct ab8500_shared_mode ldo_anamic1_shared; 234 static struct ab8500_shared_mode ldo_anamic2_shared; 235 static struct ab8500_shared_mode ab8540_ldo_anamic1_shared; 236 static struct ab8500_shared_mode ab8540_ldo_anamic2_shared; 237 238 static int ab8500_regulator_enable(struct regulator_dev *rdev) 239 { 240 int ret; 241 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 242 243 if (info == NULL) { 244 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 245 return -EINVAL; 246 } 247 248 ret = abx500_mask_and_set_register_interruptible(info->dev, 249 info->update_bank, info->update_reg, 250 info->update_mask, info->update_val); 251 if (ret < 0) { 252 dev_err(rdev_get_dev(rdev), 253 "couldn't set enable bits for regulator\n"); 254 return ret; 255 } 256 257 dev_vdbg(rdev_get_dev(rdev), 258 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 259 info->desc.name, info->update_bank, info->update_reg, 260 info->update_mask, info->update_val); 261 262 return ret; 263 } 264 265 static int ab8500_regulator_disable(struct regulator_dev *rdev) 266 { 267 int ret; 268 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 269 270 if (info == NULL) { 271 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 272 return -EINVAL; 273 } 274 275 ret = abx500_mask_and_set_register_interruptible(info->dev, 276 info->update_bank, info->update_reg, 277 info->update_mask, 0x0); 278 if (ret < 0) { 279 dev_err(rdev_get_dev(rdev), 280 "couldn't set disable bits for regulator\n"); 281 return ret; 282 } 283 284 dev_vdbg(rdev_get_dev(rdev), 285 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 286 info->desc.name, info->update_bank, info->update_reg, 287 info->update_mask, 0x0); 288 289 return ret; 290 } 291 292 static int ab8500_regulator_is_enabled(struct regulator_dev *rdev) 293 { 294 int ret; 295 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 296 u8 regval; 297 298 if (info == NULL) { 299 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 300 return -EINVAL; 301 } 302 303 ret = abx500_get_register_interruptible(info->dev, 304 info->update_bank, info->update_reg, ®val); 305 if (ret < 0) { 306 dev_err(rdev_get_dev(rdev), 307 "couldn't read 0x%x register\n", info->update_reg); 308 return ret; 309 } 310 311 dev_vdbg(rdev_get_dev(rdev), 312 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," 313 " 0x%x\n", 314 info->desc.name, info->update_bank, info->update_reg, 315 info->update_mask, regval); 316 317 if (regval & info->update_mask) 318 return 1; 319 else 320 return 0; 321 } 322 323 static unsigned int ab8500_regulator_get_optimum_mode( 324 struct regulator_dev *rdev, int input_uV, 325 int output_uV, int load_uA) 326 { 327 unsigned int mode; 328 329 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 330 331 if (info == NULL) { 332 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 333 return -EINVAL; 334 } 335 336 if (load_uA <= info->load_lp_uA) 337 mode = REGULATOR_MODE_IDLE; 338 else 339 mode = REGULATOR_MODE_NORMAL; 340 341 return mode; 342 } 343 344 static int ab8500_regulator_set_mode(struct regulator_dev *rdev, 345 unsigned int mode) 346 { 347 int ret = 0; 348 u8 bank, reg, mask, val; 349 bool lp_mode_req = false; 350 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 351 352 if (info == NULL) { 353 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 354 return -EINVAL; 355 } 356 357 if (info->mode_mask) { 358 bank = info->mode_bank; 359 reg = info->mode_reg; 360 mask = info->mode_mask; 361 } else { 362 bank = info->update_bank; 363 reg = info->update_reg; 364 mask = info->update_mask; 365 } 366 367 if (info->shared_mode) 368 mutex_lock(&shared_mode_mutex); 369 370 switch (mode) { 371 case REGULATOR_MODE_NORMAL: 372 if (info->shared_mode) 373 lp_mode_req = false; 374 375 if (info->mode_mask) 376 val = info->mode_val_normal; 377 else 378 val = info->update_val_normal; 379 break; 380 case REGULATOR_MODE_IDLE: 381 if (info->shared_mode) { 382 struct ab8500_regulator_info *shared_regulator; 383 384 shared_regulator = info->shared_mode->shared_regulator; 385 if (!shared_regulator->shared_mode->lp_mode_req) { 386 /* Other regulator prevent LP mode */ 387 info->shared_mode->lp_mode_req = true; 388 goto out_unlock; 389 } 390 391 lp_mode_req = true; 392 } 393 394 if (info->mode_mask) 395 val = info->mode_val_idle; 396 else 397 val = info->update_val_idle; 398 break; 399 default: 400 ret = -EINVAL; 401 goto out_unlock; 402 } 403 404 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) { 405 ret = abx500_mask_and_set_register_interruptible(info->dev, 406 bank, reg, mask, val); 407 if (ret < 0) { 408 dev_err(rdev_get_dev(rdev), 409 "couldn't set regulator mode\n"); 410 goto out_unlock; 411 } 412 413 dev_vdbg(rdev_get_dev(rdev), 414 "%s-set_mode (bank, reg, mask, value): " 415 "0x%x, 0x%x, 0x%x, 0x%x\n", 416 info->desc.name, bank, reg, 417 mask, val); 418 } 419 420 if (!info->mode_mask) 421 info->update_val = val; 422 423 if (info->shared_mode) 424 info->shared_mode->lp_mode_req = lp_mode_req; 425 426 out_unlock: 427 if (info->shared_mode) 428 mutex_unlock(&shared_mode_mutex); 429 430 return ret; 431 } 432 433 static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev) 434 { 435 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 436 int ret; 437 u8 val; 438 u8 val_normal; 439 u8 val_idle; 440 441 if (info == NULL) { 442 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 443 return -EINVAL; 444 } 445 446 /* Need special handling for shared mode */ 447 if (info->shared_mode) { 448 if (info->shared_mode->lp_mode_req) 449 return REGULATOR_MODE_IDLE; 450 else 451 return REGULATOR_MODE_NORMAL; 452 } 453 454 if (info->mode_mask) { 455 /* Dedicated register for handling mode */ 456 ret = abx500_get_register_interruptible(info->dev, 457 info->mode_bank, info->mode_reg, &val); 458 val = val & info->mode_mask; 459 460 val_normal = info->mode_val_normal; 461 val_idle = info->mode_val_idle; 462 } else { 463 /* Mode register same as enable register */ 464 val = info->update_val; 465 val_normal = info->update_val_normal; 466 val_idle = info->update_val_idle; 467 } 468 469 if (val == val_normal) 470 ret = REGULATOR_MODE_NORMAL; 471 else if (val == val_idle) 472 ret = REGULATOR_MODE_IDLE; 473 else 474 ret = -EINVAL; 475 476 return ret; 477 } 478 479 static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev) 480 { 481 int ret, voltage_shift; 482 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 483 u8 regval; 484 485 if (info == NULL) { 486 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 487 return -EINVAL; 488 } 489 490 voltage_shift = ffs(info->voltage_mask) - 1; 491 492 ret = abx500_get_register_interruptible(info->dev, 493 info->voltage_bank, info->voltage_reg, ®val); 494 if (ret < 0) { 495 dev_err(rdev_get_dev(rdev), 496 "couldn't read voltage reg for regulator\n"); 497 return ret; 498 } 499 500 dev_vdbg(rdev_get_dev(rdev), 501 "%s-get_voltage (bank, reg, mask, shift, value): " 502 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", 503 info->desc.name, info->voltage_bank, 504 info->voltage_reg, info->voltage_mask, 505 voltage_shift, regval); 506 507 return (regval & info->voltage_mask) >> voltage_shift; 508 } 509 510 static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev) 511 { 512 int ret, voltage_shift; 513 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 514 u8 regval, regval_expand; 515 516 if (info == NULL) { 517 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 518 return -EINVAL; 519 } 520 521 ret = abx500_get_register_interruptible(info->dev, 522 info->expand_register.voltage_bank, 523 info->expand_register.voltage_reg, ®val_expand); 524 if (ret < 0) { 525 dev_err(rdev_get_dev(rdev), 526 "couldn't read voltage expand reg for regulator\n"); 527 return ret; 528 } 529 530 dev_vdbg(rdev_get_dev(rdev), 531 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 532 info->desc.name, info->expand_register.voltage_bank, 533 info->expand_register.voltage_reg, 534 info->expand_register.voltage_mask, regval_expand); 535 536 if (regval_expand & info->expand_register.voltage_mask) 537 return info->expand_register.voltage_limit; 538 539 ret = abx500_get_register_interruptible(info->dev, 540 info->voltage_bank, info->voltage_reg, ®val); 541 if (ret < 0) { 542 dev_err(rdev_get_dev(rdev), 543 "couldn't read voltage reg for regulator\n"); 544 return ret; 545 } 546 547 dev_vdbg(rdev_get_dev(rdev), 548 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 549 info->desc.name, info->voltage_bank, info->voltage_reg, 550 info->voltage_mask, regval); 551 552 voltage_shift = ffs(info->voltage_mask) - 1; 553 554 return (regval & info->voltage_mask) >> voltage_shift; 555 } 556 557 static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev, 558 unsigned selector) 559 { 560 int ret, voltage_shift; 561 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 562 u8 regval; 563 564 if (info == NULL) { 565 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 566 return -EINVAL; 567 } 568 569 voltage_shift = ffs(info->voltage_mask) - 1; 570 571 /* set the registers for the request */ 572 regval = (u8)selector << voltage_shift; 573 ret = abx500_mask_and_set_register_interruptible(info->dev, 574 info->voltage_bank, info->voltage_reg, 575 info->voltage_mask, regval); 576 if (ret < 0) 577 dev_err(rdev_get_dev(rdev), 578 "couldn't set voltage reg for regulator\n"); 579 580 dev_vdbg(rdev_get_dev(rdev), 581 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," 582 " 0x%x\n", 583 info->desc.name, info->voltage_bank, info->voltage_reg, 584 info->voltage_mask, regval); 585 586 return ret; 587 } 588 589 static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev, 590 unsigned selector) 591 { 592 int ret; 593 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 594 u8 regval, regval_expand; 595 596 if (info == NULL) { 597 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 598 return -EINVAL; 599 } 600 601 if (selector < info->expand_register.voltage_limit) { 602 int voltage_shift = ffs(info->voltage_mask) - 1; 603 604 regval = (u8)selector << voltage_shift; 605 ret = abx500_mask_and_set_register_interruptible(info->dev, 606 info->voltage_bank, info->voltage_reg, 607 info->voltage_mask, regval); 608 if (ret < 0) { 609 dev_err(rdev_get_dev(rdev), 610 "couldn't set voltage reg for regulator\n"); 611 return ret; 612 } 613 614 dev_vdbg(rdev_get_dev(rdev), 615 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 616 info->desc.name, info->voltage_bank, info->voltage_reg, 617 info->voltage_mask, regval); 618 619 regval_expand = 0; 620 } else { 621 regval_expand = info->expand_register.voltage_mask; 622 } 623 624 ret = abx500_mask_and_set_register_interruptible(info->dev, 625 info->expand_register.voltage_bank, 626 info->expand_register.voltage_reg, 627 info->expand_register.voltage_mask, 628 regval_expand); 629 if (ret < 0) { 630 dev_err(rdev_get_dev(rdev), 631 "couldn't set expand voltage reg for regulator\n"); 632 return ret; 633 } 634 635 dev_vdbg(rdev_get_dev(rdev), 636 "%s-set_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 637 info->desc.name, info->expand_register.voltage_bank, 638 info->expand_register.voltage_reg, 639 info->expand_register.voltage_mask, regval_expand); 640 641 return 0; 642 } 643 644 static struct regulator_ops ab8500_regulator_volt_mode_ops = { 645 .enable = ab8500_regulator_enable, 646 .disable = ab8500_regulator_disable, 647 .is_enabled = ab8500_regulator_is_enabled, 648 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 649 .set_mode = ab8500_regulator_set_mode, 650 .get_mode = ab8500_regulator_get_mode, 651 .get_voltage_sel = ab8500_regulator_get_voltage_sel, 652 .set_voltage_sel = ab8500_regulator_set_voltage_sel, 653 .list_voltage = regulator_list_voltage_table, 654 }; 655 656 static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = { 657 .enable = ab8500_regulator_enable, 658 .disable = ab8500_regulator_disable, 659 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 660 .set_mode = ab8500_regulator_set_mode, 661 .get_mode = ab8500_regulator_get_mode, 662 .is_enabled = ab8500_regulator_is_enabled, 663 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel, 664 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel, 665 .list_voltage = regulator_list_voltage_table, 666 }; 667 668 static struct regulator_ops ab8500_regulator_volt_ops = { 669 .enable = ab8500_regulator_enable, 670 .disable = ab8500_regulator_disable, 671 .is_enabled = ab8500_regulator_is_enabled, 672 .get_voltage_sel = ab8500_regulator_get_voltage_sel, 673 .set_voltage_sel = ab8500_regulator_set_voltage_sel, 674 .list_voltage = regulator_list_voltage_table, 675 }; 676 677 static struct regulator_ops ab8500_regulator_mode_ops = { 678 .enable = ab8500_regulator_enable, 679 .disable = ab8500_regulator_disable, 680 .is_enabled = ab8500_regulator_is_enabled, 681 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 682 .set_mode = ab8500_regulator_set_mode, 683 .get_mode = ab8500_regulator_get_mode, 684 .list_voltage = regulator_list_voltage_table, 685 }; 686 687 static struct regulator_ops ab8500_regulator_ops = { 688 .enable = ab8500_regulator_enable, 689 .disable = ab8500_regulator_disable, 690 .is_enabled = ab8500_regulator_is_enabled, 691 .list_voltage = regulator_list_voltage_table, 692 }; 693 694 static struct regulator_ops ab8500_regulator_anamic_mode_ops = { 695 .enable = ab8500_regulator_enable, 696 .disable = ab8500_regulator_disable, 697 .is_enabled = ab8500_regulator_is_enabled, 698 .set_mode = ab8500_regulator_set_mode, 699 .get_mode = ab8500_regulator_get_mode, 700 .list_voltage = regulator_list_voltage_table, 701 }; 702 703 /* AB8500 regulator information */ 704 static struct ab8500_regulator_info 705 ab8500_regulator_info[AB8500_NUM_REGULATORS] = { 706 /* 707 * Variable Voltage Regulators 708 * name, min mV, max mV, 709 * update bank, reg, mask, enable val 710 * volt bank, reg, mask 711 */ 712 [AB8500_LDO_AUX1] = { 713 .desc = { 714 .name = "LDO-AUX1", 715 .ops = &ab8500_regulator_volt_mode_ops, 716 .type = REGULATOR_VOLTAGE, 717 .id = AB8500_LDO_AUX1, 718 .owner = THIS_MODULE, 719 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 720 .volt_table = ldo_vauxn_voltages, 721 .enable_time = 200, 722 }, 723 .load_lp_uA = 5000, 724 .update_bank = 0x04, 725 .update_reg = 0x09, 726 .update_mask = 0x03, 727 .update_val = 0x01, 728 .update_val_idle = 0x03, 729 .update_val_normal = 0x01, 730 .voltage_bank = 0x04, 731 .voltage_reg = 0x1f, 732 .voltage_mask = 0x0f, 733 }, 734 [AB8500_LDO_AUX2] = { 735 .desc = { 736 .name = "LDO-AUX2", 737 .ops = &ab8500_regulator_volt_mode_ops, 738 .type = REGULATOR_VOLTAGE, 739 .id = AB8500_LDO_AUX2, 740 .owner = THIS_MODULE, 741 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 742 .volt_table = ldo_vauxn_voltages, 743 .enable_time = 200, 744 }, 745 .load_lp_uA = 5000, 746 .update_bank = 0x04, 747 .update_reg = 0x09, 748 .update_mask = 0x0c, 749 .update_val = 0x04, 750 .update_val_idle = 0x0c, 751 .update_val_normal = 0x04, 752 .voltage_bank = 0x04, 753 .voltage_reg = 0x20, 754 .voltage_mask = 0x0f, 755 }, 756 [AB8500_LDO_AUX3] = { 757 .desc = { 758 .name = "LDO-AUX3", 759 .ops = &ab8500_regulator_volt_mode_ops, 760 .type = REGULATOR_VOLTAGE, 761 .id = AB8500_LDO_AUX3, 762 .owner = THIS_MODULE, 763 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 764 .volt_table = ldo_vaux3_voltages, 765 .enable_time = 450, 766 }, 767 .load_lp_uA = 5000, 768 .update_bank = 0x04, 769 .update_reg = 0x0a, 770 .update_mask = 0x03, 771 .update_val = 0x01, 772 .update_val_idle = 0x03, 773 .update_val_normal = 0x01, 774 .voltage_bank = 0x04, 775 .voltage_reg = 0x21, 776 .voltage_mask = 0x07, 777 }, 778 [AB8500_LDO_INTCORE] = { 779 .desc = { 780 .name = "LDO-INTCORE", 781 .ops = &ab8500_regulator_volt_mode_ops, 782 .type = REGULATOR_VOLTAGE, 783 .id = AB8500_LDO_INTCORE, 784 .owner = THIS_MODULE, 785 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 786 .volt_table = ldo_vintcore_voltages, 787 .enable_time = 750, 788 }, 789 .load_lp_uA = 5000, 790 .update_bank = 0x03, 791 .update_reg = 0x80, 792 .update_mask = 0x44, 793 .update_val = 0x44, 794 .update_val_idle = 0x44, 795 .update_val_normal = 0x04, 796 .voltage_bank = 0x03, 797 .voltage_reg = 0x80, 798 .voltage_mask = 0x38, 799 }, 800 801 /* 802 * Fixed Voltage Regulators 803 * name, fixed mV, 804 * update bank, reg, mask, enable val 805 */ 806 [AB8500_LDO_TVOUT] = { 807 .desc = { 808 .name = "LDO-TVOUT", 809 .ops = &ab8500_regulator_mode_ops, 810 .type = REGULATOR_VOLTAGE, 811 .id = AB8500_LDO_TVOUT, 812 .owner = THIS_MODULE, 813 .n_voltages = 1, 814 .volt_table = fixed_2000000_voltage, 815 .enable_time = 500, 816 }, 817 .load_lp_uA = 1000, 818 .update_bank = 0x03, 819 .update_reg = 0x80, 820 .update_mask = 0x82, 821 .update_val = 0x02, 822 .update_val_idle = 0x82, 823 .update_val_normal = 0x02, 824 }, 825 [AB8500_LDO_AUDIO] = { 826 .desc = { 827 .name = "LDO-AUDIO", 828 .ops = &ab8500_regulator_ops, 829 .type = REGULATOR_VOLTAGE, 830 .id = AB8500_LDO_AUDIO, 831 .owner = THIS_MODULE, 832 .n_voltages = 1, 833 .enable_time = 140, 834 .volt_table = fixed_2000000_voltage, 835 }, 836 .update_bank = 0x03, 837 .update_reg = 0x83, 838 .update_mask = 0x02, 839 .update_val = 0x02, 840 }, 841 [AB8500_LDO_ANAMIC1] = { 842 .desc = { 843 .name = "LDO-ANAMIC1", 844 .ops = &ab8500_regulator_ops, 845 .type = REGULATOR_VOLTAGE, 846 .id = AB8500_LDO_ANAMIC1, 847 .owner = THIS_MODULE, 848 .n_voltages = 1, 849 .enable_time = 500, 850 .volt_table = fixed_2050000_voltage, 851 }, 852 .update_bank = 0x03, 853 .update_reg = 0x83, 854 .update_mask = 0x08, 855 .update_val = 0x08, 856 }, 857 [AB8500_LDO_ANAMIC2] = { 858 .desc = { 859 .name = "LDO-ANAMIC2", 860 .ops = &ab8500_regulator_ops, 861 .type = REGULATOR_VOLTAGE, 862 .id = AB8500_LDO_ANAMIC2, 863 .owner = THIS_MODULE, 864 .n_voltages = 1, 865 .enable_time = 500, 866 .volt_table = fixed_2050000_voltage, 867 }, 868 .update_bank = 0x03, 869 .update_reg = 0x83, 870 .update_mask = 0x10, 871 .update_val = 0x10, 872 }, 873 [AB8500_LDO_DMIC] = { 874 .desc = { 875 .name = "LDO-DMIC", 876 .ops = &ab8500_regulator_ops, 877 .type = REGULATOR_VOLTAGE, 878 .id = AB8500_LDO_DMIC, 879 .owner = THIS_MODULE, 880 .n_voltages = 1, 881 .enable_time = 420, 882 .volt_table = fixed_1800000_voltage, 883 }, 884 .update_bank = 0x03, 885 .update_reg = 0x83, 886 .update_mask = 0x04, 887 .update_val = 0x04, 888 }, 889 890 /* 891 * Regulators with fixed voltage and normal/idle modes 892 */ 893 [AB8500_LDO_ANA] = { 894 .desc = { 895 .name = "LDO-ANA", 896 .ops = &ab8500_regulator_mode_ops, 897 .type = REGULATOR_VOLTAGE, 898 .id = AB8500_LDO_ANA, 899 .owner = THIS_MODULE, 900 .n_voltages = 1, 901 .enable_time = 140, 902 .volt_table = fixed_1200000_voltage, 903 }, 904 .load_lp_uA = 1000, 905 .update_bank = 0x04, 906 .update_reg = 0x06, 907 .update_mask = 0x0c, 908 .update_val = 0x04, 909 .update_val_idle = 0x0c, 910 .update_val_normal = 0x04, 911 }, 912 }; 913 914 /* AB8505 regulator information */ 915 static struct ab8500_regulator_info 916 ab8505_regulator_info[AB8505_NUM_REGULATORS] = { 917 /* 918 * Variable Voltage Regulators 919 * name, min mV, max mV, 920 * update bank, reg, mask, enable val 921 * volt bank, reg, mask 922 */ 923 [AB8505_LDO_AUX1] = { 924 .desc = { 925 .name = "LDO-AUX1", 926 .ops = &ab8500_regulator_volt_mode_ops, 927 .type = REGULATOR_VOLTAGE, 928 .id = AB8505_LDO_AUX1, 929 .owner = THIS_MODULE, 930 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 931 .volt_table = ldo_vauxn_voltages, 932 }, 933 .load_lp_uA = 5000, 934 .update_bank = 0x04, 935 .update_reg = 0x09, 936 .update_mask = 0x03, 937 .update_val = 0x01, 938 .update_val_idle = 0x03, 939 .update_val_normal = 0x01, 940 .voltage_bank = 0x04, 941 .voltage_reg = 0x1f, 942 .voltage_mask = 0x0f, 943 }, 944 [AB8505_LDO_AUX2] = { 945 .desc = { 946 .name = "LDO-AUX2", 947 .ops = &ab8500_regulator_volt_mode_ops, 948 .type = REGULATOR_VOLTAGE, 949 .id = AB8505_LDO_AUX2, 950 .owner = THIS_MODULE, 951 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 952 .volt_table = ldo_vauxn_voltages, 953 }, 954 .load_lp_uA = 5000, 955 .update_bank = 0x04, 956 .update_reg = 0x09, 957 .update_mask = 0x0c, 958 .update_val = 0x04, 959 .update_val_idle = 0x0c, 960 .update_val_normal = 0x04, 961 .voltage_bank = 0x04, 962 .voltage_reg = 0x20, 963 .voltage_mask = 0x0f, 964 }, 965 [AB8505_LDO_AUX3] = { 966 .desc = { 967 .name = "LDO-AUX3", 968 .ops = &ab8500_regulator_volt_mode_ops, 969 .type = REGULATOR_VOLTAGE, 970 .id = AB8505_LDO_AUX3, 971 .owner = THIS_MODULE, 972 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 973 .volt_table = ldo_vaux3_voltages, 974 }, 975 .load_lp_uA = 5000, 976 .update_bank = 0x04, 977 .update_reg = 0x0a, 978 .update_mask = 0x03, 979 .update_val = 0x01, 980 .update_val_idle = 0x03, 981 .update_val_normal = 0x01, 982 .voltage_bank = 0x04, 983 .voltage_reg = 0x21, 984 .voltage_mask = 0x07, 985 }, 986 [AB8505_LDO_AUX4] = { 987 .desc = { 988 .name = "LDO-AUX4", 989 .ops = &ab8500_regulator_volt_mode_ops, 990 .type = REGULATOR_VOLTAGE, 991 .id = AB8505_LDO_AUX4, 992 .owner = THIS_MODULE, 993 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 994 .volt_table = ldo_vauxn_voltages, 995 }, 996 .load_lp_uA = 5000, 997 /* values for Vaux4Regu register */ 998 .update_bank = 0x04, 999 .update_reg = 0x2e, 1000 .update_mask = 0x03, 1001 .update_val = 0x01, 1002 .update_val_idle = 0x03, 1003 .update_val_normal = 0x01, 1004 /* values for Vaux4SEL register */ 1005 .voltage_bank = 0x04, 1006 .voltage_reg = 0x2f, 1007 .voltage_mask = 0x0f, 1008 }, 1009 [AB8505_LDO_AUX5] = { 1010 .desc = { 1011 .name = "LDO-AUX5", 1012 .ops = &ab8500_regulator_volt_mode_ops, 1013 .type = REGULATOR_VOLTAGE, 1014 .id = AB8505_LDO_AUX5, 1015 .owner = THIS_MODULE, 1016 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), 1017 .volt_table = ldo_vaux56_voltages, 1018 }, 1019 .load_lp_uA = 2000, 1020 /* values for CtrlVaux5 register */ 1021 .update_bank = 0x01, 1022 .update_reg = 0x55, 1023 .update_mask = 0x18, 1024 .update_val = 0x10, 1025 .update_val_idle = 0x18, 1026 .update_val_normal = 0x10, 1027 .voltage_bank = 0x01, 1028 .voltage_reg = 0x55, 1029 .voltage_mask = 0x07, 1030 }, 1031 [AB8505_LDO_AUX6] = { 1032 .desc = { 1033 .name = "LDO-AUX6", 1034 .ops = &ab8500_regulator_volt_mode_ops, 1035 .type = REGULATOR_VOLTAGE, 1036 .id = AB8505_LDO_AUX6, 1037 .owner = THIS_MODULE, 1038 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), 1039 .volt_table = ldo_vaux56_voltages, 1040 }, 1041 .load_lp_uA = 2000, 1042 /* values for CtrlVaux6 register */ 1043 .update_bank = 0x01, 1044 .update_reg = 0x56, 1045 .update_mask = 0x18, 1046 .update_val = 0x10, 1047 .update_val_idle = 0x18, 1048 .update_val_normal = 0x10, 1049 .voltage_bank = 0x01, 1050 .voltage_reg = 0x56, 1051 .voltage_mask = 0x07, 1052 }, 1053 [AB8505_LDO_INTCORE] = { 1054 .desc = { 1055 .name = "LDO-INTCORE", 1056 .ops = &ab8500_regulator_volt_mode_ops, 1057 .type = REGULATOR_VOLTAGE, 1058 .id = AB8505_LDO_INTCORE, 1059 .owner = THIS_MODULE, 1060 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 1061 .volt_table = ldo_vintcore_voltages, 1062 }, 1063 .load_lp_uA = 5000, 1064 .update_bank = 0x03, 1065 .update_reg = 0x80, 1066 .update_mask = 0x44, 1067 .update_val = 0x04, 1068 .update_val_idle = 0x44, 1069 .update_val_normal = 0x04, 1070 .voltage_bank = 0x03, 1071 .voltage_reg = 0x80, 1072 .voltage_mask = 0x38, 1073 }, 1074 1075 /* 1076 * Fixed Voltage Regulators 1077 * name, fixed mV, 1078 * update bank, reg, mask, enable val 1079 */ 1080 [AB8505_LDO_ADC] = { 1081 .desc = { 1082 .name = "LDO-ADC", 1083 .ops = &ab8500_regulator_mode_ops, 1084 .type = REGULATOR_VOLTAGE, 1085 .id = AB8505_LDO_ADC, 1086 .owner = THIS_MODULE, 1087 .n_voltages = 1, 1088 .volt_table = fixed_2000000_voltage, 1089 .enable_time = 10000, 1090 }, 1091 .load_lp_uA = 1000, 1092 .update_bank = 0x03, 1093 .update_reg = 0x80, 1094 .update_mask = 0x82, 1095 .update_val = 0x02, 1096 .update_val_idle = 0x82, 1097 .update_val_normal = 0x02, 1098 }, 1099 [AB8505_LDO_USB] = { 1100 .desc = { 1101 .name = "LDO-USB", 1102 .ops = &ab8500_regulator_mode_ops, 1103 .type = REGULATOR_VOLTAGE, 1104 .id = AB8505_LDO_USB, 1105 .owner = THIS_MODULE, 1106 .n_voltages = 1, 1107 .volt_table = fixed_3300000_voltage, 1108 }, 1109 .update_bank = 0x03, 1110 .update_reg = 0x82, 1111 .update_mask = 0x03, 1112 .update_val = 0x01, 1113 .update_val_idle = 0x03, 1114 .update_val_normal = 0x01, 1115 }, 1116 [AB8505_LDO_AUDIO] = { 1117 .desc = { 1118 .name = "LDO-AUDIO", 1119 .ops = &ab8500_regulator_volt_ops, 1120 .type = REGULATOR_VOLTAGE, 1121 .id = AB8505_LDO_AUDIO, 1122 .owner = THIS_MODULE, 1123 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages), 1124 .volt_table = ldo_vaudio_voltages, 1125 }, 1126 .update_bank = 0x03, 1127 .update_reg = 0x83, 1128 .update_mask = 0x02, 1129 .update_val = 0x02, 1130 .voltage_bank = 0x01, 1131 .voltage_reg = 0x57, 1132 .voltage_mask = 0x70, 1133 }, 1134 [AB8505_LDO_ANAMIC1] = { 1135 .desc = { 1136 .name = "LDO-ANAMIC1", 1137 .ops = &ab8500_regulator_anamic_mode_ops, 1138 .type = REGULATOR_VOLTAGE, 1139 .id = AB8505_LDO_ANAMIC1, 1140 .owner = THIS_MODULE, 1141 .n_voltages = 1, 1142 .volt_table = fixed_2050000_voltage, 1143 }, 1144 .shared_mode = &ldo_anamic1_shared, 1145 .update_bank = 0x03, 1146 .update_reg = 0x83, 1147 .update_mask = 0x08, 1148 .update_val = 0x08, 1149 .mode_bank = 0x01, 1150 .mode_reg = 0x54, 1151 .mode_mask = 0x04, 1152 .mode_val_idle = 0x04, 1153 .mode_val_normal = 0x00, 1154 }, 1155 [AB8505_LDO_ANAMIC2] = { 1156 .desc = { 1157 .name = "LDO-ANAMIC2", 1158 .ops = &ab8500_regulator_anamic_mode_ops, 1159 .type = REGULATOR_VOLTAGE, 1160 .id = AB8505_LDO_ANAMIC2, 1161 .owner = THIS_MODULE, 1162 .n_voltages = 1, 1163 .volt_table = fixed_2050000_voltage, 1164 }, 1165 .shared_mode = &ldo_anamic2_shared, 1166 .update_bank = 0x03, 1167 .update_reg = 0x83, 1168 .update_mask = 0x10, 1169 .update_val = 0x10, 1170 .mode_bank = 0x01, 1171 .mode_reg = 0x54, 1172 .mode_mask = 0x04, 1173 .mode_val_idle = 0x04, 1174 .mode_val_normal = 0x00, 1175 }, 1176 [AB8505_LDO_AUX8] = { 1177 .desc = { 1178 .name = "LDO-AUX8", 1179 .ops = &ab8500_regulator_ops, 1180 .type = REGULATOR_VOLTAGE, 1181 .id = AB8505_LDO_AUX8, 1182 .owner = THIS_MODULE, 1183 .n_voltages = 1, 1184 .volt_table = fixed_1800000_voltage, 1185 }, 1186 .update_bank = 0x03, 1187 .update_reg = 0x83, 1188 .update_mask = 0x04, 1189 .update_val = 0x04, 1190 }, 1191 /* 1192 * Regulators with fixed voltage and normal/idle modes 1193 */ 1194 [AB8505_LDO_ANA] = { 1195 .desc = { 1196 .name = "LDO-ANA", 1197 .ops = &ab8500_regulator_volt_mode_ops, 1198 .type = REGULATOR_VOLTAGE, 1199 .id = AB8505_LDO_ANA, 1200 .owner = THIS_MODULE, 1201 .n_voltages = ARRAY_SIZE(ldo_vana_voltages), 1202 .volt_table = ldo_vana_voltages, 1203 }, 1204 .load_lp_uA = 1000, 1205 .update_bank = 0x04, 1206 .update_reg = 0x06, 1207 .update_mask = 0x0c, 1208 .update_val = 0x04, 1209 .update_val_idle = 0x0c, 1210 .update_val_normal = 0x04, 1211 .voltage_bank = 0x04, 1212 .voltage_reg = 0x29, 1213 .voltage_mask = 0x7, 1214 }, 1215 }; 1216 1217 /* AB9540 regulator information */ 1218 static struct ab8500_regulator_info 1219 ab9540_regulator_info[AB9540_NUM_REGULATORS] = { 1220 /* 1221 * Variable Voltage Regulators 1222 * name, min mV, max mV, 1223 * update bank, reg, mask, enable val 1224 * volt bank, reg, mask 1225 */ 1226 [AB9540_LDO_AUX1] = { 1227 .desc = { 1228 .name = "LDO-AUX1", 1229 .ops = &ab8500_regulator_volt_mode_ops, 1230 .type = REGULATOR_VOLTAGE, 1231 .id = AB9540_LDO_AUX1, 1232 .owner = THIS_MODULE, 1233 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 1234 .volt_table = ldo_vauxn_voltages, 1235 }, 1236 .load_lp_uA = 5000, 1237 .update_bank = 0x04, 1238 .update_reg = 0x09, 1239 .update_mask = 0x03, 1240 .update_val = 0x01, 1241 .update_val_idle = 0x03, 1242 .update_val_normal = 0x01, 1243 .voltage_bank = 0x04, 1244 .voltage_reg = 0x1f, 1245 .voltage_mask = 0x0f, 1246 }, 1247 [AB9540_LDO_AUX2] = { 1248 .desc = { 1249 .name = "LDO-AUX2", 1250 .ops = &ab8500_regulator_volt_mode_ops, 1251 .type = REGULATOR_VOLTAGE, 1252 .id = AB9540_LDO_AUX2, 1253 .owner = THIS_MODULE, 1254 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 1255 .volt_table = ldo_vauxn_voltages, 1256 }, 1257 .load_lp_uA = 5000, 1258 .update_bank = 0x04, 1259 .update_reg = 0x09, 1260 .update_mask = 0x0c, 1261 .update_val = 0x04, 1262 .update_val_idle = 0x0c, 1263 .update_val_normal = 0x04, 1264 .voltage_bank = 0x04, 1265 .voltage_reg = 0x20, 1266 .voltage_mask = 0x0f, 1267 }, 1268 [AB9540_LDO_AUX3] = { 1269 .desc = { 1270 .name = "LDO-AUX3", 1271 .ops = &ab8500_regulator_volt_mode_ops, 1272 .type = REGULATOR_VOLTAGE, 1273 .id = AB9540_LDO_AUX3, 1274 .owner = THIS_MODULE, 1275 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 1276 .volt_table = ldo_vaux3_voltages, 1277 }, 1278 .load_lp_uA = 5000, 1279 .update_bank = 0x04, 1280 .update_reg = 0x0a, 1281 .update_mask = 0x03, 1282 .update_val = 0x01, 1283 .update_val_idle = 0x03, 1284 .update_val_normal = 0x01, 1285 .voltage_bank = 0x04, 1286 .voltage_reg = 0x21, 1287 .voltage_mask = 0x07, 1288 }, 1289 [AB9540_LDO_AUX4] = { 1290 .desc = { 1291 .name = "LDO-AUX4", 1292 .ops = &ab8500_regulator_volt_mode_ops, 1293 .type = REGULATOR_VOLTAGE, 1294 .id = AB9540_LDO_AUX4, 1295 .owner = THIS_MODULE, 1296 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 1297 .volt_table = ldo_vauxn_voltages, 1298 }, 1299 .load_lp_uA = 5000, 1300 /* values for Vaux4Regu register */ 1301 .update_bank = 0x04, 1302 .update_reg = 0x2e, 1303 .update_mask = 0x03, 1304 .update_val = 0x01, 1305 .update_val_idle = 0x03, 1306 .update_val_normal = 0x01, 1307 /* values for Vaux4SEL register */ 1308 .voltage_bank = 0x04, 1309 .voltage_reg = 0x2f, 1310 .voltage_mask = 0x0f, 1311 }, 1312 [AB9540_LDO_INTCORE] = { 1313 .desc = { 1314 .name = "LDO-INTCORE", 1315 .ops = &ab8500_regulator_volt_mode_ops, 1316 .type = REGULATOR_VOLTAGE, 1317 .id = AB9540_LDO_INTCORE, 1318 .owner = THIS_MODULE, 1319 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 1320 .volt_table = ldo_vintcore_voltages, 1321 }, 1322 .load_lp_uA = 5000, 1323 .update_bank = 0x03, 1324 .update_reg = 0x80, 1325 .update_mask = 0x44, 1326 .update_val = 0x44, 1327 .update_val_idle = 0x44, 1328 .update_val_normal = 0x04, 1329 .voltage_bank = 0x03, 1330 .voltage_reg = 0x80, 1331 .voltage_mask = 0x38, 1332 }, 1333 1334 /* 1335 * Fixed Voltage Regulators 1336 * name, fixed mV, 1337 * update bank, reg, mask, enable val 1338 */ 1339 [AB9540_LDO_TVOUT] = { 1340 .desc = { 1341 .name = "LDO-TVOUT", 1342 .ops = &ab8500_regulator_mode_ops, 1343 .type = REGULATOR_VOLTAGE, 1344 .id = AB9540_LDO_TVOUT, 1345 .owner = THIS_MODULE, 1346 .n_voltages = 1, 1347 .volt_table = fixed_2000000_voltage, 1348 .enable_time = 10000, 1349 }, 1350 .load_lp_uA = 1000, 1351 .update_bank = 0x03, 1352 .update_reg = 0x80, 1353 .update_mask = 0x82, 1354 .update_val = 0x02, 1355 .update_val_idle = 0x82, 1356 .update_val_normal = 0x02, 1357 }, 1358 [AB9540_LDO_USB] = { 1359 .desc = { 1360 .name = "LDO-USB", 1361 .ops = &ab8500_regulator_ops, 1362 .type = REGULATOR_VOLTAGE, 1363 .id = AB9540_LDO_USB, 1364 .owner = THIS_MODULE, 1365 .n_voltages = 1, 1366 .volt_table = fixed_3300000_voltage, 1367 }, 1368 .update_bank = 0x03, 1369 .update_reg = 0x82, 1370 .update_mask = 0x03, 1371 .update_val = 0x01, 1372 .update_val_idle = 0x03, 1373 .update_val_normal = 0x01, 1374 }, 1375 [AB9540_LDO_AUDIO] = { 1376 .desc = { 1377 .name = "LDO-AUDIO", 1378 .ops = &ab8500_regulator_ops, 1379 .type = REGULATOR_VOLTAGE, 1380 .id = AB9540_LDO_AUDIO, 1381 .owner = THIS_MODULE, 1382 .n_voltages = 1, 1383 .volt_table = fixed_2000000_voltage, 1384 }, 1385 .update_bank = 0x03, 1386 .update_reg = 0x83, 1387 .update_mask = 0x02, 1388 .update_val = 0x02, 1389 }, 1390 [AB9540_LDO_ANAMIC1] = { 1391 .desc = { 1392 .name = "LDO-ANAMIC1", 1393 .ops = &ab8500_regulator_ops, 1394 .type = REGULATOR_VOLTAGE, 1395 .id = AB9540_LDO_ANAMIC1, 1396 .owner = THIS_MODULE, 1397 .n_voltages = 1, 1398 .volt_table = fixed_2050000_voltage, 1399 }, 1400 .update_bank = 0x03, 1401 .update_reg = 0x83, 1402 .update_mask = 0x08, 1403 .update_val = 0x08, 1404 }, 1405 [AB9540_LDO_ANAMIC2] = { 1406 .desc = { 1407 .name = "LDO-ANAMIC2", 1408 .ops = &ab8500_regulator_ops, 1409 .type = REGULATOR_VOLTAGE, 1410 .id = AB9540_LDO_ANAMIC2, 1411 .owner = THIS_MODULE, 1412 .n_voltages = 1, 1413 .volt_table = fixed_2050000_voltage, 1414 }, 1415 .update_bank = 0x03, 1416 .update_reg = 0x83, 1417 .update_mask = 0x10, 1418 .update_val = 0x10, 1419 }, 1420 [AB9540_LDO_DMIC] = { 1421 .desc = { 1422 .name = "LDO-DMIC", 1423 .ops = &ab8500_regulator_ops, 1424 .type = REGULATOR_VOLTAGE, 1425 .id = AB9540_LDO_DMIC, 1426 .owner = THIS_MODULE, 1427 .n_voltages = 1, 1428 .volt_table = fixed_1800000_voltage, 1429 }, 1430 .update_bank = 0x03, 1431 .update_reg = 0x83, 1432 .update_mask = 0x04, 1433 .update_val = 0x04, 1434 }, 1435 1436 /* 1437 * Regulators with fixed voltage and normal/idle modes 1438 */ 1439 [AB9540_LDO_ANA] = { 1440 .desc = { 1441 .name = "LDO-ANA", 1442 .ops = &ab8500_regulator_mode_ops, 1443 .type = REGULATOR_VOLTAGE, 1444 .id = AB9540_LDO_ANA, 1445 .owner = THIS_MODULE, 1446 .n_voltages = 1, 1447 .volt_table = fixed_1200000_voltage, 1448 }, 1449 .load_lp_uA = 1000, 1450 .update_bank = 0x04, 1451 .update_reg = 0x06, 1452 .update_mask = 0x0c, 1453 .update_val = 0x08, 1454 .update_val_idle = 0x0c, 1455 .update_val_normal = 0x08, 1456 }, 1457 }; 1458 1459 /* AB8540 regulator information */ 1460 static struct ab8500_regulator_info 1461 ab8540_regulator_info[AB8540_NUM_REGULATORS] = { 1462 /* 1463 * Variable Voltage Regulators 1464 * name, min mV, max mV, 1465 * update bank, reg, mask, enable val 1466 * volt bank, reg, mask 1467 */ 1468 [AB8540_LDO_AUX1] = { 1469 .desc = { 1470 .name = "LDO-AUX1", 1471 .ops = &ab8500_regulator_volt_mode_ops, 1472 .type = REGULATOR_VOLTAGE, 1473 .id = AB8540_LDO_AUX1, 1474 .owner = THIS_MODULE, 1475 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 1476 .volt_table = ldo_vauxn_voltages, 1477 }, 1478 .load_lp_uA = 5000, 1479 .update_bank = 0x04, 1480 .update_reg = 0x09, 1481 .update_mask = 0x03, 1482 .update_val = 0x01, 1483 .update_val_idle = 0x03, 1484 .update_val_normal = 0x01, 1485 .voltage_bank = 0x04, 1486 .voltage_reg = 0x1f, 1487 .voltage_mask = 0x0f, 1488 }, 1489 [AB8540_LDO_AUX2] = { 1490 .desc = { 1491 .name = "LDO-AUX2", 1492 .ops = &ab8500_regulator_volt_mode_ops, 1493 .type = REGULATOR_VOLTAGE, 1494 .id = AB8540_LDO_AUX2, 1495 .owner = THIS_MODULE, 1496 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 1497 .volt_table = ldo_vauxn_voltages, 1498 }, 1499 .load_lp_uA = 5000, 1500 .update_bank = 0x04, 1501 .update_reg = 0x09, 1502 .update_mask = 0x0c, 1503 .update_val = 0x04, 1504 .update_val_idle = 0x0c, 1505 .update_val_normal = 0x04, 1506 .voltage_bank = 0x04, 1507 .voltage_reg = 0x20, 1508 .voltage_mask = 0x0f, 1509 }, 1510 [AB8540_LDO_AUX3] = { 1511 .desc = { 1512 .name = "LDO-AUX3", 1513 .ops = &ab8540_aux3_regulator_volt_mode_ops, 1514 .type = REGULATOR_VOLTAGE, 1515 .id = AB8540_LDO_AUX3, 1516 .owner = THIS_MODULE, 1517 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages), 1518 .volt_table = ldo_vaux3_ab8540_voltages, 1519 }, 1520 .load_lp_uA = 5000, 1521 .update_bank = 0x04, 1522 .update_reg = 0x0a, 1523 .update_mask = 0x03, 1524 .update_val = 0x01, 1525 .update_val_idle = 0x03, 1526 .update_val_normal = 0x01, 1527 .voltage_bank = 0x04, 1528 .voltage_reg = 0x21, 1529 .voltage_mask = 0x07, 1530 .expand_register = { 1531 .voltage_limit = 8, 1532 .voltage_bank = 0x04, 1533 .voltage_reg = 0x01, 1534 .voltage_mask = 0x10, 1535 } 1536 }, 1537 [AB8540_LDO_AUX4] = { 1538 .desc = { 1539 .name = "LDO-AUX4", 1540 .ops = &ab8500_regulator_volt_mode_ops, 1541 .type = REGULATOR_VOLTAGE, 1542 .id = AB8540_LDO_AUX4, 1543 .owner = THIS_MODULE, 1544 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 1545 .volt_table = ldo_vauxn_voltages, 1546 }, 1547 .load_lp_uA = 5000, 1548 /* values for Vaux4Regu register */ 1549 .update_bank = 0x04, 1550 .update_reg = 0x2e, 1551 .update_mask = 0x03, 1552 .update_val = 0x01, 1553 .update_val_idle = 0x03, 1554 .update_val_normal = 0x01, 1555 /* values for Vaux4SEL register */ 1556 .voltage_bank = 0x04, 1557 .voltage_reg = 0x2f, 1558 .voltage_mask = 0x0f, 1559 }, 1560 [AB8540_LDO_AUX5] = { 1561 .desc = { 1562 .name = "LDO-AUX5", 1563 .ops = &ab8500_regulator_volt_mode_ops, 1564 .type = REGULATOR_VOLTAGE, 1565 .id = AB8540_LDO_AUX5, 1566 .owner = THIS_MODULE, 1567 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages), 1568 .volt_table = ldo_vaux56_ab8540_voltages, 1569 }, 1570 .load_lp_uA = 20000, 1571 /* values for Vaux5Regu register */ 1572 .update_bank = 0x04, 1573 .update_reg = 0x32, 1574 .update_mask = 0x03, 1575 .update_val = 0x01, 1576 .update_val_idle = 0x03, 1577 .update_val_normal = 0x01, 1578 /* values for Vaux5SEL register */ 1579 .voltage_bank = 0x04, 1580 .voltage_reg = 0x33, 1581 .voltage_mask = 0x3f, 1582 }, 1583 [AB8540_LDO_AUX6] = { 1584 .desc = { 1585 .name = "LDO-AUX6", 1586 .ops = &ab8500_regulator_volt_mode_ops, 1587 .type = REGULATOR_VOLTAGE, 1588 .id = AB8540_LDO_AUX6, 1589 .owner = THIS_MODULE, 1590 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages), 1591 .volt_table = ldo_vaux56_ab8540_voltages, 1592 }, 1593 .load_lp_uA = 20000, 1594 /* values for Vaux6Regu register */ 1595 .update_bank = 0x04, 1596 .update_reg = 0x35, 1597 .update_mask = 0x03, 1598 .update_val = 0x01, 1599 .update_val_idle = 0x03, 1600 .update_val_normal = 0x01, 1601 /* values for Vaux6SEL register */ 1602 .voltage_bank = 0x04, 1603 .voltage_reg = 0x36, 1604 .voltage_mask = 0x3f, 1605 }, 1606 [AB8540_LDO_INTCORE] = { 1607 .desc = { 1608 .name = "LDO-INTCORE", 1609 .ops = &ab8500_regulator_volt_mode_ops, 1610 .type = REGULATOR_VOLTAGE, 1611 .id = AB8540_LDO_INTCORE, 1612 .owner = THIS_MODULE, 1613 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 1614 .volt_table = ldo_vintcore_voltages, 1615 }, 1616 .load_lp_uA = 5000, 1617 .update_bank = 0x03, 1618 .update_reg = 0x80, 1619 .update_mask = 0x44, 1620 .update_val = 0x44, 1621 .update_val_idle = 0x44, 1622 .update_val_normal = 0x04, 1623 .voltage_bank = 0x03, 1624 .voltage_reg = 0x80, 1625 .voltage_mask = 0x38, 1626 }, 1627 1628 /* 1629 * Fixed Voltage Regulators 1630 * name, fixed mV, 1631 * update bank, reg, mask, enable val 1632 */ 1633 [AB8540_LDO_TVOUT] = { 1634 .desc = { 1635 .name = "LDO-TVOUT", 1636 .ops = &ab8500_regulator_mode_ops, 1637 .type = REGULATOR_VOLTAGE, 1638 .id = AB8540_LDO_TVOUT, 1639 .owner = THIS_MODULE, 1640 .n_voltages = 1, 1641 .volt_table = fixed_2000000_voltage, 1642 .enable_time = 10000, 1643 }, 1644 .load_lp_uA = 1000, 1645 .update_bank = 0x03, 1646 .update_reg = 0x80, 1647 .update_mask = 0x82, 1648 .update_val = 0x02, 1649 .update_val_idle = 0x82, 1650 .update_val_normal = 0x02, 1651 }, 1652 [AB8540_LDO_AUDIO] = { 1653 .desc = { 1654 .name = "LDO-AUDIO", 1655 .ops = &ab8500_regulator_ops, 1656 .type = REGULATOR_VOLTAGE, 1657 .id = AB8540_LDO_AUDIO, 1658 .owner = THIS_MODULE, 1659 .n_voltages = 1, 1660 .volt_table = fixed_2000000_voltage, 1661 }, 1662 .update_bank = 0x03, 1663 .update_reg = 0x83, 1664 .update_mask = 0x02, 1665 .update_val = 0x02, 1666 }, 1667 [AB8540_LDO_ANAMIC1] = { 1668 .desc = { 1669 .name = "LDO-ANAMIC1", 1670 .ops = &ab8500_regulator_anamic_mode_ops, 1671 .type = REGULATOR_VOLTAGE, 1672 .id = AB8540_LDO_ANAMIC1, 1673 .owner = THIS_MODULE, 1674 .n_voltages = 1, 1675 .volt_table = fixed_2050000_voltage, 1676 }, 1677 .shared_mode = &ab8540_ldo_anamic1_shared, 1678 .update_bank = 0x03, 1679 .update_reg = 0x83, 1680 .update_mask = 0x08, 1681 .update_val = 0x08, 1682 .mode_bank = 0x03, 1683 .mode_reg = 0x83, 1684 .mode_mask = 0x20, 1685 .mode_val_idle = 0x20, 1686 .mode_val_normal = 0x00, 1687 }, 1688 [AB8540_LDO_ANAMIC2] = { 1689 .desc = { 1690 .name = "LDO-ANAMIC2", 1691 .ops = &ab8500_regulator_anamic_mode_ops, 1692 .type = REGULATOR_VOLTAGE, 1693 .id = AB8540_LDO_ANAMIC2, 1694 .owner = THIS_MODULE, 1695 .n_voltages = 1, 1696 .volt_table = fixed_2050000_voltage, 1697 }, 1698 .shared_mode = &ab8540_ldo_anamic2_shared, 1699 .update_bank = 0x03, 1700 .update_reg = 0x83, 1701 .update_mask = 0x10, 1702 .update_val = 0x10, 1703 .mode_bank = 0x03, 1704 .mode_reg = 0x83, 1705 .mode_mask = 0x20, 1706 .mode_val_idle = 0x20, 1707 .mode_val_normal = 0x00, 1708 }, 1709 [AB8540_LDO_DMIC] = { 1710 .desc = { 1711 .name = "LDO-DMIC", 1712 .ops = &ab8500_regulator_volt_mode_ops, 1713 .type = REGULATOR_VOLTAGE, 1714 .id = AB8540_LDO_DMIC, 1715 .owner = THIS_MODULE, 1716 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages), 1717 .volt_table = ldo_vdmic_voltages, 1718 }, 1719 .load_lp_uA = 1000, 1720 .update_bank = 0x03, 1721 .update_reg = 0x83, 1722 .update_mask = 0x04, 1723 .update_val = 0x04, 1724 .voltage_bank = 0x03, 1725 .voltage_reg = 0x83, 1726 .voltage_mask = 0xc0, 1727 }, 1728 1729 /* 1730 * Regulators with fixed voltage and normal/idle modes 1731 */ 1732 [AB8540_LDO_ANA] = { 1733 .desc = { 1734 .name = "LDO-ANA", 1735 .ops = &ab8500_regulator_mode_ops, 1736 .type = REGULATOR_VOLTAGE, 1737 .id = AB8540_LDO_ANA, 1738 .owner = THIS_MODULE, 1739 .n_voltages = 1, 1740 .volt_table = fixed_1200000_voltage, 1741 }, 1742 .load_lp_uA = 1000, 1743 .update_bank = 0x04, 1744 .update_reg = 0x06, 1745 .update_mask = 0x0c, 1746 .update_val = 0x04, 1747 .update_val_idle = 0x0c, 1748 .update_val_normal = 0x04, 1749 }, 1750 [AB8540_LDO_SDIO] = { 1751 .desc = { 1752 .name = "LDO-SDIO", 1753 .ops = &ab8500_regulator_volt_mode_ops, 1754 .type = REGULATOR_VOLTAGE, 1755 .id = AB8540_LDO_SDIO, 1756 .owner = THIS_MODULE, 1757 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages), 1758 .volt_table = ldo_sdio_voltages, 1759 }, 1760 .load_lp_uA = 5000, 1761 .update_bank = 0x03, 1762 .update_reg = 0x88, 1763 .update_mask = 0x30, 1764 .update_val = 0x10, 1765 .update_val_idle = 0x30, 1766 .update_val_normal = 0x10, 1767 .voltage_bank = 0x03, 1768 .voltage_reg = 0x88, 1769 .voltage_mask = 0x07, 1770 }, 1771 }; 1772 1773 static struct ab8500_shared_mode ldo_anamic1_shared = { 1774 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2], 1775 }; 1776 1777 static struct ab8500_shared_mode ldo_anamic2_shared = { 1778 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1], 1779 }; 1780 1781 static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = { 1782 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2], 1783 }; 1784 1785 static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = { 1786 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1], 1787 }; 1788 1789 struct ab8500_reg_init { 1790 u8 bank; 1791 u8 addr; 1792 u8 mask; 1793 }; 1794 1795 #define REG_INIT(_id, _bank, _addr, _mask) \ 1796 [_id] = { \ 1797 .bank = _bank, \ 1798 .addr = _addr, \ 1799 .mask = _mask, \ 1800 } 1801 1802 /* AB8500 register init */ 1803 static struct ab8500_reg_init ab8500_reg_init[] = { 1804 /* 1805 * 0x30, VanaRequestCtrl 1806 * 0xc0, VextSupply1RequestCtrl 1807 */ 1808 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0), 1809 /* 1810 * 0x03, VextSupply2RequestCtrl 1811 * 0x0c, VextSupply3RequestCtrl 1812 * 0x30, Vaux1RequestCtrl 1813 * 0xc0, Vaux2RequestCtrl 1814 */ 1815 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), 1816 /* 1817 * 0x03, Vaux3RequestCtrl 1818 * 0x04, SwHPReq 1819 */ 1820 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 1821 /* 1822 * 0x08, VanaSysClkReq1HPValid 1823 * 0x20, Vaux1SysClkReq1HPValid 1824 * 0x40, Vaux2SysClkReq1HPValid 1825 * 0x80, Vaux3SysClkReq1HPValid 1826 */ 1827 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8), 1828 /* 1829 * 0x10, VextSupply1SysClkReq1HPValid 1830 * 0x20, VextSupply2SysClkReq1HPValid 1831 * 0x40, VextSupply3SysClkReq1HPValid 1832 */ 1833 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70), 1834 /* 1835 * 0x08, VanaHwHPReq1Valid 1836 * 0x20, Vaux1HwHPReq1Valid 1837 * 0x40, Vaux2HwHPReq1Valid 1838 * 0x80, Vaux3HwHPReq1Valid 1839 */ 1840 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8), 1841 /* 1842 * 0x01, VextSupply1HwHPReq1Valid 1843 * 0x02, VextSupply2HwHPReq1Valid 1844 * 0x04, VextSupply3HwHPReq1Valid 1845 */ 1846 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), 1847 /* 1848 * 0x08, VanaHwHPReq2Valid 1849 * 0x20, Vaux1HwHPReq2Valid 1850 * 0x40, Vaux2HwHPReq2Valid 1851 * 0x80, Vaux3HwHPReq2Valid 1852 */ 1853 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8), 1854 /* 1855 * 0x01, VextSupply1HwHPReq2Valid 1856 * 0x02, VextSupply2HwHPReq2Valid 1857 * 0x04, VextSupply3HwHPReq2Valid 1858 */ 1859 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), 1860 /* 1861 * 0x20, VanaSwHPReqValid 1862 * 0x80, Vaux1SwHPReqValid 1863 */ 1864 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0), 1865 /* 1866 * 0x01, Vaux2SwHPReqValid 1867 * 0x02, Vaux3SwHPReqValid 1868 * 0x04, VextSupply1SwHPReqValid 1869 * 0x08, VextSupply2SwHPReqValid 1870 * 0x10, VextSupply3SwHPReqValid 1871 */ 1872 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), 1873 /* 1874 * 0x02, SysClkReq2Valid1 1875 * 0x04, SysClkReq3Valid1 1876 * 0x08, SysClkReq4Valid1 1877 * 0x10, SysClkReq5Valid1 1878 * 0x20, SysClkReq6Valid1 1879 * 0x40, SysClkReq7Valid1 1880 * 0x80, SysClkReq8Valid1 1881 */ 1882 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), 1883 /* 1884 * 0x02, SysClkReq2Valid2 1885 * 0x04, SysClkReq3Valid2 1886 * 0x08, SysClkReq4Valid2 1887 * 0x10, SysClkReq5Valid2 1888 * 0x20, SysClkReq6Valid2 1889 * 0x40, SysClkReq7Valid2 1890 * 0x80, SysClkReq8Valid2 1891 */ 1892 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), 1893 /* 1894 * 0x02, VTVoutEna 1895 * 0x04, Vintcore12Ena 1896 * 0x38, Vintcore12Sel 1897 * 0x40, Vintcore12LP 1898 * 0x80, VTVoutLP 1899 */ 1900 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe), 1901 /* 1902 * 0x02, VaudioEna 1903 * 0x04, VdmicEna 1904 * 0x08, Vamic1Ena 1905 * 0x10, Vamic2Ena 1906 */ 1907 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 1908 /* 1909 * 0x01, Vamic1_dzout 1910 * 0x02, Vamic2_dzout 1911 */ 1912 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 1913 /* 1914 * 0x03, VpllRegu (NOTE! PRCMU register bits) 1915 * 0x0c, VanaRegu 1916 */ 1917 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f), 1918 /* 1919 * 0x01, VrefDDREna 1920 * 0x02, VrefDDRSleepMode 1921 */ 1922 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03), 1923 /* 1924 * 0x03, VextSupply1Regu 1925 * 0x0c, VextSupply2Regu 1926 * 0x30, VextSupply3Regu 1927 * 0x40, ExtSupply2Bypass 1928 * 0x80, ExtSupply3Bypass 1929 */ 1930 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 1931 /* 1932 * 0x03, Vaux1Regu 1933 * 0x0c, Vaux2Regu 1934 */ 1935 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f), 1936 /* 1937 * 0x03, Vaux3Regu 1938 */ 1939 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03), 1940 /* 1941 * 0x0f, Vaux1Sel 1942 */ 1943 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f), 1944 /* 1945 * 0x0f, Vaux2Sel 1946 */ 1947 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f), 1948 /* 1949 * 0x07, Vaux3Sel 1950 */ 1951 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07), 1952 /* 1953 * 0x01, VextSupply12LP 1954 */ 1955 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01), 1956 /* 1957 * 0x04, Vaux1Disch 1958 * 0x08, Vaux2Disch 1959 * 0x10, Vaux3Disch 1960 * 0x20, Vintcore12Disch 1961 * 0x40, VTVoutDisch 1962 * 0x80, VaudioDisch 1963 */ 1964 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc), 1965 /* 1966 * 0x02, VanaDisch 1967 * 0x04, VdmicPullDownEna 1968 * 0x10, VdmicDisch 1969 */ 1970 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 1971 }; 1972 1973 /* AB8505 register init */ 1974 static struct ab8500_reg_init ab8505_reg_init[] = { 1975 /* 1976 * 0x03, VarmRequestCtrl 1977 * 0x0c, VsmpsCRequestCtrl 1978 * 0x30, VsmpsARequestCtrl 1979 * 0xc0, VsmpsBRequestCtrl 1980 */ 1981 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), 1982 /* 1983 * 0x03, VsafeRequestCtrl 1984 * 0x0c, VpllRequestCtrl 1985 * 0x30, VanaRequestCtrl 1986 */ 1987 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f), 1988 /* 1989 * 0x30, Vaux1RequestCtrl 1990 * 0xc0, Vaux2RequestCtrl 1991 */ 1992 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0), 1993 /* 1994 * 0x03, Vaux3RequestCtrl 1995 * 0x04, SwHPReq 1996 */ 1997 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 1998 /* 1999 * 0x01, VsmpsASysClkReq1HPValid 2000 * 0x02, VsmpsBSysClkReq1HPValid 2001 * 0x04, VsafeSysClkReq1HPValid 2002 * 0x08, VanaSysClkReq1HPValid 2003 * 0x10, VpllSysClkReq1HPValid 2004 * 0x20, Vaux1SysClkReq1HPValid 2005 * 0x40, Vaux2SysClkReq1HPValid 2006 * 0x80, Vaux3SysClkReq1HPValid 2007 */ 2008 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), 2009 /* 2010 * 0x01, VsmpsCSysClkReq1HPValid 2011 * 0x02, VarmSysClkReq1HPValid 2012 * 0x04, VbbSysClkReq1HPValid 2013 * 0x08, VsmpsMSysClkReq1HPValid 2014 */ 2015 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f), 2016 /* 2017 * 0x01, VsmpsAHwHPReq1Valid 2018 * 0x02, VsmpsBHwHPReq1Valid 2019 * 0x04, VsafeHwHPReq1Valid 2020 * 0x08, VanaHwHPReq1Valid 2021 * 0x10, VpllHwHPReq1Valid 2022 * 0x20, Vaux1HwHPReq1Valid 2023 * 0x40, Vaux2HwHPReq1Valid 2024 * 0x80, Vaux3HwHPReq1Valid 2025 */ 2026 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), 2027 /* 2028 * 0x08, VsmpsMHwHPReq1Valid 2029 */ 2030 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08), 2031 /* 2032 * 0x01, VsmpsAHwHPReq2Valid 2033 * 0x02, VsmpsBHwHPReq2Valid 2034 * 0x04, VsafeHwHPReq2Valid 2035 * 0x08, VanaHwHPReq2Valid 2036 * 0x10, VpllHwHPReq2Valid 2037 * 0x20, Vaux1HwHPReq2Valid 2038 * 0x40, Vaux2HwHPReq2Valid 2039 * 0x80, Vaux3HwHPReq2Valid 2040 */ 2041 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), 2042 /* 2043 * 0x08, VsmpsMHwHPReq2Valid 2044 */ 2045 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08), 2046 /* 2047 * 0x01, VsmpsCSwHPReqValid 2048 * 0x02, VarmSwHPReqValid 2049 * 0x04, VsmpsASwHPReqValid 2050 * 0x08, VsmpsBSwHPReqValid 2051 * 0x10, VsafeSwHPReqValid 2052 * 0x20, VanaSwHPReqValid 2053 * 0x40, VpllSwHPReqValid 2054 * 0x80, Vaux1SwHPReqValid 2055 */ 2056 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), 2057 /* 2058 * 0x01, Vaux2SwHPReqValid 2059 * 0x02, Vaux3SwHPReqValid 2060 * 0x20, VsmpsMSwHPReqValid 2061 */ 2062 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23), 2063 /* 2064 * 0x02, SysClkReq2Valid1 2065 * 0x04, SysClkReq3Valid1 2066 * 0x08, SysClkReq4Valid1 2067 */ 2068 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e), 2069 /* 2070 * 0x02, SysClkReq2Valid2 2071 * 0x04, SysClkReq3Valid2 2072 * 0x08, SysClkReq4Valid2 2073 */ 2074 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e), 2075 /* 2076 * 0x01, Vaux4SwHPReqValid 2077 * 0x02, Vaux4HwHPReq2Valid 2078 * 0x04, Vaux4HwHPReq1Valid 2079 * 0x08, Vaux4SysClkReq1HPValid 2080 */ 2081 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), 2082 /* 2083 * 0x02, VadcEna 2084 * 0x04, VintCore12Ena 2085 * 0x38, VintCore12Sel 2086 * 0x40, VintCore12LP 2087 * 0x80, VadcLP 2088 */ 2089 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe), 2090 /* 2091 * 0x02, VaudioEna 2092 * 0x04, VdmicEna 2093 * 0x08, Vamic1Ena 2094 * 0x10, Vamic2Ena 2095 */ 2096 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 2097 /* 2098 * 0x01, Vamic1_dzout 2099 * 0x02, Vamic2_dzout 2100 */ 2101 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 2102 /* 2103 * 0x03, VsmpsARegu 2104 * 0x0c, VsmpsASelCtrl 2105 * 0x10, VsmpsAAutoMode 2106 * 0x20, VsmpsAPWMMode 2107 */ 2108 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f), 2109 /* 2110 * 0x03, VsmpsBRegu 2111 * 0x0c, VsmpsBSelCtrl 2112 * 0x10, VsmpsBAutoMode 2113 * 0x20, VsmpsBPWMMode 2114 */ 2115 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f), 2116 /* 2117 * 0x03, VsafeRegu 2118 * 0x0c, VsafeSelCtrl 2119 * 0x10, VsafeAutoMode 2120 * 0x20, VsafePWMMode 2121 */ 2122 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f), 2123 /* 2124 * 0x03, VpllRegu (NOTE! PRCMU register bits) 2125 * 0x0c, VanaRegu 2126 */ 2127 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f), 2128 /* 2129 * 0x03, VextSupply1Regu 2130 * 0x0c, VextSupply2Regu 2131 * 0x30, VextSupply3Regu 2132 * 0x40, ExtSupply2Bypass 2133 * 0x80, ExtSupply3Bypass 2134 */ 2135 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 2136 /* 2137 * 0x03, Vaux1Regu 2138 * 0x0c, Vaux2Regu 2139 */ 2140 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f), 2141 /* 2142 * 0x0f, Vaux3Regu 2143 */ 2144 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), 2145 /* 2146 * 0x3f, VsmpsASel1 2147 */ 2148 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f), 2149 /* 2150 * 0x3f, VsmpsASel2 2151 */ 2152 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f), 2153 /* 2154 * 0x3f, VsmpsASel3 2155 */ 2156 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f), 2157 /* 2158 * 0x3f, VsmpsBSel1 2159 */ 2160 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f), 2161 /* 2162 * 0x3f, VsmpsBSel2 2163 */ 2164 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f), 2165 /* 2166 * 0x3f, VsmpsBSel3 2167 */ 2168 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f), 2169 /* 2170 * 0x7f, VsafeSel1 2171 */ 2172 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f), 2173 /* 2174 * 0x3f, VsafeSel2 2175 */ 2176 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f), 2177 /* 2178 * 0x3f, VsafeSel3 2179 */ 2180 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f), 2181 /* 2182 * 0x0f, Vaux1Sel 2183 */ 2184 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f), 2185 /* 2186 * 0x0f, Vaux2Sel 2187 */ 2188 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f), 2189 /* 2190 * 0x07, Vaux3Sel 2191 * 0x30, VRF1Sel 2192 */ 2193 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37), 2194 /* 2195 * 0x03, Vaux4RequestCtrl 2196 */ 2197 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03), 2198 /* 2199 * 0x03, Vaux4Regu 2200 */ 2201 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03), 2202 /* 2203 * 0x0f, Vaux4Sel 2204 */ 2205 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f), 2206 /* 2207 * 0x04, Vaux1Disch 2208 * 0x08, Vaux2Disch 2209 * 0x10, Vaux3Disch 2210 * 0x20, Vintcore12Disch 2211 * 0x40, VTVoutDisch 2212 * 0x80, VaudioDisch 2213 */ 2214 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc), 2215 /* 2216 * 0x02, VanaDisch 2217 * 0x04, VdmicPullDownEna 2218 * 0x10, VdmicDisch 2219 */ 2220 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 2221 /* 2222 * 0x01, Vaux4Disch 2223 */ 2224 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01), 2225 /* 2226 * 0x07, Vaux5Sel 2227 * 0x08, Vaux5LP 2228 * 0x10, Vaux5Ena 2229 * 0x20, Vaux5Disch 2230 * 0x40, Vaux5DisSfst 2231 * 0x80, Vaux5DisPulld 2232 */ 2233 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff), 2234 /* 2235 * 0x07, Vaux6Sel 2236 * 0x08, Vaux6LP 2237 * 0x10, Vaux6Ena 2238 * 0x80, Vaux6DisPulld 2239 */ 2240 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f), 2241 }; 2242 2243 /* AB9540 register init */ 2244 static struct ab8500_reg_init ab9540_reg_init[] = { 2245 /* 2246 * 0x03, VarmRequestCtrl 2247 * 0x0c, VapeRequestCtrl 2248 * 0x30, Vsmps1RequestCtrl 2249 * 0xc0, Vsmps2RequestCtrl 2250 */ 2251 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), 2252 /* 2253 * 0x03, Vsmps3RequestCtrl 2254 * 0x0c, VpllRequestCtrl 2255 * 0x30, VanaRequestCtrl 2256 * 0xc0, VextSupply1RequestCtrl 2257 */ 2258 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff), 2259 /* 2260 * 0x03, VextSupply2RequestCtrl 2261 * 0x0c, VextSupply3RequestCtrl 2262 * 0x30, Vaux1RequestCtrl 2263 * 0xc0, Vaux2RequestCtrl 2264 */ 2265 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), 2266 /* 2267 * 0x03, Vaux3RequestCtrl 2268 * 0x04, SwHPReq 2269 */ 2270 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 2271 /* 2272 * 0x01, Vsmps1SysClkReq1HPValid 2273 * 0x02, Vsmps2SysClkReq1HPValid 2274 * 0x04, Vsmps3SysClkReq1HPValid 2275 * 0x08, VanaSysClkReq1HPValid 2276 * 0x10, VpllSysClkReq1HPValid 2277 * 0x20, Vaux1SysClkReq1HPValid 2278 * 0x40, Vaux2SysClkReq1HPValid 2279 * 0x80, Vaux3SysClkReq1HPValid 2280 */ 2281 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), 2282 /* 2283 * 0x01, VapeSysClkReq1HPValid 2284 * 0x02, VarmSysClkReq1HPValid 2285 * 0x04, VbbSysClkReq1HPValid 2286 * 0x08, VmodSysClkReq1HPValid 2287 * 0x10, VextSupply1SysClkReq1HPValid 2288 * 0x20, VextSupply2SysClkReq1HPValid 2289 * 0x40, VextSupply3SysClkReq1HPValid 2290 */ 2291 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f), 2292 /* 2293 * 0x01, Vsmps1HwHPReq1Valid 2294 * 0x02, Vsmps2HwHPReq1Valid 2295 * 0x04, Vsmps3HwHPReq1Valid 2296 * 0x08, VanaHwHPReq1Valid 2297 * 0x10, VpllHwHPReq1Valid 2298 * 0x20, Vaux1HwHPReq1Valid 2299 * 0x40, Vaux2HwHPReq1Valid 2300 * 0x80, Vaux3HwHPReq1Valid 2301 */ 2302 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), 2303 /* 2304 * 0x01, VextSupply1HwHPReq1Valid 2305 * 0x02, VextSupply2HwHPReq1Valid 2306 * 0x04, VextSupply3HwHPReq1Valid 2307 * 0x08, VmodHwHPReq1Valid 2308 */ 2309 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f), 2310 /* 2311 * 0x01, Vsmps1HwHPReq2Valid 2312 * 0x02, Vsmps2HwHPReq2Valid 2313 * 0x03, Vsmps3HwHPReq2Valid 2314 * 0x08, VanaHwHPReq2Valid 2315 * 0x10, VpllHwHPReq2Valid 2316 * 0x20, Vaux1HwHPReq2Valid 2317 * 0x40, Vaux2HwHPReq2Valid 2318 * 0x80, Vaux3HwHPReq2Valid 2319 */ 2320 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), 2321 /* 2322 * 0x01, VextSupply1HwHPReq2Valid 2323 * 0x02, VextSupply2HwHPReq2Valid 2324 * 0x04, VextSupply3HwHPReq2Valid 2325 * 0x08, VmodHwHPReq2Valid 2326 */ 2327 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f), 2328 /* 2329 * 0x01, VapeSwHPReqValid 2330 * 0x02, VarmSwHPReqValid 2331 * 0x04, Vsmps1SwHPReqValid 2332 * 0x08, Vsmps2SwHPReqValid 2333 * 0x10, Vsmps3SwHPReqValid 2334 * 0x20, VanaSwHPReqValid 2335 * 0x40, VpllSwHPReqValid 2336 * 0x80, Vaux1SwHPReqValid 2337 */ 2338 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), 2339 /* 2340 * 0x01, Vaux2SwHPReqValid 2341 * 0x02, Vaux3SwHPReqValid 2342 * 0x04, VextSupply1SwHPReqValid 2343 * 0x08, VextSupply2SwHPReqValid 2344 * 0x10, VextSupply3SwHPReqValid 2345 * 0x20, VmodSwHPReqValid 2346 */ 2347 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f), 2348 /* 2349 * 0x02, SysClkReq2Valid1 2350 * ... 2351 * 0x80, SysClkReq8Valid1 2352 */ 2353 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), 2354 /* 2355 * 0x02, SysClkReq2Valid2 2356 * ... 2357 * 0x80, SysClkReq8Valid2 2358 */ 2359 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), 2360 /* 2361 * 0x01, Vaux4SwHPReqValid 2362 * 0x02, Vaux4HwHPReq2Valid 2363 * 0x04, Vaux4HwHPReq1Valid 2364 * 0x08, Vaux4SysClkReq1HPValid 2365 */ 2366 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), 2367 /* 2368 * 0x02, VTVoutEna 2369 * 0x04, Vintcore12Ena 2370 * 0x38, Vintcore12Sel 2371 * 0x40, Vintcore12LP 2372 * 0x80, VTVoutLP 2373 */ 2374 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe), 2375 /* 2376 * 0x02, VaudioEna 2377 * 0x04, VdmicEna 2378 * 0x08, Vamic1Ena 2379 * 0x10, Vamic2Ena 2380 */ 2381 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 2382 /* 2383 * 0x01, Vamic1_dzout 2384 * 0x02, Vamic2_dzout 2385 */ 2386 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 2387 /* 2388 * 0x03, Vsmps1Regu 2389 * 0x0c, Vsmps1SelCtrl 2390 * 0x10, Vsmps1AutoMode 2391 * 0x20, Vsmps1PWMMode 2392 */ 2393 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f), 2394 /* 2395 * 0x03, Vsmps2Regu 2396 * 0x0c, Vsmps2SelCtrl 2397 * 0x10, Vsmps2AutoMode 2398 * 0x20, Vsmps2PWMMode 2399 */ 2400 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f), 2401 /* 2402 * 0x03, Vsmps3Regu 2403 * 0x0c, Vsmps3SelCtrl 2404 * NOTE! PRCMU register 2405 */ 2406 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f), 2407 /* 2408 * 0x03, VpllRegu 2409 * 0x0c, VanaRegu 2410 */ 2411 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f), 2412 /* 2413 * 0x03, VextSupply1Regu 2414 * 0x0c, VextSupply2Regu 2415 * 0x30, VextSupply3Regu 2416 * 0x40, ExtSupply2Bypass 2417 * 0x80, ExtSupply3Bypass 2418 */ 2419 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 2420 /* 2421 * 0x03, Vaux1Regu 2422 * 0x0c, Vaux2Regu 2423 */ 2424 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f), 2425 /* 2426 * 0x0c, Vrf1Regu 2427 * 0x03, Vaux3Regu 2428 */ 2429 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), 2430 /* 2431 * 0x3f, Vsmps1Sel1 2432 */ 2433 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f), 2434 /* 2435 * 0x3f, Vsmps1Sel2 2436 */ 2437 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f), 2438 /* 2439 * 0x3f, Vsmps1Sel3 2440 */ 2441 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f), 2442 /* 2443 * 0x3f, Vsmps2Sel1 2444 */ 2445 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f), 2446 /* 2447 * 0x3f, Vsmps2Sel2 2448 */ 2449 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f), 2450 /* 2451 * 0x3f, Vsmps2Sel3 2452 */ 2453 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f), 2454 /* 2455 * 0x7f, Vsmps3Sel1 2456 * NOTE! PRCMU register 2457 */ 2458 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f), 2459 /* 2460 * 0x7f, Vsmps3Sel2 2461 * NOTE! PRCMU register 2462 */ 2463 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f), 2464 /* 2465 * 0x0f, Vaux1Sel 2466 */ 2467 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f), 2468 /* 2469 * 0x0f, Vaux2Sel 2470 */ 2471 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f), 2472 /* 2473 * 0x07, Vaux3Sel 2474 * 0x30, Vrf1Sel 2475 */ 2476 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37), 2477 /* 2478 * 0x01, VextSupply12LP 2479 */ 2480 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01), 2481 /* 2482 * 0x03, Vaux4RequestCtrl 2483 */ 2484 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03), 2485 /* 2486 * 0x03, Vaux4Regu 2487 */ 2488 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03), 2489 /* 2490 * 0x08, Vaux4Sel 2491 */ 2492 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f), 2493 /* 2494 * 0x01, VpllDisch 2495 * 0x02, Vrf1Disch 2496 * 0x04, Vaux1Disch 2497 * 0x08, Vaux2Disch 2498 * 0x10, Vaux3Disch 2499 * 0x20, Vintcore12Disch 2500 * 0x40, VTVoutDisch 2501 * 0x80, VaudioDisch 2502 */ 2503 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff), 2504 /* 2505 * 0x01, VsimDisch 2506 * 0x02, VanaDisch 2507 * 0x04, VdmicPullDownEna 2508 * 0x08, VpllPullDownEna 2509 * 0x10, VdmicDisch 2510 */ 2511 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f), 2512 /* 2513 * 0x01, Vaux4Disch 2514 */ 2515 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01), 2516 }; 2517 2518 /* AB8540 register init */ 2519 static struct ab8500_reg_init ab8540_reg_init[] = { 2520 /* 2521 * 0x01, VSimSycClkReq1Valid 2522 * 0x02, VSimSycClkReq2Valid 2523 * 0x04, VSimSycClkReq3Valid 2524 * 0x08, VSimSycClkReq4Valid 2525 * 0x10, VSimSycClkReq5Valid 2526 * 0x20, VSimSycClkReq6Valid 2527 * 0x40, VSimSycClkReq7Valid 2528 * 0x80, VSimSycClkReq8Valid 2529 */ 2530 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff), 2531 /* 2532 * 0x03, VarmRequestCtrl 2533 * 0x0c, VapeRequestCtrl 2534 * 0x30, Vsmps1RequestCtrl 2535 * 0xc0, Vsmps2RequestCtrl 2536 */ 2537 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), 2538 /* 2539 * 0x03, Vsmps3RequestCtrl 2540 * 0x0c, VpllRequestCtrl 2541 * 0x30, VanaRequestCtrl 2542 * 0xc0, VextSupply1RequestCtrl 2543 */ 2544 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff), 2545 /* 2546 * 0x03, VextSupply2RequestCtrl 2547 * 0x0c, VextSupply3RequestCtrl 2548 * 0x30, Vaux1RequestCtrl 2549 * 0xc0, Vaux2RequestCtrl 2550 */ 2551 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), 2552 /* 2553 * 0x03, Vaux3RequestCtrl 2554 * 0x04, SwHPReq 2555 */ 2556 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 2557 /* 2558 * 0x01, Vsmps1SysClkReq1HPValid 2559 * 0x02, Vsmps2SysClkReq1HPValid 2560 * 0x04, Vsmps3SysClkReq1HPValid 2561 * 0x08, VanaSysClkReq1HPValid 2562 * 0x10, VpllSysClkReq1HPValid 2563 * 0x20, Vaux1SysClkReq1HPValid 2564 * 0x40, Vaux2SysClkReq1HPValid 2565 * 0x80, Vaux3SysClkReq1HPValid 2566 */ 2567 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), 2568 /* 2569 * 0x01, VapeSysClkReq1HPValid 2570 * 0x02, VarmSysClkReq1HPValid 2571 * 0x04, VbbSysClkReq1HPValid 2572 * 0x10, VextSupply1SysClkReq1HPValid 2573 * 0x20, VextSupply2SysClkReq1HPValid 2574 * 0x40, VextSupply3SysClkReq1HPValid 2575 */ 2576 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77), 2577 /* 2578 * 0x01, Vsmps1HwHPReq1Valid 2579 * 0x02, Vsmps2HwHPReq1Valid 2580 * 0x04, Vsmps3HwHPReq1Valid 2581 * 0x08, VanaHwHPReq1Valid 2582 * 0x10, VpllHwHPReq1Valid 2583 * 0x20, Vaux1HwHPReq1Valid 2584 * 0x40, Vaux2HwHPReq1Valid 2585 * 0x80, Vaux3HwHPReq1Valid 2586 */ 2587 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), 2588 /* 2589 * 0x01, VextSupply1HwHPReq1Valid 2590 * 0x02, VextSupply2HwHPReq1Valid 2591 * 0x04, VextSupply3HwHPReq1Valid 2592 */ 2593 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), 2594 /* 2595 * 0x01, Vsmps1HwHPReq2Valid 2596 * 0x02, Vsmps2HwHPReq2Valid 2597 * 0x03, Vsmps3HwHPReq2Valid 2598 * 0x08, VanaHwHPReq2Valid 2599 * 0x10, VpllHwHPReq2Valid 2600 * 0x20, Vaux1HwHPReq2Valid 2601 * 0x40, Vaux2HwHPReq2Valid 2602 * 0x80, Vaux3HwHPReq2Valid 2603 */ 2604 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), 2605 /* 2606 * 0x01, VextSupply1HwHPReq2Valid 2607 * 0x02, VextSupply2HwHPReq2Valid 2608 * 0x04, VextSupply3HwHPReq2Valid 2609 */ 2610 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), 2611 /* 2612 * 0x01, VapeSwHPReqValid 2613 * 0x02, VarmSwHPReqValid 2614 * 0x04, Vsmps1SwHPReqValid 2615 * 0x08, Vsmps2SwHPReqValid 2616 * 0x10, Vsmps3SwHPReqValid 2617 * 0x20, VanaSwHPReqValid 2618 * 0x40, VpllSwHPReqValid 2619 * 0x80, Vaux1SwHPReqValid 2620 */ 2621 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), 2622 /* 2623 * 0x01, Vaux2SwHPReqValid 2624 * 0x02, Vaux3SwHPReqValid 2625 * 0x04, VextSupply1SwHPReqValid 2626 * 0x08, VextSupply2SwHPReqValid 2627 * 0x10, VextSupply3SwHPReqValid 2628 */ 2629 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), 2630 /* 2631 * 0x02, SysClkReq2Valid1 2632 * ... 2633 * 0x80, SysClkReq8Valid1 2634 */ 2635 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff), 2636 /* 2637 * 0x02, SysClkReq2Valid2 2638 * ... 2639 * 0x80, SysClkReq8Valid2 2640 */ 2641 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff), 2642 /* 2643 * 0x01, Vaux4SwHPReqValid 2644 * 0x02, Vaux4HwHPReq2Valid 2645 * 0x04, Vaux4HwHPReq1Valid 2646 * 0x08, Vaux4SysClkReq1HPValid 2647 */ 2648 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), 2649 /* 2650 * 0x01, Vaux5SwHPReqValid 2651 * 0x02, Vaux5HwHPReq2Valid 2652 * 0x04, Vaux5HwHPReq1Valid 2653 * 0x08, Vaux5SysClkReq1HPValid 2654 */ 2655 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f), 2656 /* 2657 * 0x01, Vaux6SwHPReqValid 2658 * 0x02, Vaux6HwHPReq2Valid 2659 * 0x04, Vaux6HwHPReq1Valid 2660 * 0x08, Vaux6SysClkReq1HPValid 2661 */ 2662 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f), 2663 /* 2664 * 0x01, VclkbSwHPReqValid 2665 * 0x02, VclkbHwHPReq2Valid 2666 * 0x04, VclkbHwHPReq1Valid 2667 * 0x08, VclkbSysClkReq1HPValid 2668 */ 2669 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f), 2670 /* 2671 * 0x01, Vrf1SwHPReqValid 2672 * 0x02, Vrf1HwHPReq2Valid 2673 * 0x04, Vrf1HwHPReq1Valid 2674 * 0x08, Vrf1SysClkReq1HPValid 2675 */ 2676 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f), 2677 /* 2678 * 0x02, VTVoutEna 2679 * 0x04, Vintcore12Ena 2680 * 0x38, Vintcore12Sel 2681 * 0x40, Vintcore12LP 2682 * 0x80, VTVoutLP 2683 */ 2684 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe), 2685 /* 2686 * 0x02, VaudioEna 2687 * 0x04, VdmicEna 2688 * 0x08, Vamic1Ena 2689 * 0x10, Vamic2Ena 2690 * 0x20, Vamic12LP 2691 * 0xC0, VdmicSel 2692 */ 2693 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe), 2694 /* 2695 * 0x01, Vamic1_dzout 2696 * 0x02, Vamic2_dzout 2697 */ 2698 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 2699 /* 2700 * 0x07, VHSICSel 2701 * 0x08, VHSICOffState 2702 * 0x10, VHSIEna 2703 * 0x20, VHSICLP 2704 */ 2705 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f), 2706 /* 2707 * 0x07, VSDIOSel 2708 * 0x08, VSDIOOffState 2709 * 0x10, VSDIOEna 2710 * 0x20, VSDIOLP 2711 */ 2712 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f), 2713 /* 2714 * 0x03, Vsmps1Regu 2715 * 0x0c, Vsmps1SelCtrl 2716 * 0x10, Vsmps1AutoMode 2717 * 0x20, Vsmps1PWMMode 2718 */ 2719 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f), 2720 /* 2721 * 0x03, Vsmps2Regu 2722 * 0x0c, Vsmps2SelCtrl 2723 * 0x10, Vsmps2AutoMode 2724 * 0x20, Vsmps2PWMMode 2725 */ 2726 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f), 2727 /* 2728 * 0x03, Vsmps3Regu 2729 * 0x0c, Vsmps3SelCtrl 2730 * 0x10, Vsmps3AutoMode 2731 * 0x20, Vsmps3PWMMode 2732 * NOTE! PRCMU register 2733 */ 2734 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f), 2735 /* 2736 * 0x03, VpllRegu 2737 * 0x0c, VanaRegu 2738 */ 2739 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f), 2740 /* 2741 * 0x03, VextSupply1Regu 2742 * 0x0c, VextSupply2Regu 2743 * 0x30, VextSupply3Regu 2744 * 0x40, ExtSupply2Bypass 2745 * 0x80, ExtSupply3Bypass 2746 */ 2747 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 2748 /* 2749 * 0x03, Vaux1Regu 2750 * 0x0c, Vaux2Regu 2751 */ 2752 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f), 2753 /* 2754 * 0x0c, VRF1Regu 2755 * 0x03, Vaux3Regu 2756 */ 2757 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), 2758 /* 2759 * 0x3f, Vsmps1Sel1 2760 */ 2761 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f), 2762 /* 2763 * 0x3f, Vsmps1Sel2 2764 */ 2765 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f), 2766 /* 2767 * 0x3f, Vsmps1Sel3 2768 */ 2769 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f), 2770 /* 2771 * 0x3f, Vsmps2Sel1 2772 */ 2773 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f), 2774 /* 2775 * 0x3f, Vsmps2Sel2 2776 */ 2777 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f), 2778 /* 2779 * 0x3f, Vsmps2Sel3 2780 */ 2781 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f), 2782 /* 2783 * 0x7f, Vsmps3Sel1 2784 * NOTE! PRCMU register 2785 */ 2786 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f), 2787 /* 2788 * 0x7f, Vsmps3Sel2 2789 * NOTE! PRCMU register 2790 */ 2791 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f), 2792 /* 2793 * 0x0f, Vaux1Sel 2794 */ 2795 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f), 2796 /* 2797 * 0x0f, Vaux2Sel 2798 */ 2799 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f), 2800 /* 2801 * 0x07, Vaux3Sel 2802 * 0x70, Vrf1Sel 2803 */ 2804 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77), 2805 /* 2806 * 0x01, VextSupply12LP 2807 */ 2808 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01), 2809 /* 2810 * 0x07, Vanasel 2811 * 0x30, Vpllsel 2812 */ 2813 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37), 2814 /* 2815 * 0x03, Vaux4RequestCtrl 2816 */ 2817 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03), 2818 /* 2819 * 0x03, Vaux4Regu 2820 */ 2821 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03), 2822 /* 2823 * 0x0f, Vaux4Sel 2824 */ 2825 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f), 2826 /* 2827 * 0x03, Vaux5RequestCtrl 2828 */ 2829 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03), 2830 /* 2831 * 0x03, Vaux5Regu 2832 */ 2833 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03), 2834 /* 2835 * 0x3f, Vaux5Sel 2836 */ 2837 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f), 2838 /* 2839 * 0x03, Vaux6RequestCtrl 2840 */ 2841 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03), 2842 /* 2843 * 0x03, Vaux6Regu 2844 */ 2845 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03), 2846 /* 2847 * 0x3f, Vaux6Sel 2848 */ 2849 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f), 2850 /* 2851 * 0x03, VCLKBRequestCtrl 2852 */ 2853 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03), 2854 /* 2855 * 0x03, VCLKBRegu 2856 */ 2857 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03), 2858 /* 2859 * 0x07, VCLKBSel 2860 */ 2861 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07), 2862 /* 2863 * 0x03, Vrf1RequestCtrl 2864 */ 2865 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03), 2866 /* 2867 * 0x01, VpllDisch 2868 * 0x02, Vrf1Disch 2869 * 0x04, Vaux1Disch 2870 * 0x08, Vaux2Disch 2871 * 0x10, Vaux3Disch 2872 * 0x20, Vintcore12Disch 2873 * 0x40, VTVoutDisch 2874 * 0x80, VaudioDisch 2875 */ 2876 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff), 2877 /* 2878 * 0x02, VanaDisch 2879 * 0x04, VdmicPullDownEna 2880 * 0x08, VpllPullDownEna 2881 * 0x10, VdmicDisch 2882 */ 2883 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e), 2884 /* 2885 * 0x01, Vaux4Disch 2886 */ 2887 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01), 2888 /* 2889 * 0x01, Vaux5Disch 2890 * 0x02, Vaux6Disch 2891 * 0x04, VCLKBDisch 2892 */ 2893 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07), 2894 }; 2895 2896 static struct of_regulator_match ab8500_regulator_match[] = { 2897 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, }, 2898 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, }, 2899 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, }, 2900 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, }, 2901 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, 2902 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, 2903 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, 2904 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, 2905 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, 2906 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, 2907 }; 2908 2909 static struct of_regulator_match ab8505_regulator_match[] = { 2910 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, }, 2911 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, }, 2912 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, }, 2913 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, }, 2914 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, }, 2915 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, }, 2916 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, }, 2917 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, 2918 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, 2919 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, 2920 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, 2921 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, 2922 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, 2923 }; 2924 2925 static struct of_regulator_match ab8540_regulator_match[] = { 2926 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, }, 2927 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, }, 2928 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, }, 2929 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, }, 2930 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, }, 2931 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, }, 2932 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, }, 2933 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, }, 2934 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, }, 2935 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, }, 2936 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, }, 2937 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, }, 2938 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, }, 2939 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, }, 2940 }; 2941 2942 static struct of_regulator_match ab9540_regulator_match[] = { 2943 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, }, 2944 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, }, 2945 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, }, 2946 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, }, 2947 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, }, 2948 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, }, 2949 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, }, 2950 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, }, 2951 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, }, 2952 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, }, 2953 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, }, 2954 }; 2955 2956 static struct { 2957 struct ab8500_regulator_info *info; 2958 int info_size; 2959 struct ab8500_reg_init *init; 2960 int init_size; 2961 struct of_regulator_match *match; 2962 int match_size; 2963 } abx500_regulator; 2964 2965 static void abx500_get_regulator_info(struct ab8500 *ab8500) 2966 { 2967 if (is_ab9540(ab8500)) { 2968 abx500_regulator.info = ab9540_regulator_info; 2969 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info); 2970 abx500_regulator.init = ab9540_reg_init; 2971 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS; 2972 abx500_regulator.match = ab9540_regulator_match; 2973 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match); 2974 } else if (is_ab8505(ab8500)) { 2975 abx500_regulator.info = ab8505_regulator_info; 2976 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info); 2977 abx500_regulator.init = ab8505_reg_init; 2978 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS; 2979 abx500_regulator.match = ab8505_regulator_match; 2980 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match); 2981 } else if (is_ab8540(ab8500)) { 2982 abx500_regulator.info = ab8540_regulator_info; 2983 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info); 2984 abx500_regulator.init = ab8540_reg_init; 2985 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS; 2986 abx500_regulator.match = ab8540_regulator_match; 2987 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match); 2988 } else { 2989 abx500_regulator.info = ab8500_regulator_info; 2990 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info); 2991 abx500_regulator.init = ab8500_reg_init; 2992 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS; 2993 abx500_regulator.match = ab8500_regulator_match; 2994 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match); 2995 } 2996 } 2997 2998 static int ab8500_regulator_init_registers(struct platform_device *pdev, 2999 int id, int mask, int value) 3000 { 3001 struct ab8500_reg_init *reg_init = abx500_regulator.init; 3002 int err; 3003 3004 BUG_ON(value & ~mask); 3005 BUG_ON(mask & ~reg_init[id].mask); 3006 3007 /* initialize register */ 3008 err = abx500_mask_and_set_register_interruptible( 3009 &pdev->dev, 3010 reg_init[id].bank, 3011 reg_init[id].addr, 3012 mask, value); 3013 if (err < 0) { 3014 dev_err(&pdev->dev, 3015 "Failed to initialize 0x%02x, 0x%02x.\n", 3016 reg_init[id].bank, 3017 reg_init[id].addr); 3018 return err; 3019 } 3020 dev_vdbg(&pdev->dev, 3021 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", 3022 reg_init[id].bank, 3023 reg_init[id].addr, 3024 mask, value); 3025 3026 return 0; 3027 } 3028 3029 static int ab8500_regulator_register(struct platform_device *pdev, 3030 struct regulator_init_data *init_data, 3031 int id, struct device_node *np) 3032 { 3033 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 3034 struct ab8500_regulator_info *info = NULL; 3035 struct regulator_config config = { }; 3036 int err; 3037 3038 /* assign per-regulator data */ 3039 info = &abx500_regulator.info[id]; 3040 info->dev = &pdev->dev; 3041 3042 config.dev = &pdev->dev; 3043 config.init_data = init_data; 3044 config.driver_data = info; 3045 config.of_node = np; 3046 3047 /* fix for hardware before ab8500v2.0 */ 3048 if (is_ab8500_1p1_or_earlier(ab8500)) { 3049 if (info->desc.id == AB8500_LDO_AUX3) { 3050 info->desc.n_voltages = 3051 ARRAY_SIZE(ldo_vauxn_voltages); 3052 info->desc.volt_table = ldo_vauxn_voltages; 3053 info->voltage_mask = 0xf; 3054 } 3055 } 3056 3057 /* register regulator with framework */ 3058 info->regulator = regulator_register(&info->desc, &config); 3059 if (IS_ERR(info->regulator)) { 3060 err = PTR_ERR(info->regulator); 3061 dev_err(&pdev->dev, "failed to register regulator %s\n", 3062 info->desc.name); 3063 /* when we fail, un-register all earlier regulators */ 3064 while (--id >= 0) { 3065 info = &abx500_regulator.info[id]; 3066 regulator_unregister(info->regulator); 3067 } 3068 return err; 3069 } 3070 3071 return 0; 3072 } 3073 3074 static int 3075 ab8500_regulator_of_probe(struct platform_device *pdev, 3076 struct device_node *np) 3077 { 3078 struct of_regulator_match *match = abx500_regulator.match; 3079 int err, i; 3080 3081 for (i = 0; i < abx500_regulator.info_size; i++) { 3082 err = ab8500_regulator_register( 3083 pdev, match[i].init_data, i, match[i].of_node); 3084 if (err) 3085 return err; 3086 } 3087 3088 return 0; 3089 } 3090 3091 static int ab8500_regulator_probe(struct platform_device *pdev) 3092 { 3093 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 3094 struct device_node *np = pdev->dev.of_node; 3095 struct ab8500_platform_data *ppdata; 3096 struct ab8500_regulator_platform_data *pdata; 3097 int i, err; 3098 3099 if (!ab8500) { 3100 dev_err(&pdev->dev, "null mfd parent\n"); 3101 return -EINVAL; 3102 } 3103 3104 abx500_get_regulator_info(ab8500); 3105 3106 if (np) { 3107 err = of_regulator_match(&pdev->dev, np, 3108 abx500_regulator.match, 3109 abx500_regulator.match_size); 3110 if (err < 0) { 3111 dev_err(&pdev->dev, 3112 "Error parsing regulator init data: %d\n", err); 3113 return err; 3114 } 3115 3116 err = ab8500_regulator_of_probe(pdev, np); 3117 return err; 3118 } 3119 3120 ppdata = dev_get_platdata(ab8500->dev); 3121 if (!ppdata) { 3122 dev_err(&pdev->dev, "null parent pdata\n"); 3123 return -EINVAL; 3124 } 3125 3126 pdata = ppdata->regulator; 3127 if (!pdata) { 3128 dev_err(&pdev->dev, "null pdata\n"); 3129 return -EINVAL; 3130 } 3131 3132 /* make sure the platform data has the correct size */ 3133 if (pdata->num_regulator != abx500_regulator.info_size) { 3134 dev_err(&pdev->dev, "Configuration error: size mismatch.\n"); 3135 return -EINVAL; 3136 } 3137 3138 /* initialize debug (initial state is recorded with this call) */ 3139 err = ab8500_regulator_debug_init(pdev); 3140 if (err) 3141 return err; 3142 3143 /* initialize registers */ 3144 for (i = 0; i < pdata->num_reg_init; i++) { 3145 int id, mask, value; 3146 3147 id = pdata->reg_init[i].id; 3148 mask = pdata->reg_init[i].mask; 3149 value = pdata->reg_init[i].value; 3150 3151 /* check for configuration errors */ 3152 BUG_ON(id >= abx500_regulator.init_size); 3153 3154 err = ab8500_regulator_init_registers(pdev, id, mask, value); 3155 if (err < 0) 3156 return err; 3157 } 3158 3159 if (!is_ab8505(ab8500)) { 3160 /* register external regulators (before Vaux1, 2 and 3) */ 3161 err = ab8500_ext_regulator_init(pdev); 3162 if (err) 3163 return err; 3164 } 3165 3166 /* register all regulators */ 3167 for (i = 0; i < abx500_regulator.info_size; i++) { 3168 err = ab8500_regulator_register(pdev, &pdata->regulator[i], 3169 i, NULL); 3170 if (err < 0) { 3171 if (!is_ab8505(ab8500)) 3172 ab8500_ext_regulator_exit(pdev); 3173 return err; 3174 } 3175 } 3176 3177 return 0; 3178 } 3179 3180 static int ab8500_regulator_remove(struct platform_device *pdev) 3181 { 3182 int i, err; 3183 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 3184 3185 for (i = 0; i < abx500_regulator.info_size; i++) { 3186 struct ab8500_regulator_info *info = NULL; 3187 info = &abx500_regulator.info[i]; 3188 3189 dev_vdbg(rdev_get_dev(info->regulator), 3190 "%s-remove\n", info->desc.name); 3191 3192 regulator_unregister(info->regulator); 3193 } 3194 3195 /* remove external regulators (after Vaux1, 2 and 3) */ 3196 if (!is_ab8505(ab8500)) 3197 ab8500_ext_regulator_exit(pdev); 3198 3199 /* remove regulator debug */ 3200 err = ab8500_regulator_debug_exit(pdev); 3201 if (err) 3202 return err; 3203 3204 return 0; 3205 } 3206 3207 static struct platform_driver ab8500_regulator_driver = { 3208 .probe = ab8500_regulator_probe, 3209 .remove = ab8500_regulator_remove, 3210 .driver = { 3211 .name = "ab8500-regulator", 3212 .owner = THIS_MODULE, 3213 }, 3214 }; 3215 3216 static int __init ab8500_regulator_init(void) 3217 { 3218 int ret; 3219 3220 ret = platform_driver_register(&ab8500_regulator_driver); 3221 if (ret != 0) 3222 pr_err("Failed to register ab8500 regulator: %d\n", ret); 3223 3224 return ret; 3225 } 3226 subsys_initcall(ab8500_regulator_init); 3227 3228 static void __exit ab8500_regulator_exit(void) 3229 { 3230 platform_driver_unregister(&ab8500_regulator_driver); 3231 } 3232 module_exit(ab8500_regulator_exit); 3233 3234 MODULE_LICENSE("GPL v2"); 3235 MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>"); 3236 MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>"); 3237 MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>"); 3238 MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC"); 3239 MODULE_ALIAS("platform:ab8500-regulator"); 3240