1 /* 2 * IDT CPS Gen.2 Serial RapidIO switch family support 3 * 4 * Copyright 2010 Integrated Device Technology, Inc. 5 * Alexandre Bounine <alexandre.bounine@idt.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/stat.h> 14 #include <linux/module.h> 15 #include <linux/rio.h> 16 #include <linux/rio_drv.h> 17 #include <linux/rio_ids.h> 18 #include <linux/delay.h> 19 #include "../rio.h" 20 21 #define LOCAL_RTE_CONF_DESTID_SEL 0x010070 22 #define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f 23 24 #define IDT_LT_ERR_REPORT_EN 0x03100c 25 26 #define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40) 27 #define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04 28 29 #define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40) 30 #define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c 31 #define IDT_PORT_INIT_TX_ACQUIRED 0x00000020 32 33 #define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100) 34 #define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10 35 36 #define IDT_DEV_CTRL_1 0xf2000c 37 #define IDT_DEV_CTRL_1_GENPW 0x02000000 38 #define IDT_DEV_CTRL_1_PRSTBEH 0x00000001 39 40 #define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008 41 #define IDT_CFGBLK_ERR_REPORT 0xf20014 42 #define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002 43 44 #define IDT_AUX_PORT_ERR_CAP_EN 0x020000 45 #define IDT_AUX_ERR_REPORT_EN 0xf20018 46 #define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002 47 #define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001 48 49 #define IDT_ISLTL_ADDRESS_CAP 0x021014 50 51 #define IDT_RIO_DOMAIN 0xf20020 52 #define IDT_RIO_DOMAIN_MASK 0x000000ff 53 54 #define IDT_PW_INFO_CSR 0xf20024 55 56 #define IDT_SOFT_RESET 0xf20040 57 #define IDT_SOFT_RESET_REQ 0x00030097 58 59 #define IDT_I2C_MCTRL 0xf20050 60 #define IDT_I2C_MCTRL_GENPW 0x04000000 61 62 #define IDT_JTAG_CTRL 0xf2005c 63 #define IDT_JTAG_CTRL_GENPW 0x00000002 64 65 #define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100) 66 #define IDT_LANE_CTRL_BC 0xffff00 67 #define IDT_LANE_CTRL_GENPW 0x00200000 68 #define IDT_LANE_DFE_1_BC 0xffff18 69 #define IDT_LANE_DFE_2_BC 0xffff1c 70 71 #define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100) 72 #define IDT_PORT_OPS_GENPW 0x08000000 73 #define IDT_PORT_OPS_PL_ELOG 0x00000040 74 #define IDT_PORT_OPS_LL_ELOG 0x00000020 75 #define IDT_PORT_OPS_LT_ELOG 0x00000010 76 #define IDT_PORT_OPS_BC 0xf4ff04 77 78 #define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100) 79 80 #define IDT_ERR_CAP 0xfd0000 81 #define IDT_ERR_CAP_LOG_OVERWR 0x00000004 82 83 #define IDT_ERR_RD 0xfd0004 84 85 #define IDT_DEFAULT_ROUTE 0xde 86 #define IDT_NO_ROUTE 0xdf 87 88 static int 89 idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount, 90 u16 table, u16 route_destid, u8 route_port) 91 { 92 /* 93 * Select routing table to update 94 */ 95 if (table == RIO_GLOBAL_TABLE) 96 table = 0; 97 else 98 table++; 99 100 if (route_port == RIO_INVALID_ROUTE) 101 route_port = IDT_DEFAULT_ROUTE; 102 103 rio_mport_write_config_32(mport, destid, hopcount, 104 LOCAL_RTE_CONF_DESTID_SEL, table); 105 106 /* 107 * Program destination port for the specified destID 108 */ 109 rio_mport_write_config_32(mport, destid, hopcount, 110 RIO_STD_RTE_CONF_DESTID_SEL_CSR, 111 (u32)route_destid); 112 113 rio_mport_write_config_32(mport, destid, hopcount, 114 RIO_STD_RTE_CONF_PORT_SEL_CSR, 115 (u32)route_port); 116 udelay(10); 117 118 return 0; 119 } 120 121 static int 122 idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount, 123 u16 table, u16 route_destid, u8 *route_port) 124 { 125 u32 result; 126 127 /* 128 * Select routing table to read 129 */ 130 if (table == RIO_GLOBAL_TABLE) 131 table = 0; 132 else 133 table++; 134 135 rio_mport_write_config_32(mport, destid, hopcount, 136 LOCAL_RTE_CONF_DESTID_SEL, table); 137 138 rio_mport_write_config_32(mport, destid, hopcount, 139 RIO_STD_RTE_CONF_DESTID_SEL_CSR, 140 route_destid); 141 142 rio_mport_read_config_32(mport, destid, hopcount, 143 RIO_STD_RTE_CONF_PORT_SEL_CSR, &result); 144 145 if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result) 146 *route_port = RIO_INVALID_ROUTE; 147 else 148 *route_port = (u8)result; 149 150 return 0; 151 } 152 153 static int 154 idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount, 155 u16 table) 156 { 157 u32 i; 158 159 /* 160 * Select routing table to read 161 */ 162 if (table == RIO_GLOBAL_TABLE) 163 table = 0; 164 else 165 table++; 166 167 rio_mport_write_config_32(mport, destid, hopcount, 168 LOCAL_RTE_CONF_DESTID_SEL, table); 169 170 for (i = RIO_STD_RTE_CONF_EXTCFGEN; 171 i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) { 172 rio_mport_write_config_32(mport, destid, hopcount, 173 RIO_STD_RTE_CONF_DESTID_SEL_CSR, i); 174 rio_mport_write_config_32(mport, destid, hopcount, 175 RIO_STD_RTE_CONF_PORT_SEL_CSR, 176 (IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) | 177 (IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE); 178 i += 4; 179 } 180 181 return 0; 182 } 183 184 185 static int 186 idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount, 187 u8 sw_domain) 188 { 189 /* 190 * Switch domain configuration operates only at global level 191 */ 192 rio_mport_write_config_32(mport, destid, hopcount, 193 IDT_RIO_DOMAIN, (u32)sw_domain); 194 return 0; 195 } 196 197 static int 198 idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount, 199 u8 *sw_domain) 200 { 201 u32 regval; 202 203 /* 204 * Switch domain configuration operates only at global level 205 */ 206 rio_mport_read_config_32(mport, destid, hopcount, 207 IDT_RIO_DOMAIN, ®val); 208 209 *sw_domain = (u8)(regval & 0xff); 210 211 return 0; 212 } 213 214 static int 215 idtg2_em_init(struct rio_dev *rdev) 216 { 217 u32 regval; 218 int i, tmp; 219 220 /* 221 * This routine performs device-specific initialization only. 222 * All standard EM configuration should be performed at upper level. 223 */ 224 225 pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); 226 227 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */ 228 rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000); 229 230 /* 231 * Configure LT LAYER error reporting. 232 */ 233 234 /* Enable standard (RIO.p8) error reporting */ 235 rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN, 236 REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR | 237 REM_LTL_ERR_UNSUPTR); 238 239 /* Use Port-Writes for LT layer error reporting. 240 * Enable per-port reset 241 */ 242 rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); 243 rio_write_config_32(rdev, IDT_DEV_CTRL_1, 244 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); 245 246 /* 247 * Configure PORT error reporting. 248 */ 249 250 /* Report all RIO.p8 errors supported by device */ 251 rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037); 252 253 /* Configure reporting of implementation specific errors/events */ 254 rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC, 255 IDT_PORT_INIT_TX_ACQUIRED); 256 257 /* Use Port-Writes for port error reporting and enable error logging */ 258 tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); 259 for (i = 0; i < tmp; i++) { 260 rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); 261 rio_write_config_32(rdev, 262 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | 263 IDT_PORT_OPS_PL_ELOG | 264 IDT_PORT_OPS_LL_ELOG | 265 IDT_PORT_OPS_LT_ELOG); 266 } 267 /* Overwrite error log if full */ 268 rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR); 269 270 /* 271 * Configure LANE error reporting. 272 */ 273 274 /* Disable line error reporting */ 275 rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0); 276 277 /* Use Port-Writes for lane error reporting (when enabled) 278 * (do per-lane update because lanes may have different configuration) 279 */ 280 tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; 281 for (i = 0; i < tmp; i++) { 282 rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); 283 rio_write_config_32(rdev, IDT_LANE_CTRL(i), 284 regval | IDT_LANE_CTRL_GENPW); 285 } 286 287 /* 288 * Configure AUX error reporting. 289 */ 290 291 /* Disable JTAG and I2C Error capture */ 292 rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0); 293 294 /* Disable JTAG and I2C Error reporting/logging */ 295 rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0); 296 297 /* Disable Port-Write notification from JTAG */ 298 rio_write_config_32(rdev, IDT_JTAG_CTRL, 0); 299 300 /* Disable Port-Write notification from I2C */ 301 rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); 302 rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); 303 304 /* 305 * Configure CFG_BLK error reporting. 306 */ 307 308 /* Disable Configuration Block error capture */ 309 rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0); 310 311 /* Disable Port-Writes for Configuration Block error reporting */ 312 rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); 313 rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT, 314 regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); 315 316 /* set TVAL = ~50us */ 317 rio_write_config_32(rdev, 318 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); 319 320 return 0; 321 } 322 323 static int 324 idtg2_em_handler(struct rio_dev *rdev, u8 portnum) 325 { 326 u32 regval, em_perrdet, em_ltlerrdet; 327 328 rio_read_config_32(rdev, 329 rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); 330 if (em_ltlerrdet) { 331 /* Service Logical/Transport Layer Error(s) */ 332 if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { 333 /* Implementation specific error reported */ 334 rio_read_config_32(rdev, 335 IDT_ISLTL_ADDRESS_CAP, ®val); 336 337 pr_debug("RIO: %s Implementation Specific LTL errors" \ 338 " 0x%x @(0x%x)\n", 339 rio_name(rdev), em_ltlerrdet, regval); 340 341 /* Clear implementation specific address capture CSR */ 342 rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); 343 344 } 345 } 346 347 rio_read_config_32(rdev, 348 rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); 349 if (em_perrdet) { 350 /* Service Port-Level Error(s) */ 351 if (em_perrdet & REM_PED_IMPL_SPEC) { 352 /* Implementation Specific port error reported */ 353 354 /* Get IS errors reported */ 355 rio_read_config_32(rdev, 356 IDT_PORT_ISERR_DET(portnum), ®val); 357 358 pr_debug("RIO: %s Implementation Specific Port" \ 359 " errors 0x%x\n", rio_name(rdev), regval); 360 361 /* Clear all implementation specific events */ 362 rio_write_config_32(rdev, 363 IDT_PORT_ISERR_DET(portnum), 0); 364 } 365 } 366 367 return 0; 368 } 369 370 static ssize_t 371 idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf) 372 { 373 struct rio_dev *rdev = to_rio_dev(dev); 374 ssize_t len = 0; 375 u32 regval; 376 377 while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) { 378 if (!regval) /* 0 = end of log */ 379 break; 380 len += snprintf(buf + len, PAGE_SIZE - len, 381 "%08x\n", regval); 382 if (len >= (PAGE_SIZE - 10)) 383 break; 384 } 385 386 return len; 387 } 388 389 static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL); 390 391 static int idtg2_sysfs(struct rio_dev *rdev, bool create) 392 { 393 struct device *dev = &rdev->dev; 394 int err = 0; 395 396 if (create) { 397 /* Initialize sysfs entries */ 398 err = device_create_file(dev, &dev_attr_errlog); 399 if (err) 400 dev_err(dev, "Unable create sysfs errlog file\n"); 401 } else 402 device_remove_file(dev, &dev_attr_errlog); 403 404 return err; 405 } 406 407 static struct rio_switch_ops idtg2_switch_ops = { 408 .owner = THIS_MODULE, 409 .add_entry = idtg2_route_add_entry, 410 .get_entry = idtg2_route_get_entry, 411 .clr_table = idtg2_route_clr_table, 412 .set_domain = idtg2_set_domain, 413 .get_domain = idtg2_get_domain, 414 .em_init = idtg2_em_init, 415 .em_handle = idtg2_em_handler, 416 }; 417 418 static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id) 419 { 420 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); 421 422 spin_lock(&rdev->rswitch->lock); 423 424 if (rdev->rswitch->ops) { 425 spin_unlock(&rdev->rswitch->lock); 426 return -EINVAL; 427 } 428 429 rdev->rswitch->ops = &idtg2_switch_ops; 430 431 if (rdev->do_enum) { 432 /* Ensure that default routing is disabled on startup */ 433 rio_write_config_32(rdev, 434 RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); 435 } 436 437 /* Create device-specific sysfs attributes */ 438 idtg2_sysfs(rdev, true); 439 440 spin_unlock(&rdev->rswitch->lock); 441 return 0; 442 } 443 444 static void idtg2_remove(struct rio_dev *rdev) 445 { 446 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); 447 spin_lock(&rdev->rswitch->lock); 448 if (rdev->rswitch->ops != &idtg2_switch_ops) { 449 spin_unlock(&rdev->rswitch->lock); 450 return; 451 } 452 rdev->rswitch->ops = NULL; 453 454 /* Remove device-specific sysfs attributes */ 455 idtg2_sysfs(rdev, false); 456 457 spin_unlock(&rdev->rswitch->lock); 458 } 459 460 static struct rio_device_id idtg2_id_table[] = { 461 {RIO_DEVICE(RIO_DID_IDTCPS1848, RIO_VID_IDT)}, 462 {RIO_DEVICE(RIO_DID_IDTCPS1616, RIO_VID_IDT)}, 463 {RIO_DEVICE(RIO_DID_IDTVPS1616, RIO_VID_IDT)}, 464 {RIO_DEVICE(RIO_DID_IDTSPS1616, RIO_VID_IDT)}, 465 {RIO_DEVICE(RIO_DID_IDTCPS1432, RIO_VID_IDT)}, 466 { 0, } /* terminate list */ 467 }; 468 469 static struct rio_driver idtg2_driver = { 470 .name = "idt_gen2", 471 .id_table = idtg2_id_table, 472 .probe = idtg2_probe, 473 .remove = idtg2_remove, 474 }; 475 476 static int __init idtg2_init(void) 477 { 478 return rio_register_driver(&idtg2_driver); 479 } 480 481 static void __exit idtg2_exit(void) 482 { 483 pr_debug("RIO: %s\n", __func__); 484 rio_unregister_driver(&idtg2_driver); 485 pr_debug("RIO: %s done\n", __func__); 486 } 487 488 device_initcall(idtg2_init); 489 module_exit(idtg2_exit); 490 491 MODULE_DESCRIPTION("IDT CPS Gen.2 Serial RapidIO switch family driver"); 492 MODULE_AUTHOR("Integrated Device Technology, Inc."); 493 MODULE_LICENSE("GPL"); 494