1 /* 2 * Tsi721 PCIExpress-to-SRIO bridge definitions 3 * 4 * Copyright 2011, Integrated Device Technology, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 59 18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #ifndef __TSI721_H 22 #define __TSI721_H 23 24 /* Debug output filtering masks */ 25 enum { 26 DBG_NONE = 0, 27 DBG_INIT = BIT(0), /* driver init */ 28 DBG_EXIT = BIT(1), /* driver exit */ 29 DBG_MPORT = BIT(2), /* mport add/remove */ 30 DBG_MAINT = BIT(3), /* maintenance ops messages */ 31 DBG_DMA = BIT(4), /* DMA transfer messages */ 32 DBG_DMAV = BIT(5), /* verbose DMA transfer messages */ 33 DBG_IBW = BIT(6), /* inbound window */ 34 DBG_EVENT = BIT(7), /* event handling messages */ 35 DBG_OBW = BIT(8), /* outbound window messages */ 36 DBG_DBELL = BIT(9), /* doorbell messages */ 37 DBG_OMSG = BIT(10), /* doorbell messages */ 38 DBG_IMSG = BIT(11), /* doorbell messages */ 39 DBG_ALL = ~0, 40 }; 41 42 #ifdef DEBUG 43 extern u32 tsi_dbg_level; 44 45 #define tsi_debug(level, dev, fmt, arg...) \ 46 do { \ 47 if (DBG_##level & tsi_dbg_level) \ 48 dev_dbg(dev, "%s: " fmt "\n", __func__, ##arg); \ 49 } while (0) 50 #else 51 #define tsi_debug(level, dev, fmt, arg...) \ 52 no_printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##arg) 53 #endif 54 55 #define tsi_info(dev, fmt, arg...) \ 56 dev_info(dev, "%s: " fmt "\n", __func__, ##arg) 57 58 #define tsi_warn(dev, fmt, arg...) \ 59 dev_warn(dev, "%s: WARNING " fmt "\n", __func__, ##arg) 60 61 #define tsi_err(dev, fmt, arg...) \ 62 dev_err(dev, "%s: ERROR " fmt "\n", __func__, ##arg) 63 64 #define DRV_NAME "tsi721" 65 66 #define DEFAULT_HOPCOUNT 0xff 67 #define DEFAULT_DESTID 0xff 68 69 /* PCI device ID */ 70 #define PCI_DEVICE_ID_TSI721 0x80ab 71 72 #define BAR_0 0 73 #define BAR_1 1 74 #define BAR_2 2 75 #define BAR_4 4 76 77 #define TSI721_PC2SR_BARS 2 78 #define TSI721_PC2SR_WINS 8 79 #define TSI721_PC2SR_ZONES 8 80 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */ 81 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */ 82 #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */ 83 84 /* Memory space sizes */ 85 #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */ 86 #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */ 87 88 #define RIO_TT_CODE_8 0x00000000 89 #define RIO_TT_CODE_16 0x00000001 90 91 #define TSI721_DMA_MAXCH 8 92 #define TSI721_DMA_MINSTSSZ 32 93 #define TSI721_DMA_STSBLKSZ 8 94 95 #define TSI721_SRIO_MAXCH 8 96 97 #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3]) 98 #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5]) 99 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1]) 100 101 #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */ 102 103 /* Register definitions */ 104 105 /* 106 * Registers in PCIe configuration space 107 */ 108 109 #define TSI721_PCIECFG_MSIXTBL 0x0a4 110 #define TSI721_MSIXTBL_OFFSET 0x2c000 111 #define TSI721_PCIECFG_MSIXPBA 0x0a8 112 #define TSI721_MSIXPBA_OFFSET 0x2a000 113 #define TSI721_PCIECFG_EPCTL 0x400 114 115 /* 116 * Event Management Registers 117 */ 118 119 #define TSI721_RIO_EM_INT_STAT 0x10910 120 #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000 121 122 #define TSI721_RIO_EM_INT_ENABLE 0x10914 123 #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000 124 125 #define TSI721_RIO_EM_DEV_INT_EN 0x10930 126 #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001 127 128 /* 129 * Port-Write Block Registers 130 */ 131 132 #define TSI721_RIO_PW_CTL 0x10a04 133 #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000 134 #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28) 135 #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28) 136 #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29) 137 #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30) 138 #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31) 139 #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000 140 #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000 141 #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000 142 143 #define TSI721_RIO_PW_RX_STAT 0x10a10 144 #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000 145 #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100 146 #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008 147 #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004 148 #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002 149 #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001 150 151 #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4) 152 153 /* 154 * Inbound Doorbells 155 */ 156 157 #define TSI721_IDB_ENTRY_SIZE 64 158 159 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000) 160 #define TSI721_IDQ_SUSPEND 0x00000002 161 #define TSI721_IDQ_INIT 0x00000001 162 163 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000) 164 #define TSI721_IDQ_RUN 0x00200000 165 166 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000) 167 #define TSI721_IDQ_MASK_MASK 0xffff0000 168 #define TSI721_IDQ_MASK_PATT 0x0000ffff 169 170 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000) 171 #define TSI721_IDQ_RP_PTR 0x0007ffff 172 173 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000) 174 #define TSI721_IDQ_WP_PTR 0x0007ffff 175 176 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000) 177 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0 178 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000) 179 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000) 180 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4) 181 #define TSI721_IDQ_SIZE_MIN 512 182 #define TSI721_IDQ_SIZE_MAX (512 * 1024) 183 184 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000) 185 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000) 186 #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000) 187 #define TSI721_SR_CHINT_ODBOK 0x00000020 188 #define TSI721_SR_CHINT_IDBQRCV 0x00000010 189 #define TSI721_SR_CHINT_SUSP 0x00000008 190 #define TSI721_SR_CHINT_ODBTO 0x00000004 191 #define TSI721_SR_CHINT_ODBRTRY 0x00000002 192 #define TSI721_SR_CHINT_ODBERR 0x00000001 193 #define TSI721_SR_CHINT_ALL 0x0000003f 194 195 #define TSI721_IBWIN_NUM 8 196 197 #define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20) 198 #define TSI721_IBWIN_LB_BA 0xfffff000 199 #define TSI721_IBWIN_LB_WEN 0x00000001 200 201 #define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20) 202 #define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20) 203 #define TSI721_IBWIN_SZ_SIZE 0x00001f00 204 #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12) 205 206 #define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20) 207 #define TSI721_IBWIN_TLA_ADD 0xfffff000 208 #define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20) 209 210 #define TSI721_SR2PC_GEN_INTE 0x29800 211 #define TSI721_SR2PC_PWE 0x29804 212 #define TSI721_SR2PC_GEN_INT 0x29808 213 214 #define TSI721_DEV_INTE 0x29840 215 #define TSI721_DEV_INT 0x29844 216 #define TSI721_DEV_INTSET 0x29848 217 #define TSI721_DEV_INT_BDMA_CH 0x00002000 218 #define TSI721_DEV_INT_BDMA_NCH 0x00001000 219 #define TSI721_DEV_INT_SMSG_CH 0x00000800 220 #define TSI721_DEV_INT_SMSG_NCH 0x00000400 221 #define TSI721_DEV_INT_SR2PC_CH 0x00000200 222 #define TSI721_DEV_INT_SRIO 0x00000020 223 224 #define TSI721_DEV_CHAN_INTE 0x2984c 225 #define TSI721_DEV_CHAN_INT 0x29850 226 227 #define TSI721_INT_SR2PC_CHAN_M 0xff000000 228 #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x))) 229 #define TSI721_INT_IMSG_CHAN_M 0x00ff0000 230 #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x))) 231 #define TSI721_INT_OMSG_CHAN_M 0x0000ff00 232 #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x))) 233 #define TSI721_INT_BDMA_CHAN_M 0x000000ff 234 #define TSI721_INT_BDMA_CHAN(x) (1 << (x)) 235 236 /* 237 * PC2SR block registers 238 */ 239 #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS 240 241 #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20) 242 #define TSI721_OBWINLB_BA 0xffff8000 243 #define TSI721_OBWINLB_WEN 0x00000001 244 245 #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20) 246 247 #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20) 248 #define TSI721_OBWINSZ_SIZE 0x00001f00 249 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15) 250 251 #define TSI721_ZONE_SEL 0x41300 252 #define TSI721_ZONE_SEL_RD_WRB 0x00020000 253 #define TSI721_ZONE_SEL_GO 0x00010000 254 #define TSI721_ZONE_SEL_WIN 0x00000038 255 #define TSI721_ZONE_SEL_ZONE 0x00000007 256 257 #define TSI721_LUT_DATA0 0x41304 258 #define TSI721_LUT_DATA0_ADD 0xfffff000 259 #define TSI721_LUT_DATA0_RDTYPE 0x00000f00 260 #define TSI721_LUT_DATA0_NREAD 0x00000100 261 #define TSI721_LUT_DATA0_MNTRD 0x00000200 262 #define TSI721_LUT_DATA0_RDCRF 0x00000020 263 #define TSI721_LUT_DATA0_WRCRF 0x00000010 264 #define TSI721_LUT_DATA0_WRTYPE 0x0000000f 265 #define TSI721_LUT_DATA0_NWR 0x00000001 266 #define TSI721_LUT_DATA0_MNTWR 0x00000002 267 #define TSI721_LUT_DATA0_NWR_R 0x00000004 268 269 #define TSI721_LUT_DATA1 0x41308 270 271 #define TSI721_LUT_DATA2 0x4130c 272 #define TSI721_LUT_DATA2_HC 0xff000000 273 #define TSI721_LUT_DATA2_ADD65 0x000c0000 274 #define TSI721_LUT_DATA2_TT 0x00030000 275 #define TSI721_LUT_DATA2_DSTID 0x0000ffff 276 277 #define TSI721_PC2SR_INTE 0x41310 278 279 #define TSI721_DEVCTL 0x48004 280 #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004 281 282 #define TSI721_I2C_INT_ENABLE 0x49120 283 284 /* 285 * Block DMA Engine Registers 286 * x = 0..7 287 */ 288 289 #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000) 290 291 #define TSI721_DMAC_DWRCNT 0x000 292 #define TSI721_DMAC_DRDCNT 0x004 293 294 #define TSI721_DMAC_CTL 0x008 295 #define TSI721_DMAC_CTL_SUSP 0x00000002 296 #define TSI721_DMAC_CTL_INIT 0x00000001 297 298 #define TSI721_DMAC_INT 0x00c 299 #define TSI721_DMAC_INT_STFULL 0x00000010 300 #define TSI721_DMAC_INT_DONE 0x00000008 301 #define TSI721_DMAC_INT_SUSP 0x00000004 302 #define TSI721_DMAC_INT_ERR 0x00000002 303 #define TSI721_DMAC_INT_IOFDONE 0x00000001 304 #define TSI721_DMAC_INT_ALL 0x0000001f 305 306 #define TSI721_DMAC_INTSET 0x010 307 308 #define TSI721_DMAC_STS 0x014 309 #define TSI721_DMAC_STS_ABORT 0x00400000 310 #define TSI721_DMAC_STS_RUN 0x00200000 311 #define TSI721_DMAC_STS_CS 0x001f0000 312 313 #define TSI721_DMAC_INTE 0x018 314 315 #define TSI721_DMAC_DPTRL 0x024 316 #define TSI721_DMAC_DPTRL_MASK 0xffffffe0 317 318 #define TSI721_DMAC_DPTRH 0x028 319 320 #define TSI721_DMAC_DSBL 0x02c 321 #define TSI721_DMAC_DSBL_MASK 0xffffffc0 322 323 #define TSI721_DMAC_DSBH 0x030 324 325 #define TSI721_DMAC_DSSZ 0x034 326 #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f 327 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4) 328 329 #define TSI721_DMAC_DSRP 0x038 330 #define TSI721_DMAC_DSRP_MASK 0x0007ffff 331 332 #define TSI721_DMAC_DSWP 0x03c 333 #define TSI721_DMAC_DSWP_MASK 0x0007ffff 334 335 #define TSI721_BDMA_INTE 0x5f000 336 337 /* 338 * Messaging definitions 339 */ 340 #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE 341 #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE 342 #define TSI721_IMSG_MAXCH 8 343 #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH 344 #define TSI721_IMSGD_MIN_RING_SIZE 32 345 #define TSI721_IMSGD_RING_SIZE 512 346 347 #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */ 348 #define TSI721_OMSGD_MIN_RING_SIZE 32 349 #define TSI721_OMSGD_RING_SIZE 512 350 351 /* 352 * Outbound Messaging Engine Registers 353 * x = 0..7 354 */ 355 356 #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000) 357 358 #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000) 359 360 #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000) 361 #define TSI721_OBDMAC_CTL_MASK 0x00000007 362 #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004 363 #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002 364 #define TSI721_OBDMAC_CTL_INIT 0x00000001 365 366 #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000) 367 #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000) 368 #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000) 369 #define TSI721_OBDMAC_INT_MASK 0x0000001F 370 #define TSI721_OBDMAC_INT_ST_FULL 0x00000010 371 #define TSI721_OBDMAC_INT_DONE 0x00000008 372 #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004 373 #define TSI721_OBDMAC_INT_ERROR 0x00000002 374 #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001 375 #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK 376 377 #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000) 378 #define TSI721_OBDMAC_STS_MASK 0x007f0000 379 #define TSI721_OBDMAC_STS_ABORT 0x00400000 380 #define TSI721_OBDMAC_STS_RUN 0x00200000 381 #define TSI721_OBDMAC_STS_CS 0x001f0000 382 383 #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000) 384 #define TSI721_OBDMAC_PWE_MASK 0x00000002 385 #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002 386 387 #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000) 388 #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0 389 390 #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000) 391 #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff 392 393 #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000) 394 #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0 395 396 #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000) 397 #define TSI721_OBDMAC_DSBH_MASK 0xffffffff 398 399 #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000) 400 #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f 401 402 #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000) 403 #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff 404 405 #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000) 406 #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff 407 408 #define TSI721_RQRPTO 0x60010 409 #define TSI721_RQRPTO_MASK 0x00ffffff 410 #define TSI721_RQRPTO_VAL 400 /* Response TO value */ 411 412 /* 413 * Inbound Messaging Engine Registers 414 * x = 0..7 415 */ 416 417 #define TSI721_IB_DEVID_GLOBAL 0xffff 418 #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000) 419 #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0 420 421 #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000) 422 #define TSI721_IBDMAC_FQBH_MASK 0xffffffff 423 424 #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE 425 #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000) 426 #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f 427 428 #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000) 429 #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff 430 431 #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000) 432 #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff 433 434 #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000) 435 #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff 436 437 #define TSI721_IB_DEVID 0x60020 438 #define TSI721_IB_DEVID_MASK 0x0000ffff 439 440 #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000) 441 #define TSI721_IBDMAC_CTL_MASK 0x00000003 442 #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002 443 #define TSI721_IBDMAC_CTL_INIT 0x00000001 444 445 #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000) 446 #define TSI721_IBDMAC_STS_MASK 0x007f0000 447 #define TSI721_IBSMAC_STS_ABORT 0x00400000 448 #define TSI721_IBSMAC_STS_RUN 0x00200000 449 #define TSI721_IBSMAC_STS_CS 0x001f0000 450 451 #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000) 452 #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000) 453 #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000) 454 #define TSI721_IBDMAC_INT_MASK 0x0000100f 455 #define TSI721_IBDMAC_INT_SRTO 0x00001000 456 #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008 457 #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004 458 #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002 459 #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001 460 #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK 461 462 #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000) 463 #define TSI721_IBDMAC_PWE_MASK 0x00001700 464 #define TSI721_IBDMAC_PWE_SRTO 0x00001000 465 #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400 466 #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200 467 #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100 468 469 #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000) 470 #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0 471 #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0 472 473 #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000) 474 #define TSI721_IBDMAC_DQBH_MASK 0xffffffff 475 476 #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000) 477 #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff 478 479 #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000) 480 #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff 481 482 #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000) 483 #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f 484 485 /* 486 * Messaging Engine Interrupts 487 */ 488 489 #define TSI721_SMSG_PWE 0x6a004 490 491 #define TSI721_SMSG_INTE 0x6a000 492 #define TSI721_SMSG_INT 0x6a008 493 #define TSI721_SMSG_INTSET 0x6a010 494 #define TSI721_SMSG_INT_MASK 0x0086ffff 495 #define TSI721_SMSG_INT_UNS_RSP 0x00800000 496 #define TSI721_SMSG_INT_ECC_NCOR 0x00040000 497 #define TSI721_SMSG_INT_ECC_COR 0x00020000 498 #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00 499 #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff 500 501 #define TSI721_SMSG_ECC_LOG 0x6a014 502 #define TSI721_SMSG_ECC_LOG_MASK 0x00070007 503 #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000 504 #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007 505 506 #define TSI721_RETRY_GEN_CNT 0x6a100 507 #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff 508 509 #define TSI721_RETRY_RX_CNT 0x6a104 510 #define TSI721_RETRY_RX_CNT_MASK 0xffffffff 511 512 #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4) 513 #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff 514 515 #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4) 516 #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff 517 518 /* 519 * Block DMA Descriptors 520 */ 521 522 struct tsi721_dma_desc { 523 __le32 type_id; 524 525 #define TSI721_DMAD_DEVID 0x0000ffff 526 #define TSI721_DMAD_CRF 0x00010000 527 #define TSI721_DMAD_PRIO 0x00060000 528 #define TSI721_DMAD_RTYPE 0x00780000 529 #define TSI721_DMAD_IOF 0x08000000 530 #define TSI721_DMAD_DTYPE 0xe0000000 531 532 __le32 bcount; 533 534 #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */ 535 #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */ 536 #define TSI721_DMAD_TT 0x0c000000 537 #define TSI721_DMAD_RADDR0 0xc0000000 538 539 union { 540 __le32 raddr_lo; /* if DTYPE == (1 || 2) */ 541 __le32 next_lo; /* if DTYPE == 3 */ 542 }; 543 544 #define TSI721_DMAD_CFGOFF 0x00ffffff 545 #define TSI721_DMAD_HOPCNT 0xff000000 546 547 union { 548 __le32 raddr_hi; /* if DTYPE == (1 || 2) */ 549 __le32 next_hi; /* if DTYPE == 3 */ 550 }; 551 552 union { 553 struct { /* if DTYPE == 1 */ 554 __le32 bufptr_lo; 555 __le32 bufptr_hi; 556 __le32 s_dist; 557 __le32 s_size; 558 } t1; 559 __le32 data[4]; /* if DTYPE == 2 */ 560 u32 reserved[4]; /* if DTYPE == 3 */ 561 }; 562 } __aligned(32); 563 564 /* 565 * Inbound Messaging Descriptor 566 */ 567 struct tsi721_imsg_desc { 568 __le32 type_id; 569 570 #define TSI721_IMD_DEVID 0x0000ffff 571 #define TSI721_IMD_CRF 0x00010000 572 #define TSI721_IMD_PRIO 0x00060000 573 #define TSI721_IMD_TT 0x00180000 574 #define TSI721_IMD_DTYPE 0xe0000000 575 576 __le32 msg_info; 577 578 #define TSI721_IMD_BCOUNT 0x00000ff8 579 #define TSI721_IMD_SSIZE 0x0000f000 580 #define TSI721_IMD_LETER 0x00030000 581 #define TSI721_IMD_XMBOX 0x003c0000 582 #define TSI721_IMD_MBOX 0x00c00000 583 #define TSI721_IMD_CS 0x78000000 584 #define TSI721_IMD_HO 0x80000000 585 586 __le32 bufptr_lo; 587 __le32 bufptr_hi; 588 u32 reserved[12]; 589 590 } __aligned(64); 591 592 /* 593 * Outbound Messaging Descriptor 594 */ 595 struct tsi721_omsg_desc { 596 __le32 type_id; 597 598 #define TSI721_OMD_DEVID 0x0000ffff 599 #define TSI721_OMD_CRF 0x00010000 600 #define TSI721_OMD_PRIO 0x00060000 601 #define TSI721_OMD_IOF 0x08000000 602 #define TSI721_OMD_DTYPE 0xe0000000 603 #define TSI721_OMD_RSRVD 0x17f80000 604 605 __le32 msg_info; 606 607 #define TSI721_OMD_BCOUNT 0x00000ff8 608 #define TSI721_OMD_SSIZE 0x0000f000 609 #define TSI721_OMD_LETER 0x00030000 610 #define TSI721_OMD_XMBOX 0x003c0000 611 #define TSI721_OMD_MBOX 0x00c00000 612 #define TSI721_OMD_TT 0x0c000000 613 614 union { 615 __le32 bufptr_lo; /* if DTYPE == 4 */ 616 __le32 next_lo; /* if DTYPE == 5 */ 617 }; 618 619 union { 620 __le32 bufptr_hi; /* if DTYPE == 4 */ 621 __le32 next_hi; /* if DTYPE == 5 */ 622 }; 623 624 } __aligned(16); 625 626 struct tsi721_dma_sts { 627 __le64 desc_sts[8]; 628 } __aligned(64); 629 630 struct tsi721_desc_sts_fifo { 631 union { 632 __le64 da64; 633 struct { 634 __le32 lo; 635 __le32 hi; 636 } da32; 637 } stat[8]; 638 } __aligned(64); 639 640 /* Descriptor types for BDMA and Messaging blocks */ 641 enum dma_dtype { 642 DTYPE1 = 1, /* Data Transfer DMA Descriptor */ 643 DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */ 644 DTYPE3 = 3, /* Block Pointer DMA Descriptor */ 645 DTYPE4 = 4, /* Outbound Msg DMA Descriptor */ 646 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */ 647 DTYPE6 = 6 /* Inbound Messaging Descriptor */ 648 }; 649 650 enum dma_rtype { 651 NREAD = 0, 652 LAST_NWRITE_R = 1, 653 ALL_NWRITE = 2, 654 ALL_NWRITE_R = 3, 655 MAINT_RD = 4, 656 MAINT_WR = 5 657 }; 658 659 /* 660 * mport Driver Definitions 661 */ 662 #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH 663 664 #define TSI721_DMACH_MAINT 7 /* DMA channel for maint requests */ 665 #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */ 666 667 #define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */ 668 669 #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0) 670 671 enum tsi721_smsg_int_flag { 672 SMSG_INT_NONE = 0x00000000, 673 SMSG_INT_ECC_COR_CH = 0x000000ff, 674 SMSG_INT_ECC_NCOR_CH = 0x0000ff00, 675 SMSG_INT_ECC_COR = 0x00020000, 676 SMSG_INT_ECC_NCOR = 0x00040000, 677 SMSG_INT_UNS_RSP = 0x00800000, 678 SMSG_INT_ALL = 0x0006ffff 679 }; 680 681 /* Structures */ 682 683 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 684 685 #define TSI721_BDMA_MAX_BCOUNT (TSI721_DMAD_BCOUNT1 + 1) 686 687 struct tsi721_tx_desc { 688 struct dma_async_tx_descriptor txd; 689 u16 destid; 690 /* low 64-bits of 66-bit RIO address */ 691 u64 rio_addr; 692 /* upper 2-bits of 66-bit RIO address */ 693 u8 rio_addr_u; 694 enum dma_rtype rtype; 695 struct list_head desc_node; 696 struct scatterlist *sg; 697 unsigned int sg_len; 698 enum dma_status status; 699 }; 700 701 struct tsi721_bdma_chan { 702 int id; 703 void __iomem *regs; 704 int bd_num; /* number of HW buffer descriptors */ 705 void *bd_base; /* start of DMA descriptors */ 706 dma_addr_t bd_phys; 707 void *sts_base; /* start of DMA BD status FIFO */ 708 dma_addr_t sts_phys; 709 int sts_size; 710 u32 sts_rdptr; 711 u32 wr_count; 712 u32 wr_count_next; 713 714 struct dma_chan dchan; 715 struct tsi721_tx_desc *tx_desc; 716 spinlock_t lock; 717 struct tsi721_tx_desc *active_tx; 718 struct list_head queue; 719 struct list_head free_list; 720 struct tasklet_struct tasklet; 721 bool active; 722 }; 723 724 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ 725 726 struct tsi721_bdma_maint { 727 int ch_id; /* BDMA channel number */ 728 int bd_num; /* number of buffer descriptors */ 729 void *bd_base; /* start of DMA descriptors */ 730 dma_addr_t bd_phys; 731 void *sts_base; /* start of DMA BD status FIFO */ 732 dma_addr_t sts_phys; 733 int sts_size; 734 }; 735 736 struct tsi721_imsg_ring { 737 u32 size; 738 /* VA/PA of data buffers for incoming messages */ 739 void *buf_base; 740 dma_addr_t buf_phys; 741 /* VA/PA of circular free buffer list */ 742 void *imfq_base; 743 dma_addr_t imfq_phys; 744 /* VA/PA of Inbound message descriptors */ 745 void *imd_base; 746 dma_addr_t imd_phys; 747 /* Inbound Queue buffer pointers */ 748 void *imq_base[TSI721_IMSGD_RING_SIZE]; 749 750 u32 rx_slot; 751 void *dev_id; 752 u32 fq_wrptr; 753 u32 desc_rdptr; 754 spinlock_t lock; 755 }; 756 757 struct tsi721_omsg_ring { 758 u32 size; 759 /* VA/PA of OB Msg descriptors */ 760 void *omd_base; 761 dma_addr_t omd_phys; 762 /* VA/PA of OB Msg data buffers */ 763 void *omq_base[TSI721_OMSGD_RING_SIZE]; 764 dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE]; 765 /* VA/PA of OB Msg descriptor status FIFO */ 766 void *sts_base; 767 dma_addr_t sts_phys; 768 u32 sts_size; /* # of allocated status entries */ 769 u32 sts_rdptr; 770 771 u32 tx_slot; 772 void *dev_id; 773 u32 wr_count; 774 spinlock_t lock; 775 }; 776 777 enum tsi721_flags { 778 TSI721_USING_MSI = (1 << 0), 779 TSI721_USING_MSIX = (1 << 1), 780 TSI721_IMSGID_SET = (1 << 2), 781 }; 782 783 #ifdef CONFIG_PCI_MSI 784 /* 785 * MSI-X Table Entries (0 ... 69) 786 */ 787 #define TSI721_MSIX_DMACH_DONE(x) (0 + (x)) 788 #define TSI721_MSIX_DMACH_INT(x) (8 + (x)) 789 #define TSI721_MSIX_BDMA_INT 16 790 #define TSI721_MSIX_OMSG_DONE(x) (17 + (x)) 791 #define TSI721_MSIX_OMSG_INT(x) (25 + (x)) 792 #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x)) 793 #define TSI721_MSIX_IMSG_INT(x) (41 + (x)) 794 #define TSI721_MSIX_MSG_INT 49 795 #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x)) 796 #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x)) 797 #define TSI721_MSIX_SR2PC_INT 66 798 #define TSI721_MSIX_PC2SR_INT 67 799 #define TSI721_MSIX_SRIO_MAC_INT 68 800 #define TSI721_MSIX_I2C_INT 69 801 802 /* MSI-X vector and init table entry indexes */ 803 enum tsi721_msix_vect { 804 TSI721_VECT_IDB, 805 TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */ 806 TSI721_VECT_OMB0_DONE, 807 TSI721_VECT_OMB1_DONE, 808 TSI721_VECT_OMB2_DONE, 809 TSI721_VECT_OMB3_DONE, 810 TSI721_VECT_OMB0_INT, 811 TSI721_VECT_OMB1_INT, 812 TSI721_VECT_OMB2_INT, 813 TSI721_VECT_OMB3_INT, 814 TSI721_VECT_IMB0_RCV, 815 TSI721_VECT_IMB1_RCV, 816 TSI721_VECT_IMB2_RCV, 817 TSI721_VECT_IMB3_RCV, 818 TSI721_VECT_IMB0_INT, 819 TSI721_VECT_IMB1_INT, 820 TSI721_VECT_IMB2_INT, 821 TSI721_VECT_IMB3_INT, 822 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 823 TSI721_VECT_DMA0_DONE, 824 TSI721_VECT_DMA1_DONE, 825 TSI721_VECT_DMA2_DONE, 826 TSI721_VECT_DMA3_DONE, 827 TSI721_VECT_DMA4_DONE, 828 TSI721_VECT_DMA5_DONE, 829 TSI721_VECT_DMA6_DONE, 830 TSI721_VECT_DMA7_DONE, 831 TSI721_VECT_DMA0_INT, 832 TSI721_VECT_DMA1_INT, 833 TSI721_VECT_DMA2_INT, 834 TSI721_VECT_DMA3_INT, 835 TSI721_VECT_DMA4_INT, 836 TSI721_VECT_DMA5_INT, 837 TSI721_VECT_DMA6_INT, 838 TSI721_VECT_DMA7_INT, 839 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ 840 TSI721_VECT_MAX 841 }; 842 843 #define IRQ_DEVICE_NAME_MAX 64 844 845 struct msix_irq { 846 u16 vector; 847 char irq_name[IRQ_DEVICE_NAME_MAX]; 848 }; 849 #endif /* CONFIG_PCI_MSI */ 850 851 struct tsi721_ib_win_mapping { 852 struct list_head node; 853 dma_addr_t lstart; 854 }; 855 856 struct tsi721_ib_win { 857 u64 rstart; 858 u32 size; 859 dma_addr_t lstart; 860 bool active; 861 bool xlat; 862 struct list_head mappings; 863 }; 864 865 struct tsi721_obw_bar { 866 u64 base; 867 u64 size; 868 u64 free; 869 }; 870 871 struct tsi721_ob_win { 872 u64 base; 873 u32 size; 874 u16 destid; 875 u64 rstart; 876 bool active; 877 struct tsi721_obw_bar *pbar; 878 }; 879 880 struct tsi721_device { 881 struct pci_dev *pdev; 882 struct rio_mport mport; 883 u32 flags; 884 void __iomem *regs; 885 #ifdef CONFIG_PCI_MSI 886 struct msix_irq msix[TSI721_VECT_MAX]; 887 #endif 888 /* Doorbells */ 889 void __iomem *odb_base; 890 void *idb_base; 891 dma_addr_t idb_dma; 892 struct work_struct idb_work; 893 u32 db_discard_count; 894 895 /* Inbound Port-Write */ 896 struct work_struct pw_work; 897 struct kfifo pw_fifo; 898 spinlock_t pw_fifo_lock; 899 u32 pw_discard_count; 900 901 /* BDMA Engine */ 902 struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */ 903 904 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 905 struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM]; 906 #endif 907 908 /* Inbound Messaging */ 909 int imsg_init[TSI721_IMSG_CHNUM]; 910 struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM]; 911 912 /* Outbound Messaging */ 913 int omsg_init[TSI721_OMSG_CHNUM]; 914 struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM]; 915 916 /* Inbound Mapping Windows */ 917 struct tsi721_ib_win ib_win[TSI721_IBWIN_NUM]; 918 int ibwin_cnt; 919 920 /* Outbound Mapping Windows */ 921 struct tsi721_obw_bar p2r_bar[2]; 922 struct tsi721_ob_win ob_win[TSI721_OBWIN_NUM]; 923 int obwin_cnt; 924 }; 925 926 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 927 extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan); 928 extern int tsi721_register_dma(struct tsi721_device *priv); 929 extern void tsi721_unregister_dma(struct tsi721_device *priv); 930 extern void tsi721_dma_stop_all(struct tsi721_device *priv); 931 #else 932 #define tsi721_dma_stop_all(priv) do {} while (0) 933 #define tsi721_unregister_dma(priv) do {} while (0) 934 #endif 935 936 #endif 937